JPH0450645Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to improvements in bias stabilization circuits for amplifiers and the like.

[Conventional technology] Conventionally, in SEPP type AB class amplifier circuits, a bias current is passed through the transistor in the power amplification stage in order to reduce crossover distortion, and a negative temperature is applied to prevent the transistor from being destroyed due to thermal runaway. Figures 6-a, 6-b, and 6-c are typical circuit examples in which temperature-compensated bias circuits with characteristic characteristics are frequently used.
Reference numerals 1 denote complementary-connected transistors of the power amplification stage, and Darlington-connected output transistors may be arranged at the outputs of the respective transistors.

012, 013, 014 are temperature sensitive elements each having temperature characteristics, and 012 is a temperature sensitive element.
013 is a compensation transistor that utilizes a voltage change between emitters; 013 is a compensation thermistor that utilizes a resistance change due to temperature; 013 is a compensation varistor that utilizes a forward voltage change due to temperature.

In such a temperature compensated bias circuit, it is impossible to directly detect the temperature of the junction of the power amplification stage transistor, so the temperature sensing element is placed close to the transistor case or the heat sink where the transistor is mounted. The temperature of the power amplification stage transistor was detected by attaching it to the position.

[Problems to be solved by the invention] However, with the above configuration, as shown in Figure 7, there is a time delay in the temperature change of the case or heat sink compared to the temperature change of the junction of the power amplification stage transistor. For a signal source whose signal level changes significantly, such as a signal, it is impossible to keep the power amplification stage transistor always in an optimal bias state by following the level change.

For example, when a large level signal changes from a continuous state to a small level signal _t1 , the temperature drop of the heat sink is delayed compared to the temperature drop of the junction of the power amplifier stage transistor, resulting in an underbiased state during that time. becomes.

On the other hand, when a small level signal changes from a continuous state to a large level signal _t2 , the temperature rise of the heat sink is delayed compared to the temperature rise of the junction of the power amplification stage transistor, resulting in an excessive bias state. There was a problem.

[Means for solving the problem] This invention is based on the sum I ₁ + _I 2 of the emitter current I ₁ of the npn transistor and the emitter current I ₂ of the pnp transistor in the power amplification stage of the SEPP power amplifier circuit,
Difference I _L = Absolute value of I ₁ − I ₂ | I _L | Difference between I ₁ + I ₂ − | I _L |
This is a bias stabilization circuit that focuses on the fact that the output signal indicates a bias current value near the zero cross of the output signal, and controls the detected bias current value so that it approaches a predetermined value.

That is, as shown in Figure 3-a, the sum of the emitter currents I ₁ + with respect to the output voltage (31 in the figure)
I ₂ is represented by 32 in the figure, and the dotted line portions of I ₁ and I ₂ are due to bias.

On the other hand, as shown in Figure 3-b, the difference in the emitter current with respect to the output voltage (31 in the figure) is I _L = I ₁ - _{I 2}
is represented by 33 in the figure.

Therefore, near the zero cross of the output voltage, the fourth
As shown in the figure, I ₁ + I ₂ (32 in the figure) and |I _L | (32 in the figure)
3) (34 in the figure) indicates the bias current value.

In order to perform the above operation, this device has a current sum detection circuit that detects the current sum of the emitter current of the npn transistor and the emitter current of the pnp transistor in the power amplification stage of the SEPP power amplification circuit, and a current difference detection circuit that detects the current difference. a detection circuit, an absolute value circuit that obtains the absolute value of the output of the current difference detection circuit, a subtraction circuit that obtains the difference between the output of the current sum detection circuit and the output of the absolute value circuit, and an output of the absolute value circuit. a zero detection circuit that detects the vicinity of zero potential, a sample hold circuit that holds the output of the subtraction circuit near the zero potential using the output of the zero detection circuit, and a reference bias between the value held by the sample hold circuit and the reference bias. The bias stabilization circuit includes a bias control circuit that compares the voltage with a corresponding reference voltage source and controls the bias value of the power amplification stage transistor according to the comparison value.

[Example] In FIG. 1, 9a and 9b are power amplification stage transistors, and are an npn type transistor 9a and a power amplification stage transistor, respectively.
PNP type transistors 9b are complementary connected.

The emitter currents of the transistors 9a and 9b are represented by I ₁ and I ₂ , and the respective current directions are indicated by the arrows.

10 is the output terminal, _r1 output resistance.

1 is a current sum detection circuit that detects the sum of the emitter currents I ₁ and I ₂ , and Figure 2-a shows a concrete example of the circuit; V ₁ is expressed as V ₁ =R ₂ /R ₁ r ₁ (I ₁ +I ₂ ).

2 is a current detection circuit that detects the difference between the emitter currents I ₁ and I ₂ , FIG. V ₂ is expressed as V ₂ =R ₂ /R ₁ r ₁ (I ₁ −I ₂ ).

3 is an absolute value circuit, and a concrete example of the circuit is shown in 2-
Shown in Figure c.

In the figure, 3a and 3b are operational amplifier circuits, and the output voltage V ₃ seen from the output terminal 10 is V ₃ =-|V ₂ |=-R ₂ /R ₁ r ₁ |I ₁ −I ₂ | =- It is expressed as R ₂ /R ₁ r ₁ |I _L |.

4 is a subtraction circuit that obtains the difference between I ₁ + I ₂ and |I _L |, 6 is a sample hold circuit, and 5 is a zero detection circuit.
A concrete example of the circuit is shown in FIG. 2-d.

In the figure, R ₄ and R ₄ constitute an adder circuit, and the output voltage V ₄ seen from the output terminal 10 is V ₄ = V ₁ + V ₃ /2 = R ₂ /2R ₁ r ₁ (I ₁ + I ₂ − | I _L |), and the difference between I ₁ + I ₂ and |I _L | is obtained.

Reference numeral 6b denotes an operational amplifier circuit which provides an output only when the input voltage V ₃ is higher than the voltage V _a .

That is, only when V ₃ is larger than V _a as shown in FIG. 5a, in other words, the output V ₅ (FIG. 5b) is obtained near the zero cross of V ₃ , and the zero cross is detected.

Then, due to the differentiation of _V5 by _C1 and the bias by -B (FIG. 5c), the trigger diode 6a turns on in response to the rise of _Vc and outputs _V4 .

That is, by outputting the voltage _V4 near the zero cross and charging the capacitor _C2 ,
Holds that voltage until the next trigger output is obtained.

The output V ₄ is the differential voltage R ₂ /2R ₁ r ₁ (I ₁ +I ₂ −| _IL |).

However, near the zero cross, I ₁ +
Since I ₂ −|I _L | is the bias current I _b , the previous equation becomes V ₄ =R ₂ /R ₁ r ₁ I _b .

Reference numerals 7 and 8 denote a bias control circuit and a reference voltage source, and a concrete example of the circuit is shown in FIG. 2-e.

In the figure, 8a is an operational amplifier circuit, one input end of which is connected to the sample-and-hold circuit output _V4 , and the other input end to the reference voltage source _Vc .
A light emitting element 8b such as a light emitting diode is connected to the output end.

On the other hand, a light receiving element 11 such as Cds is optically coupled to the light emitting element 8b, and the bias of the transistors 9a and 9b of the power amplification stage can be varied by changing the resistance of the light receiving element 11.

Other combinations of the light emitting element and light receiving element that can be used include a light bulb and CDS, a light emitting diode and a photo FET, a light emitting diode and a photo diode, a light emitting diode and a photo transistor (diode connection), and the like.

In the above circuit, the bias current setting value is I _B
Then, the voltage V _B to be input as the reference voltage corresponding to the set value of the bias current to the negative input of the amplifier circuit 8a is expressed by V _B =R ₂ /R ₁ r ₁ I _b .

Therefore, the voltage V _C of the reference voltage source for obtaining the reference voltage is set to V _C =R ₆ +R ₇ /R ₇ ×R ₂ /R ₁ r ₁ I _b .

Therefore, the output of the amplifier circuit 8a is the difference voltage between _V4 and _VB , and the optical output of the light emitting element changes due to the difference voltage, and the resistance change between the light emitting element and the optically coupled light receiving element changes the power amplification stage. The bias current of the transistor is controlled so as to approach the set bias current I _b .

[Effects of the invention] According to the bias stabilization circuit of this invention described above, the bias current value is directly controlled instead of controlling the bias value by temperature changes of the transistor case or heat sink as in the conventional case. Since the bias current is detected and controlled so that it approaches a predetermined reference bias current value, it has sufficient tracking ability even with large fluctuations in the input level to the transistor, and the bias current is controlled so that it approaches a predetermined reference bias current value. Since the predetermined bias value can be quickly set, the predetermined bias current value can always be maintained, and as a result, it has the advantage of being able to exhibit a more accurate amplification effect than in the past.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the bias stabilizing circuit of this invention, Fig. 2-a is a specific circuit diagram of the current sum detection circuit, Fig. 2-b is a specific circuit diagram of the current difference detection circuit, and Fig. 2-b is a specific circuit diagram of the current difference detection circuit. Figure 2-c is a specific circuit diagram of the absolute value circuit, Figure 2-d is a specific circuit diagram of the subtraction circuit, zero detection circuit and sample hold circuit, and Figure 2-e is a specific circuit diagram of the bias control circuit and reference voltage source circuit. A specific circuit diagram, FIG. 3-a, FIG. 3-b, and FIG. 4 are waveform diagrams each explaining the relationship between the output voltage and bias, and FIG. 5 is a waveform diagram explaining the operation of the sample-and-hold circuit. Figure 6-a, Figure 6-b and Figure 6-
FIG. c is a diagram of a conventional bias stabilizing circuit, and FIG. 7 is a waveform diagram showing the operation of the conventional bias stabilizing circuit. 9a is an npn type transistor, 9b is a pnp type transistor, 1 is a current sum detection circuit, 2 is a current difference detection circuit, 3 is an absolute value circuit, 4 is a subtraction circuit, 5 is a zero detection circuit, 6 is a sample hold circuit, 7 is a reference voltage source, and 8 is a bias control circuit.

Claims (1)

[Scope of utility model registration request] A current sum detection circuit 1 detecting the current sum of the emitter current of the power amplification stage npn transistor 9a and the emitter current of the pnp transistor 9b of the SEPP power amplifier circuit, and a current difference detection circuit 2 detecting the current difference; an absolute value circuit 3 that obtains the absolute value of the output of the current difference detection circuit 2; a subtraction circuit 4 that obtains the difference between the output of the current sum detection circuit 1 and the output of the absolute value circuit 3; and the absolute value circuit 3. a zero detection circuit 5 that detects the vicinity of the zero potential of the output; a sample hold circuit 6 that holds the output of the subtraction circuit 4 near the zero potential by the output of the zero detection circuit 5; and the reference voltage source 7 corresponding to the reference bias, and depending on the comparison value, the power amplification stage transistors 9a,
Bias control circuit 8 that controls the bias value of 9b
A bias stabilization circuit comprising: