JPH0450536B2 - - Google Patents

Info

Publication number
JPH0450536B2
JPH0450536B2 JP58014326A JP1432683A JPH0450536B2 JP H0450536 B2 JPH0450536 B2 JP H0450536B2 JP 58014326 A JP58014326 A JP 58014326A JP 1432683 A JP1432683 A JP 1432683A JP H0450536 B2 JPH0450536 B2 JP H0450536B2
Authority
JP
Japan
Prior art keywords
program
measurement
test
integrated circuit
test pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58014326A
Other languages
Japanese (ja)
Other versions
JPS59141077A (en
Inventor
Nobuo Arai
Masao Kishibe
Kazuhiko Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ando Electric Co Ltd
Original Assignee
Ando Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ando Electric Co Ltd filed Critical Ando Electric Co Ltd
Priority to JP58014326A priority Critical patent/JPS59141077A/en
Publication of JPS59141077A publication Critical patent/JPS59141077A/en
Publication of JPH0450536B2 publication Critical patent/JPH0450536B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316Testing of analog circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 この発明は、完成した集積回路単体の試験をす
る場合、集積回路の中に異なる品種がある場合で
も、これらの単体に対応する測定プログラムとテ
ストパターンを転送することができる集積回路測
定装置についてのものである。
[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention provides a method for testing completed integrated circuit units, even if there are different types of integrated circuits, by using a measurement program and a measurement program corresponding to these units. It is about an integrated circuit measurement device that can transfer test patterns.

(b) 発明の目的 集積回路単体を試験する場合は、通常同じ品種
のものをまとめて試験し、品種の異なる他の集積
回路を試験するときは別のプログラムに変えて試
験する。
(b) Purpose of the Invention When testing individual integrated circuits, usually all of the same type are tested together, and when testing other integrated circuits of different types, a different program is used.

しかし、最近では多品種少量生産のケースが多
くなつており、品種の異なるごとにプログラムを
変えるのでは、測定能率が下がるという問題があ
る。
However, recently there have been many cases of high-mix, low-volume production, and changing the program for each different product poses a problem in that measurement efficiency decreases.

この発明は、多種類の集積回路を測定する場合
に、その集積回路の特性を知るために予備試験を
行ない、予備試験の結果に対して測定プログラム
を編集し、集積回路の品種に応じた試験をするこ
とができる測定装置を提供するものである。
When measuring many types of integrated circuits, this invention conducts a preliminary test to know the characteristics of the integrated circuit, edits a measurement program based on the results of the preliminary test, and performs a test according to the type of integrated circuit. The present invention provides a measuring device that can perform the following measurements.

(c) 発明の実施例 まず、この発明による実施例の構成図を第1図
に示す。
(c) Embodiment of the Invention First, FIG. 1 shows a configuration diagram of an embodiment of the invention.

第1図では、品種選択のためのテストパターン
をテストパターン発生部2で用意する。例えば、
品種が3つの場合にはA=100、B=010、C=
001などのテストパターンを使用する。このテス
トパターンを使つて測定しようとする集積回路1
の予備試験を予備試験測定部3で行ない、テスト
パターンに対する応答により集積回路1の品種を
選別する。
In FIG. 1, a test pattern generator 2 prepares a test pattern for product selection. for example,
If there are three varieties, A=100, B=010, C=
Use a test pattern such as 001. Integrated circuit 1 to be measured using this test pattern
A preliminary test is carried out in the preliminary test measuring section 3, and the type of integrated circuit 1 is selected based on the response to the test pattern.

予備試験測定部3で集積回路1の品種を選別す
ると、その品種に対応する符号を品種選別対応表
4から選び出す。
When the type of integrated circuit 1 is selected by the preliminary test measuring section 3, a code corresponding to the type is selected from the type selection correspondence table 4.

次に、集積回路1の品種と品種選別対応表4、
編集表5の一例を第2図と第3図に示す。
Next, the types of integrated circuits 1 and type selection correspondence table 4,
An example of the compilation table 5 is shown in FIGS. 2 and 3.

第2図は品種選別対応表であり、品種がAのと
きはHGになる。
Figure 2 is a variety classification correspondence table, and when the variety is A, it becomes HG.

第3図は編集表5のうちHGの部分の測定プロ
グラム・テストパターン名P〜Tを示したもので
ある。
FIG. 3 shows the measurement program/test pattern names P to T in the HG portion of the compilation table 5.

編集表5から測定プログラム・テストパターン
名P〜Tを選び出すと、高速処理格納部6,7に
第3図右辺の名前があるかどうかをサーチする。
ある場合は測定プログラム・テストパターン編集
部11から測定開始指示部12を介して測定部1
3にテスト信号を転送する。ない場合は大容量格
納部8から高速処理格納部6,7へ転送する。
When the measurement program/test pattern names P to T are selected from the compilation table 5, a search is made to see if the names shown on the right side of FIG. 3 exist in the high-speed processing storage sections 6 and 7.
If there is, the measurement program/test pattern editing section 11 sends the information to the measurement section 1 via the measurement start instruction section 12.
Transfer the test signal to 3. If not, it is transferred from the large-capacity storage section 8 to the high-speed processing storage sections 6 and 7.

この場合、高速処理格納部6,7に空き領域が
あれば、この空き領域に大容量格納部8から転送
処理部9の指令により転送するが、空き領域がな
い場合は編集表5で使用しないプログラムを不要
プログラム処理部10の指令により消去し、空き
領域をつくる。
In this case, if there is free space in the high-speed processing storage units 6 and 7, the data will be transferred from the large-capacity storage unit 8 to this free space according to a command from the transfer processing unit 9, but if there is no free space, it will not be used in the editing table 5. The program is erased according to a command from the unnecessary program processing section 10 to create a free area.

測定が終ると、測定部13は測定結果と測定終
了信号を制御部14へ送る。
When the measurement is completed, the measurement section 13 sends the measurement result and a measurement end signal to the control section 14.

制御部14は測定結果を記録し、次に測定する
集積回路を測定部13に接続する。
The control unit 14 records the measurement results and connects the integrated circuit to be measured next to the measurement unit 13.

制御部14によつて次に測定する集積回路を測
定部13に接続すると、この集積回路にテストパ
ターンを送つて品種を選別する。
When the integrated circuit to be next measured is connected to the measuring section 13 by the control section 14, a test pattern is sent to this integrated circuit to select the type.

このようにして、集積回路の品種が異なる場合
でも、各集積回路への測定プログラムを編集しな
がら測定を続けていく。
In this way, even if the types of integrated circuits are different, measurements can be continued while editing the measurement program for each integrated circuit.

これらの関係をフローチヤートで示すと、第4
図のようになる。
If these relationships are shown in a flowchart, the fourth
It will look like the figure.

第1図〜第4図に示すように、テストパターン
による予備試験で測定しようとする集積回路の品
種を選別し、この選別内容に対応して編集表5か
ら測定プログラム・テストパターンを選び出して
編集し、測定部13で集積回路単位の測定をす
る。
As shown in Figures 1 to 4, the type of integrated circuit to be measured is selected in a preliminary test using test patterns, and a measurement program/test pattern is selected from Edit Table 5 in accordance with the selection contents and edited. Then, the measurement unit 13 measures each integrated circuit.

(d) 発明の効果 この発明によれば、測定しようとする集積回路
の品種を予備試験で選別し、品種に対応した測定
プログラムとテストパターンを編集するので、品
種の異なる集積回路が混在していても各集積回路
に合つた測定プログラムとテストパターンを供給
することができ、多品種の集積回路を高速で測定
することができる。
(d) Effects of the Invention According to this invention, the type of integrated circuit to be measured is selected through a preliminary test, and the measurement program and test pattern corresponding to the type are edited. It is possible to supply measurement programs and test patterns suitable for each integrated circuit even if the test is not carried out, and it is possible to measure a wide variety of integrated circuits at high speed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明による実施例の構成図、第2
図は品種選別対応表の一例を示す図、第3図は編
集表5の測定プログラム・テストパターン名の一
例を示す図、第4図は第1図〜第3図のフローチ
ヤート。 1……集積回路単体、2……テストパターン発
生部、3……予備試験測定部、4……品種選別対
応表、5……編集表、6,7……高速処理格納
部、8……大容量格納部、9……転送処理部、1
0……不要プログラム処理部、11……測定プロ
グラム・テストパターン編集部、12……測定開
始指示部、13……測定部、14……制御部。
FIG. 1 is a configuration diagram of an embodiment according to the present invention, and FIG.
3 is a diagram showing an example of the name of the measurement program/test pattern of compilation table 5. FIG. 4 is a flowchart of FIGS. 1 to 3. 1...Integrated circuit unit, 2...Test pattern generation section, 3...Preliminary test measurement section, 4...Type selection correspondence table, 5...Editing table, 6, 7...High speed processing storage section, 8... Large capacity storage unit, 9...Transfer processing unit, 1
0...Unnecessary program processing section, 11...Measurement program/test pattern editing section, 12...Measurement start instruction section, 13...Measurement section, 14...Control section.

Claims (1)

【特許請求の範囲】 1 品種の異なる集積回路単体の試験をする場合
において、 前記集積回路の品種を選別するためのテストパ
ターン発生部と、 前記テストパターン信号による予備試験測定部
と、 前記予備試験測定部による前記集積回路の品種
との関係を表示する品種選別対応表と、 前記品種選別対応表から測定プログラム・テス
トパターン名を選出する編集表と、 前記編集表で選出したプログラムを格納する高
速処理格納部と、 前記高速処理格納部に前記プログラムがないと
きは前記高速処理格納部に前記プログラムを転送
する大容量格納部とを備え、 前記集積回路の品種を選別し、前記集積回路の
品種に対応して前記編集表から測定プログラム・
テストパターン名を選び出して編集し、前記編集
で選び出したプログラムを高速処理格納部から取
り出して前記集積回路を試験することを特徴とす
る集積回路測定装置。
[Scope of Claims] 1. In the case of testing individual integrated circuits of different types, a test pattern generation unit for selecting the type of integrated circuit, a preliminary test measurement unit using the test pattern signal, and the preliminary test. A product selection correspondence table that displays the relationship between the types of integrated circuits by the measurement unit; an editing table that selects measurement program/test pattern names from the product selection correspondence table; and a high-speed memory that stores the programs selected in the editing table. a processing storage section; and a large-capacity storage section that transfers the program to the high-speed processing storage section when the program is not present in the high-speed processing storage section; Corresponding to the measurement program and
An integrated circuit measuring device characterized in that the test pattern name is selected and edited, and the program selected in the editing is retrieved from a high-speed processing storage unit to test the integrated circuit.
JP58014326A 1983-01-31 1983-01-31 Integrated circuit measuring apparatus Granted JPS59141077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58014326A JPS59141077A (en) 1983-01-31 1983-01-31 Integrated circuit measuring apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58014326A JPS59141077A (en) 1983-01-31 1983-01-31 Integrated circuit measuring apparatus

Publications (2)

Publication Number Publication Date
JPS59141077A JPS59141077A (en) 1984-08-13
JPH0450536B2 true JPH0450536B2 (en) 1992-08-14

Family

ID=11857944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58014326A Granted JPS59141077A (en) 1983-01-31 1983-01-31 Integrated circuit measuring apparatus

Country Status (1)

Country Link
JP (1) JPS59141077A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011125530A1 (en) * 2010-03-31 2011-10-13 ユニ・チャーム株式会社 Absorbent article

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06105281B2 (en) * 1985-12-20 1994-12-21 日本電気株式会社 Dynamic aging equipment
JPS62247275A (en) * 1986-03-31 1987-10-28 Ando Electric Co Ltd Cpu identification circuit for in-circuit emulator
JPS6326580A (en) * 1986-07-18 1988-02-04 Nec Ic Microcomput Syst Ltd Lsi testing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011125530A1 (en) * 2010-03-31 2011-10-13 ユニ・チャーム株式会社 Absorbent article

Also Published As

Publication number Publication date
JPS59141077A (en) 1984-08-13

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