JPH0449868A - Pwm inverter device - Google Patents

Abstract

PURPOSE:To prevent the disturbance of inverter output voltage resulting from the upper and lower arms short circuit prevention time by providing output voltage detectors between the output of a potential divider and each phase of the center tap output of each arm pair of an inverter, respectively, and outputting a control command to a controller when the output of the inverter becomes larger than the output of the potential divider. CONSTITUTION:A potential divider 2 is composed of resistances 21 and 22, and a three-phase inverter is composed of the arm pairs 10, 20 and 30 at the inverter part consisting of a gate turn-off thyristor (GTO). Voltage detectors 40-60 are connected respectively between the inverter output lines 101-103 and the output 100 of the potential divider 2. Hereby, when the output voltage of the inverter part becomes larger than the output voltage of the potential divider, a control command is output to a controller to control upper and lower arms short circuit time, thus the GTO arm short circuit prevention time can always stably be secured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a power semiconductor element of an inverse conversion section of an inverter device using a GTO (Gate Turn-Qff Thy).
P W M (Pulse W
idth Modulation) This relates to an inverter device.

[Conventional technology]

FIG. 5 is a block diagram showing the configuration of an inverse conversion section of a conventional PWM inverter device disclosed in, for example, Japanese Patent Application Laid-open No. 60-207494, in which 1 is a DC power supply, 21
0 to 215 are transistors, 216 to 221 are freewheeling diodes, 140.150.160 are conventional inverter output voltage detectors, 204 is a positive bus of the DC power supply 1, 205 is a negative bus, and 201
-203 are inverter output lines. The inverter output line 201 corresponds to the U phase, 202 corresponds to the V phase, and 203 corresponds to the W phase.

In addition, FIG. 6 shows output voltage detectors 140, 150°160
141 is a resistor, and 142 is a photocoupler. The resistors 141 are connected to the inverter output lines 201 to 203, respectively, and the photocoupler 1
42 is connected to the minus side bus bar 205.

Next, the operation will be explained using the U phase as an example. First, the voltage of the inverter output line 201 is controlled by alternately turning on and off the transistors 210 and 211 and changing their deity. At this time, in order to prevent DC short circuit, transistors 2 on the positive side and negative side of DC power supply 1 are
'Provide a short-circuit prevention time (Td) correlated to IO, 2110 firing.

That is, although the positive side transistor 210 and the negative side transistor 211 of the DC power supply 1 are alternately KOHed, a period is provided during which both are turned off during switching to prevent DC short circuits caused by the storage time of the transistors.

However, in the case of PWM modulation, the short circuit prevention time (Td
), the voltage output pulse width of the inverter output line 201 changes depending on the magnitude and direction of the output current. When both the positive side transistor 210 and the negative side transistor 211 are OFF, that is, when the AC output current has a certain value and the output current is in the forward direction (flows from the inverter to the load), the output voltage becomes negative, and when the output current is in the opposite direction (flowing from the load to the inverter), the output voltage becomes positive. Naturally, the storage time of the transistor changes depending on the magnitude of the output current.

As a way to correct this, the inverter output line 201
A voltage detector 140 is provided between the DC power source 1 and the negative bus 205 of the DC power supply 1, and this voltage detector 140 detects the actual output pulse width to
The control unit 8 adjusts the 8 hours to obtain the output as instructed.
Controlled by 0.

As shown in FIG. 7, the output voltage waveform of the inverter output line 201 takes two values: O (Lo) and Ed (Hi). In the case of a transistor, the rise time of the output voltage Ed (
tri) and fall time (tfl) are approximately 0.5 to 2
It is short as tt se c. Inverter output line 201
When the voltage of 7 rises, the resistor 141
A current limited by the current flows. When this current value exceeds the operating threshold of the photocoupler 142, the output of the photocoupler 142 becomes active, detecting that the inverter output line 201 has become HI, and transmitting it to the control unit 80. Control unit 80
Now we control the pace drive pulse of the transistor.

[Problem to be solved by the invention]

Conventional PWM inverter devices are configured as described above, so even if a circuit that operates without problems when a transistor is used to drive the inverter, when a GTO is used, the rise time of the output voltage may vary depending on the configuration of the snubber circuit. Alternatively, the fall time may become longer, or the fall time may vary significantly depending on the load. In the conventional voltage detection circuit, the detection level fluctuates greatly due to a change in the threshold current of the photocoupler, which causes a problem in that the detection of the output voltage is disturbed and the short-circuit pause time (Td) of the correlation fluctuates.

This invention was made in order to solve the above-mentioned problems.GTO is used as the power semiconductor of the inverse conversion section, and the output voltages Hl and LO are detected with relative fluctuations around the intermediate level (Ed/2). An object of the present invention is to obtain a PWM inverter device equipped with an output voltage detector that operates in a region with a small amount of voltage.

[Means to solve the problem]

The PWM inverter device according to the present invention has a positive side GT.
A first snubber capacitor is connected to the anode side of O, and a circuit in which a first snubber diode is connected in series with the same polarity to the cathode side is connected in parallel, and
A second electrode is installed on the anode side of the negative GTO that is paired with the TO.
snubber diodes are connected to have the same polarity, and a circuit in which a second snubber capacitor is connected in series to the cathode side is connected in parallel, and the first snubber capacitor and the first snubber capacitor connected in series are connected in parallel.
A current limiting circuit that connects the intersection of the snubber diodes and the intersection of the second snubber diode and the second snubber capacitor via a snubber resistor, and has a center tap between the cathode of the positive GTO and the anode of the negative GTO. It consists of a DC power supply connected in the forward direction to the GTO, with a pair of arms of the inverse conversion section equipped with a reactor, and a plurality of pairs of arms of the inverse conversion section connected in parallel, and a plurality of resistors connected between the terminals of the DC power supply. an output voltage detector that outputs a control command when the output of the inverse converter becomes larger than the output of the voltage divider between each phase of the output of the voltage divider and the center tap output of the inverse converter; The control unit is configured to include a control unit that inputs a control command for the output voltage detector as a control signal for the upper and lower arm short-circuit prevention time.

[For production]

The output voltage detector in this invention is provided between the output of the voltage divider and each phase of the center tap output of each arm pair of the inverse converter, and the output of the inverse converter is higher than the output of the voltage divider. Since the control command is output to the control section when the control is turned on, the prevention of disturbances in the inverter output voltage caused by the upper and lower arm short-circuit prevention time is improved. Furthermore, since a portion of the snubber energy is recycled to the load, snubber loss is reduced.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as those in FIG. 5 are designated by the same reference numerals. In FIG. 10, 20, and 30 are a pair of arms of an inverse conversion unit made up of GTO, and five pairs of three arms constitute a three-phase inverter. 40, 50, and 60 are the output voltage detectors according to the present invention, and 100 is the voltage output of the voltage divider 2.

FIG. 2 is a circuit diagram showing an embodiment of the output voltage detectors 40, 50, 60, resistors 41, 42 . Zener diode 43. It is composed of a photocoupler 44.

Further, FIG. 3 is a circuit diagram showing an embodiment of the arm pair 10, 20.degree. 30 of the inverse conversion section. 11.12 is GTO11
3 and 14 are freewheeling diodes, 15.16
are (first and second) snubber capacitors, 17.18 are (
1st. 2nd) snubber diode, 19 is a snubber resistor,
20 is a current limiting reactor equipped with a center tube.

Here, GTOll, 7 Lee wheeling diode 1
3. The first snubber capacitor 15 and the first snubber diode 17 are connected to the upper arm UA, GT012, and the freewheeling diode 14. The second snubber capacitor 16 and the second snubber diode 18 are referred to as a lower arm SM.

Next, the operation will be explained. For example, in the circuit shown in Fig. 3, when current is flowing to the load through GTOl 1 and GTOl 1 is turned off, the load current ILL,
IL2 is snubber capacitor 15 → snubber diode 1
The current flows through the following paths: 7→center tap of current limiting reactor 20→load, and snubber capacitor 16→snubber resistor 19→snubber diode 17→current limiting reactor 20→load. The snubber capacitor 15 is charged and the snubber capacitor 16 is discharged by the load currents Ll and IL2. Determine the load current and the capacity and amount of the snubber capacitor 15.16.
Then, the rate of change of the output voltage ■ becomes dV/dt=It,/(2XC), which changes depending on the load current rL. For example, when the voltage waveform of an inverter output line (for example, 101) is shown in FIG. 4, the rise time tr2 and fall time tf2 of the voltage waveform vary from several μSaC to several tens of μSaC depending on the load current.
It changes greatly with sec.

Therefore, the output voltage detector 400 threshold value v1 is the output voltage Ed
It must be set to an intermediate potential (Ed/2). At this time, most of the energy in the snubber capacitor 16 circulates to the load, reducing snubber loss.

Next, detection of the output voltage Ed will be explained. First, the values of the resistors 21 and 22 constituting the voltage divider 2 are set as follows. The resistance values of the resistors 21 and 22 are assumed to be R21 and R22.

■ R21+R22; Ed/(R21+R22)>Ix
However, x is the current flowing through the voltage detectors 40 to 60 when the inverter output is Hi()i:d) or Lo(0).

The voltage of the output 100 of the voltage divider 2 becomes approximately a constant voltage source when viewed from the voltage detectors 40 to 60.

(2) R21/R22''=-1 Set the output 100 of the voltage divider 2 near the intermediate potential (Ed/2).

Next, the operation of the voltage detectors 40 to 60 will be explained with reference to FIG. Inverter output line (e.g. 101)
When the voltage is less than the output 100 of the divided voltage ls2, the current IB
flows through the path of Zener diode 43 → resistor 41, and 7
The output of Otocap 744 becomes Lo. Further, when the voltage of the inverter output line (for example, 101) is higher than the output of the voltage divider 2, the following operation is performed. The Zener voltage of the Zener diode 43 is VZ, the voltage applied to the voltage detectors 40 to 60 (for example, the relationship between the inverter output line 101 and the voltage divider output 100) is VD, and the threshold current of the photodiode of the photocoupler 44 is TH+. Resistance 41, 42
Let the resistance values of R41 and R42 be respectively. However, the voltage drop of the photocoupler 44 is ignored and R41>R42.

■ VD/R41<ITH Since the current IP is less than the threshold current ITFI flowing in the path of resistor 41 → resistor 42 → photocoupler 44, photocoupler 4
2 output beam. It remains as it is.

■ I 7B < VD/ R41 < VZ/ R42 The current flows through the path of resistor 41 → resistor 42 → 7t tokabura 44. Since the threshold current ITH is higher than the threshold current ITH, the output of the photocoupler 44 becomes I(i).

■ VZ/R42<VD/R41 The current flows through the path of resistor 41 → resistor 42 → photocoupler 44 and the path of resistor 41 → Zener diode 43,
The current of the photocoupler 44 is limited to a rated value or less. The output of the photocoupler 44 becomes Hi.

From the above explanation, the output voltage detectors 40 to 60 have a threshold value when the output voltage is Ed/2+IT, XR41, and the output of the photocoupler changes. If the resistor R41 is set to a low value, the threshold value will be close to the median value (Ed/2).

In the above embodiment, a three-phase inverter with a fixed DC power supply was used as an example, but the DC power supply may be variable.
Further, the number of inverter phases may be single phase or other, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, an output voltage detector is connected between the output of the voltage divider connected between the terminals of the DC power supply and the center tap output of the arm pair of each inverter, and the When the output voltage of the inverse converter becomes higher than the output voltage of the voltage regulator, a control command is output to the control unit to control the short-circuit time of the upper and lower arms, so the short-circuit prevention time of the GTO arm is always stable. This has the effect of providing a PWM inverter device with high reliability and low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PWM inverter device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a circuit of a voltage detector, and FIG. 3 is a circuit diagram showing an example of an arm pair of an inverse conversion section. Fourth
The figure is an output voltage waveform diagram of the inverse conversion section, Figure 5 is a configuration diagram of a conventional transistor PWM inverter device, Figure 6 is a voltage detection circuit diagram as an example of Figure 5, and Figure 7 is an example. FIG. 3 is an output voltage waveform diagram of FIG. In the figure, 1 is a DC power supply, 2 is a voltage divider, 21° and 22 are resistors, 10 to 30 are arm pairs of the inverse converter, 40 to 60 are output voltage detectors, 11.12 is a GTO 115, and 16 are (
1st. (second) snubber capacitor, 17.18 is (first
．． 2nd) snubber diode, 19 is a snubber resistor, 20
is the current limiting reactor, 80 is the control unit, UA is the upper arm, S
A is the lower arm. In addition, the same symbols in the figures indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation (2 others) 1 DC power supply 2> Voltage divider 1 ON30: Reverse *J4fISq I-IJ=p Fig. 1112: GTO +5.16' (Off 10) Snubber 17
．． 18: (Fang 1 year old 2) snubber tie auto) 9° snubber turtle resistance 20 eye two running acudle UA upper arm Sa lower arm

Claims (1)

[Claims] A circuit in which the upper arm and the lower arm are connected by a center-tapped current limiting reactor, and a first snubber circuit for the upper arm.
The intersection of the snubber capacitor and the first snubber diode,
and a circuit in which an electric valve and a series resistor are connected between the intersection point of the second snubber diode and the second snubber capacitor of the snubber circuit of the lower arm for controlling when recovering the snubber energy to an auxiliary power source, which will be described later. an inverter arm pair consisting of; a DC power supply having a plurality of inverter arm pairs arranged in parallel and connected in the forward direction to the GTO of the upper and lower arms;
A voltage divider connected between the terminals of the DC power supply and constituted by a plurality of resistors is provided for each phase between the output of the voltage divider and the center tap output of the inverse conversion section, and the output of the voltage divider is PWM comprising: an output voltage detector that outputs a control command when the output voltage of the inverse converter becomes larger; and a control unit that inputs the control command of the output voltage detector as a control signal for the upper and lower arm short circuit prevention time. Inverter device.