JPH0449504A - Peak detecting circuit for magnetic storage device - Google Patents

Abstract

PURPOSE:To prevent the reduction of the operation margin of a data reproducing circuit by changing the delay time of an output signal in accordance with the time difference between positive-polarity and negative-polarity output signals of a comparator. CONSTITUTION:The signal reproduced by a magnetic head 1 is obtained as an amplified signal 21 by an amplifier/filter 2. This signal 21 passes a differentiating device 3 and is converted to positive-polarity and negative-polarity signals 23a and 23b of a pulse signal by a comparator 4, and they are converted to pulse signals having prescribed width by pulsers 5 and 6 and are inputted to delay circuits 7 and 8. These circuits 7 and 8 delay pulser output signals 24 and 25 by prescribed times and output the results. An error detector prescribed times and output the results. An error detector 10 controls the circuit 8 through the circuit 8 in accordance with the time difference between signals 23a and 23b by an error signal 28. Thus, the reduction of the operation margin due to distortion of the waveform of the reproduced signal is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak detection circuit used in a data reproducing circuit of a magnetic storage device.

[Conventional technology]

The peak detection circuit used in the data reproduction circuit of a conventional magnetic storage device includes a differentiator that differentiates the reproduction signal from the magnetic head, a comparator that detects the zero crossing point of the output signal from this differentiator, and an output pulse of the comparator. The pulser generates a pulse signal having a predetermined time width at both the rising and falling points of the pulse signal.

[Problems to be Solved by the Invention] The peak detection circuit of the conventional magnetic storage device as described above has a problem in that the reproduced signal from the magnetic head has a waveform due to some reason (for example, a shift in the recording timing of the write current or the influence of an external magnetic field). When waveform distortion occurs due to distortion, etc., the peak of the waveform of the reproduced signal shifts, and the output pulse of the peak detection circuit also shifts accordingly, resulting in a disadvantage that the operating margin of the data reproduction circuit is significantly reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable peak detection circuit that prevents a decrease in the operating margin of a data reproducing circuit caused by a timing shift of an output pulse due to waveform distortion of a reproduced signal as described above. be.

[Means to solve the problem]

A peak detection circuit for a magnetic storage device according to the present invention includes a differentiator that differentiates a reproduced signal from a magnetic head, and a comparator that detects a zero crossing point of an output signal from the differentiator. , a first pulser that generates a pulse signal of a predetermined time width at the rising or falling point of the positive output pulse of the comparator; and a first pulser that generates a pulse signal of a predetermined time width at the rising or falling point of the negative output pulse of the comparator. a second pulser that generates a pulse signal with a predetermined time width; a first delay circuit that delays the output pulse of the first pulser by a predetermined time; and a control signal that outputs the output pulse of the second pulser. a second delay circuit that delays the output signals of the first and second delay circuits, and an OR circuit that takes the logical sum of the output signals of the first and second delay circuits, The time difference with the output signal is monitored and the delay time of the output signal of one polarity of the comparator is changed in accordance with the time difference. In particular, the delay time of the output signal of one polarity of the comparator is an error detector that compares the timing of output pulses and generates a pulse signal corresponding to the difference; and a filter that smooths the output signal of the error detector and converts it into a signal at approximately a DC level; The output signal is inputted to the second delay circuit as the control signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram showing the waveforms of each signal in the embodiment of FIG.

In the embodiment shown in FIG. 1, a magnetic head 1, an amplifier/filter 2, a differentiator 3, and a comparator 4 are connected in series, and the positive output signal of the comparator 4 is sent to a pulser 5. The output signal of the negative polarity of the comparator 4 is inputted to the delay circuit 8 via the pulser 6.

Further, both the positive output signal and the negative output signal of the comparator 4 are input to the error detector 10. The output signal of the error detector 10 is input to the control terminal of the delay circuit 8 via the filter 11 7, and the output signals of the delay circuits 7 and 8 are input to the OR circuit 9, from which it is output as a peak pulse 30. Ru.

In the peak detection circuit configured as described above, the signal reproduced by the magnetic head 1 is amplified to a predetermined level and noise is removed by the amplifier/filter 2, as shown in FIG. Amplified signal 2 with a waveform as shown
It becomes 1. In FIG. 2, a waveform 21a shown by a solid line is a normal case, and a waveform 21b shown by a broken line is an abnormal case. Differential signal 2 obtained by differentiating the amplified signal 21 with the differentiator 3
2 is converted by the comparator 4 into a positive polarity comparator output signal 23a and a negative polarity comparator output signal 23b of the pulse signal. Comparator output signal 2
3a and 23b are converted into pulse No. 13 of a predetermined width by pulsers 5 and 6, respectively, and input to delay circuits 7 and 8 as pulser output signals 24 and 25. Delay circuits 7 and 8 delay input pulser output signals 24 and 25 by a predetermined time and output them as delayed signals 26 and 27, respectively.

The time difference (TI-T2) and ('r3T4) between the high level and low level of the comparator output signal 23a indicate normal and abnormal times, respectively.
2 are equal (ITI T21=O), and in an abnormal case, T3 and T4 are not equal (l T3-"r
'41 > 0). The error detector 10 detects this l T
A pulse signal corresponding to '1-T2 and 1T3T41 is output as an error signal 28. The error signal 28 is smoothed by the filter 1 and converted into a signal of approximately DC level, which is input to the delay circuit 8 as a control signal 29.

The control signal 29 becomes positive when the comparator output signal 23a is longer than the comparator output signal 23b, becomes negative when it is shorter, and becomes 0 when they are equal.

The delay circuit 8 changes the delay time according to the control signal 29 from the filter 11. When the control signal 29 is 0, the time is the same as the delay time of the delay circuit 7, when it is positive, the time is longer than the delay time of the delay circuit 7, and when it is negative, the time is shorter.

By changing the delay time of the delay circuit 8, T and T4
In the example shown in Fig. 2, the delay time becomes longer and ``3 changes in the direction of increasing and T4 decreases'', and finally reaches (Tq T2O).As a result, the OR circuit The output 30 of 9 becomes a pulse signal at equal intervals shown by a solid line.If the delay time is not controlled, a pulse signal at unequal intervals shown by a broken line becomes a pulse signal.

〔Effect of the invention〕

As explained above, the peak detection circuit of the magnetic storage device of the present invention monitors the time difference between the output signal of the positive polarity and the output signal of the negative polarity of the comparator, and outputs the output signal of one polarity in response to the time difference. By changing the delay time of , it is possible to obtain a highly reliable peak detection circuit that prevents a reduction in the operating margin of the data reproducing circuit caused by a shift in timing of jumps due to distortion of the reproduced waveform.

FIG. 2 is a waveform diagram showing the waveform of each signal in the embodiment of FIG. 1.

■...Magnetic head, 2...Amplifier, /
Filter, 3...Differentiator, 4...Comparator, 5/6...Pulser, 78...
・・Delay circuit, 9・・・・−OR circuit, 10・・・・
...Error detector, 11...Filter.

Claims (1)

[Scope of Claims] 1. A peak detection circuit for a magnetic storage device comprising a differentiator that differentiates a reproduced signal from a magnetic head, and a comparator that detects a zero crossing point of an output signal from the differentiator. a first pulser that generates a pulse signal of a predetermined time width at the time of rising or falling of the output pulse of positive polarity; a second pulser that generates a pulse signal; a first delay circuit that delays the output pulse of the first pulser by a predetermined time; and a first delay circuit that delays the output pulse of the second pulser by a time specified by a control signal. A second delay circuit for delaying, and an OR circuit for ORing the output signals of the first and second delay circuits, and the time difference between the positive output signal and the negative output signal of the comparator is calculated. A peak detection circuit for a magnetic storage device, characterized in that the delay time of the output signal of one polarity of the comparator is changed in accordance with the time difference monitored. 2. In a peak detection circuit of a magnetic storage device that includes a differentiator that differentiates a reproduction signal from a magnetic head and a comparator that detects a zero crossing point of an output signal from the differentiator, the output pulse of the positive polarity of the comparator is a first pulser that generates a pulse signal of a predetermined time width at a rising or falling point; and a first pulser that generates a pulse signal of a predetermined time width at a rising or falling point of the negative output pulse of the comparator. a second pulser; a first delay circuit that delays the output pulse of the first pulser by a predetermined time; and a second delay circuit that delays the output pulse of the second pulser by a time specified by a control signal. a circuit, an OR circuit that logically sums the output signals of the first and second delay circuits, and a pulse that compares the timings of a positive output pulse and a negative output pulse of the comparator and corresponds to the difference. an error detector that generates a signal; and a filter that smoothes the output signal of the error detector and converts it into a signal at approximately a DC level; and the output signal of the filter is sent to the second delay circuit as the control signal. A peak detection circuit for a magnetic storage device, characterized in that the peak detection circuit receives an input signal.