JPH0449459A - Dma transfer method - Google Patents

Abstract

PURPOSE:To rapidly execute data writing in a RAM by a direct memory access (DMA) controller by providing the DMA controller with a register capable of storing data. CONSTITUTION:The DMA controller 4 is provided with the register 4b for storing data and the data are stored in the register 4b under the control of a CPU 1. A write instruction for writing the data stored in the register 4b in a memory continuously writes and stores the data read out from the register 4b in the memory 3 under the control of the DMA controller 4 access by the CPU 1. Consequently, data writing in the RAM by the DMA controller 4 can rapidly be executed.

Description

[Detailed Description of the Invention] Overview DMA (Direct Memory Access
ss) :] RAM (Rand
The purpose of this paper is to provide a DMA transfer method that allows a DMA controller to write data to RAM at high speed. In a DMA transfer method for transferring data to a memory by a controller, the DMA controller includes:
A register that stores and holds data is provided, the data is stored in the register under the control of the CPU, and an instruction to write the data stored in the register to the memory is sent to the CPU.
The data stored in the register is continuously written and stored in the memory under the control of the DMA controller accessed by the write command.

Industrial Field of Application The present invention is directed to DMA (Direct Memory).
Access) ml 7 troller by RA
The present invention relates to a DMA transfer method that accesses data in M (Random Access Memory) and initializes RAM.

In recent years, with the remarkable development of computer systems, the number of terminals that handle huge amounts of data has increased. In terminals that handle huge amounts of data,
Since the memory area such as RAM of the terminal is large, DM
Even if data is transferred to memory using A transfer,
The transfer takes a considerable amount of time. For example, it takes a considerable amount of time to initialize the RAM by transferring data to the memory. Therefore, it is desired to shorten the transfer time.

BACKGROUND ART FIG. 3 is a diagram for explaining a conventional DMA transfer method.
The initialization method of M will be explained.

In this figure, 1 is CPU (Central Pr
ocessrB [Jnit), 2 is ROM (Re
3 is a RAM, 4 is a DMA controller having a buffer register 4a, 5 is a pass line through which data is transmitted, and the CPU SROM 2, RAM 3, and DMA controller 4 are connected to each other by this pass line 5. .

In such a configuration, the case where the RAM is initialized will be explained step by step.

(2) The CPU accesses the ROM2 and reads the initialization execution instruction code stored in the ROM2.

(2) Having read the instruction code, the CPU 1 accesses the RAM 3 and writes and stores the initial data in the memory area of the nth address n of the RAM 3.

(2) The CPU 1 accesses the DMA controller 4 with a read/write command.

This read/write command is issued by the DMA controller 4.
The initial data stored in the memory area of the address of RAM 3 is read and temporarily stored in the buffer register 4a,
Furthermore, it is used to execute control for writing and storing the initial data stored in the buffer register 4a in a memory area at another address in the RAM 3.

■The DMA controller 4 accessed by the read/write command reads the initial data stored in the memory area of the n-th address of the RAM 3, and reads the initial data from the buffer register 4.
The initial data stored in the buffer register 4a is written and stored in the memory area of the (n+1)th address of the RAM 3.

After that, the operations of ■ and ■ are repeated, and as a result, RA
When the initial data is stored in the memory areas of all addresses of M3, the initialization of RAM3 is completed.

Problem to be Solved by the Invention By the way, as mentioned above, when the RAM is initialized by the DMA controller, the buffer register 4a provided in the DMA controller 4 can only temporarily store data. , the DMA controller 4 transfers the initial data from the buffer register 4a to the RAM 3.
After the initial data is transferred to the RAM 3, it is necessary to read the initial data from the RAM 3 and store it in the buffer register 4a again using a read/write command from the CPUI. For this reason, R
Each time initial data is written to AM3, a command from the CPU 1 is required, and the initial data must be read from RAM 3 into buffer register 4a and stored, so initialization of RAM 3 is delayed accordingly. In other words, R.A.
There was a problem that the speed of writing initial data to M3 was slow.

The present invention has been made in view of these points,
It is an object of the present invention to provide a DMA transfer method that allows a DMA controller to write data to a RAM at high speed.

According to the present invention, first, the DMA controller 4 is provided with a register 4b for storing and holding data, and the register 4b is
b stores data under the control of the CPU 1.

Then, the data stored in the register 4b is transferred to the memory 3.
The DMA controller 4 is accessed from the CPU 1, and the data stored in the register 4b is continuously written to the memory 3 under the control of the DMA controller 4 to which the write instruction is accessed. Let me remember it.

Function As described above, the data stored in the register 4b is continuously written and stored in the memory 3 under the control of the DMA controller 4, so data can be transferred from the register 4b of the DMA controller 4 to the memory 3 at high speed. can do.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is an indispensable diagram for explaining a DMA transfer method according to an embodiment of the present invention. In this diagram, parts corresponding to those of the conventional example shown in FIG. The explanation will be omitted.

The configuration of the embodiment of the present invention differs from the configuration of the conventional example shown in FIG. 3 in that the DMA controller 4 is provided with a register 4b that can store and hold data.

In such a configuration, the case where the RAM is initialized will be explained step by step.

(2) The CPU 1 accesses the ROM 2 and reads the initialization execution instruction code stored in the ROM 2.

■The CPU 1 that read the instruction code sets the initial data “0” or “1” to the register 4b of the DMA controller 4.
At the same time, perform a write command.

This write command causes the DMA controller 4 to write and store the initial data stored in the register 4b in the memory area of the RAM 3.

■The DMA controller 4 where the write command was executed is the RA
Initial data is sequentially and continuously written and stored starting from the memory area of the n-th address of M3. here,
When the initial data is stored in the memory areas of all addresses of the RAM 3, the initialization of the RAM 3 is completed.

■When the initialization of RΔM3 is completed, RAM3 is D),
4 Sends data informing the completion to the A controller 4, and upon receiving this data, the DMA controller 4
Informs PU 1 that initialization is complete, and thereby
3 initialization is completed.

As explained above, according to the embodiment of the present invention, the CPU
By simply issuing a write command from 1 to the DMA controller 4, the initial data of the register 4b can be unilaterally written to the RAM 3 for initialization.

This is because the conventional DMA transfer method requires a command from the CPU 1 every time initial data is written to the RAM 3, and also requires reading and storing the initial data from the RAM 3 into the buffer register 4a.
This eliminates the CPUI command operation that is performed each time initial data is written, and the operation that reads initial data into the buffer register 4a. Therefore, since these operations are eliminated, the speed at which initial data is written to the RAM 3 becomes faster, and the RAM 3 can be initialized more quickly.

Further, after a write command is issued from the CPUI to the DMA controller 4, the DMA controller 4 performs initialization, so the CPU i can be used for other purposes during that time.

In addition to initialization, this data transfer by the DMA controller 4 can be applied to writing the same data "0"..."O" or "1"..."1".

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, writing of data to RAM (transfer of data) by a DMA controller
This has the effect of allowing the process to be carried out at high speed.

Furthermore, while data is being written to the RAM by the DMA controller, the CPU can be used for other purposes.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram for explaining a DMA transfer method according to an embodiment of the present invention, and FIG. 3 is a diagram for explaining a conventional DMA transfer method. 1...CPU. 3...Memory, 4...DMA controller, 4b...Register. 4 sects

Claims (1)

[Claims] In a DMA transfer method in which a DMA controller (4) transfers data to a memory (3), the DMA controller (4) includes a register (4) for storing and holding data.
b) to store data in the register (4b) under the control of the CPU (1), and to write the data stored in the register (4b) to the memory (3).
The DMA controller (4) is accessed from the PU (1), and the data stored in the register (4b) is continuously stored in the memory (1) under the control of the DMA controller (4) accessed by the write command. A DMA transfer method characterized by writing and storing data.