JPH0449152B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an optical reading device that optically reads information at high speed and with high accuracy by making full use of IC circuit technology.

Conventional configurations and their problems With the advancement of information processing equipment such as computers, the importance of sensors as input devices is increasing.

Conventional optical reading devices include silicon vidicon, MOS target vidicon, etc., and since the access function for sequential reading is performed by deflecting an electron beam, these devices are easy to use and have high resolution. However, since it is not completely solid-state, there are drawbacks to miniaturization, low power consumption, etc.

On the other hand, all-solid-state optical readers include photodiode arrays or matrices, phototransistor arrays or matrices, photoconductor arrays or matrices, CCD arrays or matrices, and the like. Sequentially reading the information requires the ability to access the sensors in each array or matrix. If the sensor group and scanning function section are implemented as separate parts,
In high-resolution devices, interconnection becomes especially complicated. Therefore, optical readers that integrate a sensor group and a scanning section and are formed on a silicon chip include MOS solid-state optical readers, CCID (Charge Couple Image Device), and BBID (Bucket Brigade).・Image device) etc. These devices consist of an optical sensor section and a scanning section based on MOS integrated circuit technology, and although they have high resolution, they have the disadvantage of slow reading speeds and the inability to obtain large contrast.

OBJECT OF THE INVENTION The present invention enables a sensor section and a scanning section to be formed on the same chip, and the above-mentioned MOS
The objective is to provide an optical reading device with high speed, high resolution, and good linearity, which eliminates the drawbacks of optical elements, CCID, BBID, etc., and is mainly based on bipolar integrated circuit technology. When a large number of photodiodes or phototransistors are arranged in an array, such as in an image sensor, and the readout time of a particular element is sufficiently small compared to the total scan time, sensitivity can be significantly increased by operating in charge accumulation mode. It is well known that it is possible to improve In charge storage mode, charge is stored in the reverse junction capacitance in the case of a photodiode and in the base-collector reverse junction capacitance in the case of a phototransistor. The timing of the operation is divided into a period during which the photocurrent is integrated over time (during non-access) and a read time (during access). The junction capacitance is charged during access, and the charged charge is discharged by photocurrent during non-access.At the next access, a light proportional signal is obtained by detecting the amount of charge, and the integral A photoelectric conversion signal proportional to time is obtained. The reading speed is determined by the maximum possible frequency of the access clock pulses. The present invention relates to an optical reading device that enables high-speed reading by accessing a photodiode or phototransistor operating in charge storage mode at high speed.
To increase speed, a circuit that generates complementary logic signals with different DC levels and a current switching circuit are used. Since all the transistors constituting the access current switching circuit and logic signal generation circuit operate in a non-saturated state, there is almost no delay due to carrier accumulation, and high-speed operation is possible.

Structure of the Invention In order to achieve the above object, an optical reading device of the present invention includes a circuit that receives an input selection signal from the outside and generates complementary logic signals having different DC levels, a constant current source, and a cascade connection. and a current switching circuit that receives the complementary logic signal and accesses a predetermined one of the plurality of photodetecting elements, and the logic signal generation circuit generates a selection signal for operating the current switching circuit. The current switching circuit is configured to extend a photoelectric current only to a branch path selected according to a selection signal, and read the optical signal of the photoelectric conversion element.

DESCRIPTION OF EMBODIMENTS Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows a circuit that receives an input selection signal from the outside at a selection signal input terminal 1 and converts it into complementary signals having different DC levels. The current from the constant current circuit 3 is connected to the logic reference voltage terminal V th by transistor pairs 4, 5, and 6 constituting the current switching circuit _.
According to the result of comparison with input selection signal 1, transistor 4a or 4b side, 5a or 5b side,
6a or 6b, and the respective currents cause complementary three-bit voltages to be generated by the resistor pairs 7, 8, 9. V _th is, for example, in the case of transistor-transistor logic (TTL),
Set to 1.4V. The diode string 10 is for obtaining an appropriate voltage level shift from the side power supply 11, thereby determining the DC level of the logic signal for driving the cascade type current circuit connected to the complementary output. . Note that the element for obtaining this voltage level shift is not limited to a diode, but may be a diffused resistor. For example, when an "H" level signal is input to the input terminal 1a of the selection signal input terminal 1, the complementary output 2 A is "H",
A becomes "L". This logic amplitude is determined by the value of the resistor 7 and the current value of the constant current circuit 3. Set the logic amplitude to 0.6V or less. If V _cc is 10V,
The “H” level is 8.6V and the “L” level is 8.0V. Since each transistor making up the transistor pair always operates in a non-saturated state, there is no delay due to carrier saturation, resulting in extremely high speed. Although FIG. 1 shows the case of 3 bits, this can be expanded to a case with a larger number of bits by repeating the same procedure.

FIG. 2 shows that the input terminal 12 receives the complementary logic signal generated from the output terminal 2 of FIG. This circuit is for accessing 23a to 23h, and consists of current switching circuits connected in cascade in a tree shape. Transistor pairs 14, 15, 16,...
..., 20 constitute a current switching circuit for switching the current flowing through the emitter pair of each transistor pair according to a logic signal.Resistors 22a to 22h detect which transistor is in a normal state among transistor pairs 17 to 20. It is load resistance. Transistor pair 17, PNP transistors 21a, 21
To explain the case of the load resistors 22a, 22b and phototransistors 23a, 23b as an example, if the transistor on the PNP transistor 21a side of the transistor pair 17 is in a conductive state, the collector voltage of that transistor is In the future, the PNP transistor 21a
The ON state is entered, and a charging current proportional to the intensity of the irradiated light flows through the phototransistor 23a, resulting in a reading period (access period). This provides an output at V _put that is proportional to the charging current. Among the transistor pair 17, the collector potential of the NPN transistor that is not in the energized state becomes a voltage near _Vcc (side power supply voltage), the PNP transistor 21b connected thereto becomes the OFF state, and the phototransistor 23b becomes the floating state, and the integration period (non-access period). transistor pair 18
The same applies to the case of ~20. In this current switching circuit, since the input signal input to the input terminal 12 is a complementary signal, the logic amplitude is
If it is 0.6V, the current switching circuit can be reliably driven. Because of this small logic amplitude and because the two pulse waveforms forming the complementary logic signal change in opposite directions at each change timing, noise caused by the induction of these digital signals into the image signal output line is reduced. Ru.

In Figure 2, the number of connected stages of transistor pairs is 3 and 8.
Although the case where one photodiode or phototransistor is driven is shown, if the number of connected stages of transistor pairs is increased, even more photodiodes or phototransistors can be driven with one constant current power supply. Even in that case, power consumption does not increase.

Further, according to the present circuit, high-speed reading is possible because delays in access time due to ready-made capacitors can be minimized and the transistors operate in a non-saturated state.

FIG. 3 shows another embodiment of the cascade type current switching circuit, in which the current switching circuit is
It consists of a pair of PNP transistors, whose collector current directly drives the photodiode. Transistor pairs 28, 29, 30, 31, 32, 33, which operate as a cascade-connected current switching circuit, receive complementary logic signals with different DC levels from the constant current source 26 at the input terminal 27.
34 to a selected branch (collector of the transistor). transistor pair 31,
A diode array 35 and a phototransistor or photodiode 36 are attached to the collectors of each of the transistors 32, 33, and 34, and the cathode side electrodes of the photodiodes 36 are connected in common, and a common connection is made between V _put and the ground terminal 38. Connect the load resistor 39. Read output is obtained from V _put . A phototransistor or photodiode with current flowing through it is in a reading state, and a photodiode without current flowing in it is in an integrating state.
By sequentially scanning the branch paths through which current flows, one-dimensional information can be sequentially read.

In each of the above embodiments, the case where 2 ³ =8 photodiode arrays are accessed is explained. However, when accessing 2 ⁿ × m photodiodes, the multithreshold logic circuit shown in Fig. 1 is used. This can be realized by expanding the cascade type current switching circuit of FIG. 2 or 3 to n stages and m pieces. Note that, since the circuit of the present invention operates by disassembling the current source, it has the feature that power consumption can be reduced despite the use of bipolar transistors.

FIG. 4 is a block diagram of an optical reader according to the present invention. This device converts an input selection signal into a complementary signal with a different DC level using a complementary signal generation circuit 40 as shown in FIG. Only a certain photodiode or phototransistor in the phototransistor array 42 is brought into a charged state, and thereby an integrated optical proportional signal is taken out from both ends of the load resistor 43.

Effects of the Invention As is clear from the above description, according to the present invention, an optical reading device with high speed, high resolution, and good linearity can be realized. Furthermore, all functions can be formed on a silicon chip using conventional bipolar processes. Furthermore, the circuit that generates complementary logic signals operates as a non-saturating type, allowing high-speed operation and random access, allowing reading to begin and end at any position. . In addition, since the current switching circuit is connected in cascade with the constant current power supply, the power supply for the scanning circuit is 1
Even if the number of dots in the photoelectric conversion element increases, the number of branches of the current power supply increases, and basically the power consumption does not increase. Since complementary logic signals are input to the base electrodes of the left and right transistors of each transistor pair that make up the current switching circuit, reliable current switching can be performed even if the logic amplitude is as low as 0.6V. , and since the two pulse waveforms forming the complementary logic signal change in opposite directions at the same timing, the induced noise of the logic signal to the image signal output line is canceled and reduced. As described above, the present invention is extremely useful as an input device for information processing equipment, and its industrial effects are significant.

[Brief explanation of drawings]

1 to 4 show an embodiment of the present invention, FIG. 1 is a configuration diagram of a multi-threshold signal generation circuit, FIG. 2 is a configuration diagram of a current switching circuit, and FIG. 3 is a configuration diagram of a current switching circuit. FIG. 4 is a block diagram of the entire optical reading device according to the present invention. 1... Selection signal input terminal, 2... Multi-threshold signal output terminal, 3... Constant current circuit, 4,
5, 6... Current switching transistor pair, 7,
8, 9... Resistor, 10... Level shift diode string, 12... Input terminal, 13... Constant current circuit, 14, 15, 16, 17, 18, 19, 20
... Current switching transistor pair, 21a to 21
h...Switch transistor, 22...Load resistor, 23a-23h...Photodiode, 40
... Complementary signal generation circuit, 41 ... Current switching circuit, 42 ... Photodiode or phototransistor array, 43 ... Load resistance, 44 ... Output signal terminal.

Claims (1)

[Scope of Claims] 1. A current switching circuit formed by connecting a plurality of photoelectric conversion elements and a plurality of transistor pairs that operate in a non-saturated state in a tree-like cascade; It consists of one constant current power supply that supplies current, and a circuit that receives an input selection signal from the outside and generates complementary logic signals with different DC levels. An optical system characterized in that a light proportional signal is read out from the plurality of photoelectric conversion elements by receiving the input terminal and sequentially accessing the plurality of photoelectric conversion elements connected to the output terminal of the current switching circuit. formula reader. 2 The current switching circuit consists of a differential pair of NPN transistors connected in a dendritic cascade, a load resistor connected in series to the differential pair of NPN transistors, and a PNP transistor that senses the current on this load resistor. 2. The optical reading device according to claim 1, wherein the optical reading device is configured to switch a photodiode or a phototransistor connected to the PNP transistor with opposite polarity between an access state and a non-access state. 3 The current switching circuit is connected in cascade.
The optical system according to claim 1, wherein a photodiode or a phototransistor connected to the cascade circuit with a polarity opposite to that of the PNP transistor differential pair is switched between an access state and a non-access state. reader.