JPH0448739A - Wire bonding method - Google Patents
Wire bonding methodInfo
- Publication number
- JPH0448739A JPH0448739A JP2158139A JP15813990A JPH0448739A JP H0448739 A JPH0448739 A JP H0448739A JP 2158139 A JP2158139 A JP 2158139A JP 15813990 A JP15813990 A JP 15813990A JP H0448739 A JPH0448739 A JP H0448739A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- semiconductor chip
- wires
- bonding
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 22
- 238000005452 bending Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85238—Applying energy for connecting using electric resistance welding, i.e. ohmic heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体素子等を製造する際に、半導体チップ
をリードフレーム等の基板に固定後、半導体チップ上の
電極と基板上の電極をワイヤボンディングする方法に関
するものである。Detailed Description of the Invention (Industrial Application Field) The present invention provides a method for manufacturing semiconductor devices, etc., by fixing the semiconductor chip to a substrate such as a lead frame, and then connecting the electrodes on the semiconductor chip and the electrodes on the substrate. The present invention relates to a wire bonding method.
(従来技術とその課題)
半導体チップをパッケージに組み込むには、半・導体チ
ップの電極から外部リード端子への接続が必要で、この
接続方法としては、ネールへラドボンディング方式、超
音波ボンディング方式、サーモソニック方式等がある。(Prior art and its issues) In order to incorporate a semiconductor chip into a package, it is necessary to connect the electrodes of the semiconductor/conductor chip to external lead terminals.This connection method includes Neel-to-rad bonding, ultrasonic bonding, There are thermosonic methods, etc.
近年、IcからLSI、さらには超LSIへの移行に伴
ってlチップ当たりのボンディング数が数十本以上に増
加してきており、従来の接続方法では1本1本ワイヤを
ボンディングする為、効率が悪いものであった。In recent years, with the transition from ICs to LSIs and even VLSIs, the number of bonding wires per chip has increased to more than several dozen, and in the conventional connection method, each wire is bonded one by one, making it less efficient. It was bad.
また、極薄型化の傾向から超低ループでしかもループ垂
れによるタブショートやチップショート等のエツジショ
ートやループ曲がりによるワイヤショートのないボンデ
ィング方法の要望があった。In addition, due to the trend toward ultra-thin devices, there has been a demand for a bonding method that has an ultra-low loop and does not cause edge shorts such as tab shorts or chip shorts due to loop sag, or wire shorts due to loop bending.
(発明の目的)
本発明は、上記従来の課題を解決する為に成されたもの
で、作業効率が良く、薄型化の可能なワイヤボンディン
グ方法を提供するものである。(Objective of the Invention) The present invention was made in order to solve the above-mentioned conventional problems, and provides a wire bonding method that has good work efficiency and can be made thinner.
(発明の構成)
上記課題を解決する為の本発明の技術的手段は、半導体
チップをリードフレーム等の基板に固定し、半導体チッ
プ上の電極と基板上の電極間をワイヤボンディングする
方法において、半導体チップ上の一辺の電極をボンディ
ングするに足る数のワイヤを、多数のリールより繰出し
、移送の途中で徐々に整列集束させた後、その集束ワイ
ヤを半導体チップの一辺の電極及び前記半導体チップと
同一平面上とした基板上の電極間に供給して、前記両電
極に集束ワイヤを側面にて一斉にボンディングし、また
は、半導体チップの電極に続いて、基板上の電極に順次
、一斉にボンディングし、次いでリードフレーム等のワ
イヤを分離させることを特徴とするものである。(Structure of the Invention) The technical means of the present invention for solving the above problems is a method of fixing a semiconductor chip to a substrate such as a lead frame and wire bonding between an electrode on the semiconductor chip and an electrode on the substrate. A sufficient number of wires to bond the electrodes on one side of the semiconductor chip are fed out from a number of reels, and after being gradually aligned and focused during the transfer, the focused wires are bonded to the electrodes on one side of the semiconductor chip and the semiconductor chip. Supply it between electrodes on a substrate that are on the same plane, and bond a focusing wire to both electrodes at the same time on the side, or sequentially bond to the electrodes on the substrate following the electrodes of the semiconductor chip. This method is characterized in that the wires of the lead frame and the like are then separated.
(作用)
上記のように構成された本発明のワイヤボンディング方
法によれば、前記両電極間に整列集束してワイヤが供給
され、または、半導体チップの電極に続いて、基板上の
電極に順次供給されるので、一斉にまたは順次、一斉に
ボンディングでき、半導体チップの電極及びこれと同一
平面上のリードフレーム等の基板の電極とのワイヤ側面
でのボンディングなので、ループを形成することな(、
従ってループ垂れやループ曲がりによるショートのない
ボンディングができるものである。(Function) According to the wire bonding method of the present invention configured as described above, the wire is supplied between the two electrodes in an aligned manner, or the wire is supplied to the electrode of the semiconductor chip and then to the electrode on the substrate. Since the wires are supplied, bonding can be done all at once or sequentially, and since the bonding is done on the side of the wire with the electrodes of the semiconductor chip and the electrodes of a substrate such as a lead frame on the same plane, there is no need to form a loop (
Therefore, bonding can be performed without short circuits due to loop sagging or loop bending.
(実施例) 以下に本発明の詳細について説明する。(Example) The details of the present invention will be explained below.
第1図及び第2図に示す如く、純度99.99%、線径
50μm、材質Auのワイヤ12をリール軸2に支持さ
れた20ケのリールlから繰出し、材質SUSでワイヤ
12の径に対応するガイド溝を有した一次集束装置3、
整列装置4、二次集束装置5、整列装置6及び移送ガイ
ド7から成る集束供給装置8にてワイヤ12のピッチ間
隔0.2mm、本数20本の整列集束して供給されたワ
イヤ12の先端部側面を、基板供給装置9にて供給され
たリードフレームの基板13に固定された半導体チップ
上の電極I5に、超音波ボンディング装置10にて一斉
にボンディングした。その後半導体チップ14をワイヤ
供給方向に移動させワイヤ12を引き出し、次いでリー
ドフレームの基板13の電極16とワイヤ側面とを超音
波ボンディング装置IOにより一斉にボンディングし、
その後ワイヤ12をクランプ固定し、引張りにより切断
した。As shown in FIGS. 1 and 2, a wire 12 with a purity of 99.99%, a wire diameter of 50 μm, and made of Au is fed out from 20 reels l supported on the reel shaft 2, and the diameter of the wire 12 is adjusted with SUS material. a primary focusing device 3 with a corresponding guide groove;
The tips of the wires 12 are aligned and focused, with a pitch interval of 0.2 mm and a number of 20 wires 12, which are fed by a focusing and feeding device 8 comprising an alignment device 4, a secondary focusing device 5, an alignment device 6, and a transfer guide 7. The side surfaces were bonded all at once to the electrodes I5 on the semiconductor chip fixed to the substrate 13 of the lead frame supplied by the substrate supply device 9, using the ultrasonic bonding device 10. After that, the semiconductor chip 14 is moved in the wire supply direction to pull out the wire 12, and then the electrode 16 of the substrate 13 of the lead frame and the side surface of the wire are bonded all at once using an ultrasonic bonding device IO.
Thereafter, the wire 12 was clamped and cut by pulling.
次いで、同様にして他の三辺についてもリードフレーム
等の基板13を順次90°回転し四辺で合計80本のボ
ンディングされた基板11を得た。Next, the substrates 13 such as lead frames were sequentially rotated 90 degrees on the other three sides in the same manner to obtain a total of 80 bonded substrates 11 on the four sides.
なお、第3図に示す如く半導体チップ14上の電極15
及びリードフレームの基板13上の電極16とにワイヤ
12をはわせ、同時にボンディングすれば更に効率的な
ものである。In addition, as shown in FIG. 3, the electrode 15 on the semiconductor chip 14
It will be more efficient if the wire 12 is connected to the electrode 16 on the substrate 13 of the lead frame, and bonding is performed at the same time.
また、リードフレーム等の基板13は長尺の帯材でも短
尺の基材でもいずれでも可能で、長尺においては、−辺
のボンディングに続いて順次他辺のボンディングを連続
する次工程として別のワイヤ12を整列集束して供給し
ボンディングするようにしてもよいものである。更に、
基板13に対してのワイヤ供給方向は長手方向または直
角方向いずれでもよいものである。また、ボンディング
後の切断は実施例における引張りによって切断する際に
例えば第3図に示す如くボンディング時にカッター18
により予め切れ目19を設けておくことにより更に確実
に効率良(ワイヤ12を切断できるものである。In addition, the substrate 13 such as a lead frame can be either a long strip or a short base material, and in the case of a long length, following bonding on the - side, bonding on the other side is performed as a next step. The wires 12 may be aligned and focused and supplied for bonding. Furthermore,
The direction in which the wires are supplied to the substrate 13 may be either the longitudinal direction or the perpendicular direction. Further, when cutting after bonding is performed by tension in the embodiment, for example, as shown in FIG.
By providing the cut 19 in advance, the wire 12 can be cut more reliably and efficiently.
更にまた、本実施例においては、半導体チップ14の電
極15と基板13上の電極16とは等間隔に設計されて
ワイヤ12も平行であるが、例えば基板13上の電極1
6の間隔の方が半導体チップ14の電極間隔よりも広く
、従って平行でない場合でも集束、整列装置等のガイド
溝17の設定により適宜行うようにしてもよいものであ
る。Furthermore, in this embodiment, the electrodes 15 of the semiconductor chip 14 and the electrodes 16 on the substrate 13 are designed to be equally spaced, and the wires 12 are also parallel.
The interval 6 is wider than the interval between the electrodes of the semiconductor chip 14, so even if they are not parallel, it may be done as appropriate by setting the guide groove 17 of a focusing and aligning device.
なお、ボンディング方法は、公知の熱圧着、超音波ボン
ディング等の他、電気抵抗溶接でも可能である。Note that the bonding method may be not only known thermocompression bonding, ultrasonic bonding, etc., but also electric resistance welding.
(発明の効果)
上記のように構成された本発明のボンディング方法によ
れば、電極間隔に整列集束してワイヤが供給され、一斉
にボンディングでき、半導体チップの電極及びリードフ
レーム等の基板の電極とのワイヤ側面でのボンディング
なので、ループを形成することなく、従ってループ垂れ
やループ曲がりによるショートのないボンディングがで
きる等の優れた効果を有するものである。(Effects of the Invention) According to the bonding method of the present invention configured as described above, the wires are supplied aligned and focused at the electrode spacing, and bonding can be performed all at once. Since the bonding is performed on the side surface of the wire, no loops are formed, and therefore bonding can be performed without short circuits due to loop sagging or bending.
第1図及び第2図は、本発明の一実施例におけるワイヤ
供給及び基板供給を示す正面図及び平面図、第3図は本
発明における他のボンディング方法を示す断面図である
。
出願人 田中貴金属工業株式会社
7・・・杼iクヒノ7゛イド1 and 2 are a front view and a plan view showing wire supply and substrate supply in one embodiment of the present invention, and FIG. 3 is a sectional view showing another bonding method in the present invention. Applicant: Tanaka Kikinzoku Kogyo Co., Ltd.
Claims (1)
半導体チップ上の電極と基板上の電極間をワイヤボンデ
ィングする方法において、半導体チップ上の一辺の電極
をボンディングするに足る数のワイヤを、多数のリール
より繰出し、移送の途中で徐々に整列集束させた後、そ
の集束ワイヤを半導体チップの一辺の電極及び前記半導
体チップと同一平面上とした基板上の電極間に供給して
、前記両電極に集束ワイヤを側面にて一斉にボンディン
グし、または、半導体チップの電極に続いて、基板上の
電極に順次、一斉にボンディングし、次いでワイヤを分
離させることを特徴とするワイヤボンディング方法。1) Fix the semiconductor chip to a substrate such as a lead frame,
In a method of wire bonding between electrodes on a semiconductor chip and electrodes on a substrate, a number of wires sufficient to bond one side of the electrodes on the semiconductor chip are fed out from a number of reels and gradually aligned and focused during transport. After that, the focusing wire is supplied between an electrode on one side of the semiconductor chip and an electrode on a substrate that is on the same plane as the semiconductor chip, and the focusing wire is bonded to both electrodes at the same time on the side, or A wire bonding method characterized by sequentially bonding to electrodes on a semiconductor chip, then to electrodes on a substrate, and then separating the wires.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2158139A JPH0448739A (en) | 1990-06-15 | 1990-06-15 | Wire bonding method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2158139A JPH0448739A (en) | 1990-06-15 | 1990-06-15 | Wire bonding method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0448739A true JPH0448739A (en) | 1992-02-18 |
Family
ID=15665122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2158139A Pending JPH0448739A (en) | 1990-06-15 | 1990-06-15 | Wire bonding method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0448739A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130146644A1 (en) * | 2010-08-18 | 2013-06-13 | Sebastian Ruhl | Method and arrangement for welding electrical conductors |
-
1990
- 1990-06-15 JP JP2158139A patent/JPH0448739A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130146644A1 (en) * | 2010-08-18 | 2013-06-13 | Sebastian Ruhl | Method and arrangement for welding electrical conductors |
US8870052B2 (en) * | 2010-08-18 | 2014-10-28 | Schunk Sonosystems Gmbh | Method and arrangement for welding electrical conductors |
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