JPH0448342A - Interface fault processing system - Google Patents

Abstract

PURPOSE:To obtain the log information useful to analysis of the factor of an interface fault by providing a means to a service processor to collect the log information on the processor having a fault interruption and collecting automatically the log information on both the processor where an interface fault is detected and the processor of the remote side. CONSTITUTION:A CPU 11 sets its own fault latch and also the fault latch of an input/output processor A (IOP-A) 12 via a fault setting bus 43. Thus the CPU 11 and the IOP-A 12 recognize their own fault states to freeze themselves in terms of hardware and at the same time generate the fault interruptions to a service processor (SVP) 20 via a diagnostic bus 42. SVP 20 recognizes the CPU 11 shifted to a fault state by a fault interruption and then collects the log information on the CPU 11 via the bus 42 to store them in a log file 30. Thus the log information on both the processor where an interface fault is detected and the processor of the remote side can be timely collected and the fault factor is quickly analyzed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to failure handling of a processing device, and more particularly to failure handling of an inter-processor interface within a processing device.

[Conventional technology]

In conventional devices, a processor that detects an interface failure freezes its hardware and generates a failure interrupt. On the other hand, the service processor always collects log information of the processor that has generated a failure interrupt.

Therefore, at the time of the above failure, log information of the processor that detected the failure was collected.

Note that related devices of this type include, for example, Japanese Unexamined Patent Publication No. 64-91252.

[Problem to be solved by the invention]

In the conventional technology described above, log information of a processor opposite to a processor in which an interface failure has been detected is not collected. - In the case of an inter-processor interface failure, it is more likely that the cause of the failure is in the other processor than in the processor that detected the failure. Therefore, there was a problem in that log information was insufficient, making it difficult to analyze the cause of the failure.

An object of the present invention is to provide log information useful for analyzing the causes of interface failures.

[Means to solve the problem]

In order to achieve the above object, a processor that has detected an interface failure is provided with a simple interface for reporting to the other processor, thereby making it possible to set the failure latch of the other processor.

[Effect]

The partner processor recognizes the transition to the fault state by setting the fault latch.

This freezes the hardware and reports the failure to the service processor.

As a result, the service processor collects log information of the partner processor.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, CPU II, l0P-A12, and l
The OP-B 13 is connected by a system bus 41 and performs control and data transfer during normal operation. On the other hand, CPU
II, IOP-A12, and l0P-B13 are 5V
P20 and a diagnostic bus 42. Also, 5VP
20 is connected to a log file 30. Furthermore, the CPU
No. 11, ○P-A 12, and IOP-B 13 are connected by a fault setting bus 43.

FIG. 2 is an explanatory diagram of the operation of the embodiment of the present invention.

This embodiment shows the operation when the CPU 1 detects an interface failure while the C: PUll and the P-A 12 are processing through the system bus 41. CPU
11 sets its own fault latch and sets the fault latch of l0P-A 12 via the fault setting bus 43.

As a result, the CPU 11 and the 10P-A 12 recognize that they are in a faulty state and hard-freeze themselves. At the same time, the CPU II and the ■○P-A 12 generate a fault interrupt to the 5VP 20 via the diagnostic bus 42.

5VP20 receives C by the fault interrupt mini from CPU11.
Recognize that the PUII has transitioned to a failure state. This causes the 5VP 20 to communicate with the CPU via the diagnostic bus 42.
1 to collect log information and store it in the log file 30.

Next, the second SVP 20 recognizes that the ■○P-A 12 has transitioned to the failure state due to the failure interrupt from the 10P-A 12. As a result, the 5VP 20 collects the log information of the WorkP-A 21 via the diagnostic bus 42 and stores it in the log file 30.

According to this embodiment, the CP that detected the interface failure
This has the effect of being able to collect not only UII log information but also Engineering○P-A12 log information in a timely manner.

〔Effect of the invention〕

According to the present invention, it is possible to timely collect log information not only of the processor in which an interface failure has been detected but also of the other processor, so that the cause of the failure can be quickly analyzed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a processor according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of the operation of one embodiment of the present invention. 11...Central processing processor (CPU), 12...
Input/output processor A (IOP-A), 13... Input/output processor B (IOP-B), 20... Service processor (SVP), 30... Log file,
41...System bus. 42...Diagnosis bus, 43...Fault setting bus, 44...Data bus. A compilation of falcons

Claims (1)

[Claims] 1. In a processing device having a plurality of processors and a service processor, when an interface failure occurs between processors, each processor sets a failure latch of the processor and a failure latch of a partner device when detecting an interface failure; The service processor has means for freezing hardware by setting a fault latch of a processor, and means for generating a fault interrupt in a service processor by setting a fault latch of its own processor, and the service processor generates a fault interrupt. 1. An interface failure handling method, comprising means for collecting log information of a processor in which an interface failure has been detected, and automatically collecting log information of a processor in which an interface failure has been detected and a partner processor.