JPH0448011B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed packet switching system that makes it possible to simplify the control of a high-speed, large-capacity packet switch.

Attempts are being made to connect incoming and outgoing communication paths to packet switching equipment that exchanges large amounts of packets containing information that requires real-time performance, such as voice, through space division switches. There is a strong demand for simplified control in such packet switching equipment as well.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional high-speed packet switching system. In FIG. 4, intersection switches 2 are provided between all incoming communication paths 101 through which high-speed packets arrive and all outgoing communication paths 102 through which high-speed packets are sent out. The control circuit 3 extracts the destination of each high-speed packet arriving from each incoming communication path 101 from the receiving circuit 4, and connects the incoming packet to the intersection switch 2 provided between it and the outgoing communication path 102 corresponding to the destination. The high-speed packet is transferred between the corresponding receiving circuit 4 and transmitting circuit 5.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional high-speed packet switching system, an intersection switch 2 is installed between each input communication path 101 and output communication path 102.
Therefore, as the number of incoming communication paths 101 and outgoing communication paths 102 increases, there is a possibility that the number of intersection switches 2 will increase dramatically. Furthermore, since the control circuit 3 is required to control a large number of intersection switches 2, receiving circuits 4, and transmitting circuits 5 at high speed, the control also needs to be complex and high-speed.

[Means for solving problems]

The present invention solves the above problems by taking the following measures.

That is, in the present invention, a first first-in, first-out buffer for storing packets arriving from each communication path and a second first-in, first-out buffer for storing packets sent to each communication path are provided for each communication path.

A first bus for multiple connection of a predetermined number of output terminals of the first first-in first-out buffers and a second bus for multiple connection of a predetermined number of input terminals of the second first-in first-out buffers are provided.

Further, a third first-in, first-out buffer is provided between all the first buses and all the second buses to accumulate packets transmitted from the first buses and send them to the second buses.

It also sequentially extracts the packets stored in each first first-in, first-out buffer connected to the first bus, decodes the transmission header included in the packet, identifies the transfer destination communication path, and transfers the communication. A first transfer circuit for storing data in a third first-in, first-out buffer corresponding to the first bus is provided for each of the first buses.

Furthermore, the packets stored in each of the third first-in, first-out buffers connected to the second bus are sequentially extracted, the transmission header included in the packet is decoded, the transfer destination communication path is identified, and the communication A second transfer circuit for storing data in a second first-in, first-out buffer corresponding to the second bus is provided for each of the second buses.

[Effect]

That is, according to the present invention, packets arriving from each communication path are accumulated in a corresponding first first-in, first-use buffer, and each first transfer circuit is multiplex-connected to a corresponding first bus. The packets stored in a predetermined number of first first-in, first-out buffers are sequentially extracted, the transmission header included in each packet is decoded, the transfer destination channel is identified, and the packets are stored in the corresponding third first-in, first-out buffer. , each second transfer circuit sequentially extracts the packets stored in each third first-in, first-out buffer provided between the corresponding second bus and each first bus, and extracts the packets contained in each packet. The transmission header is decoded, the transfer destination channel is identified, and the packets are stored in the corresponding second first-in, first-out buffer, and the packets stored in each second first-in, first-out buffer are sequentially sent to the corresponding channel.

Therefore, the third first-in, first-out buffer is provided only between the multiplexed first bus and second bus, and the first or second first-in, first-out buffer is provided within the allowable range of the first and second buses. If the severity is increased, the number of third first-in, first-out buffers can be significantly reduced compared to the intersection switch 2 (FIG. 4) in the conventional high-speed packet switching system.

Furthermore, the control of the first and second transfer circuits is also performed using the control circuit 3 (fourth transfer circuit) of the conventional high-speed packet switching system.
(Figure), it is significantly simplified.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a high-speed packet switching system according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a buffer considering the priority in FIG. 1, and FIG. FIG. 2 is a diagram illustrating an example of a congestion state identification method in FIG. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 1, a buffer 6 is used as a first first-in, first-out buffer for each incoming communication path 10 of each communication path 1.
A buffer 7 as a second first-in first-out buffer is provided corresponding to the output communication path 102 of each communication path 1, and a bus 8 as a first bus is provided corresponding to the output of a predetermined number of buffers 6. A bus 9 serves as a second bus to multiplex connect the input terminals of a predetermined number of buffers 7, and a third bus 9 serves as a second bus.
A buffer 10 is provided as a first-in first-out buffer at the intersection of each bus 8 and 9, a reception transfer circuit 11 is provided as a first transfer circuit corresponding to each bus 8, and a transmission transfer circuit is provided as a second transfer circuit. A circuit 12 is provided corresponding to each bus 9.

In FIG. 1, packets arriving from each input channel 101 are accumulated in each buffer 6 in sequence.
Each reception transfer circuit 11 has a corresponding bus 8.
The buffer 6 connected to the buffer 6 is polled to extract the accumulated packets. Each packet is given a transmission header indicating its destination. Each reception transfer circuit 11 decodes the transmission header of the extracted packet, identifies the output communication path 102 to be transferred, and selects the destination output from among the buffers 10 connected to the corresponding bus 8. The buffer 10 provided at the intersection with the bus 9 to which the buffer 7 corresponding to the communication path 102 is connected is selected, and the data is stored after confirming that the buffer 10 has a storage margin. Each transmission transfer circuit 12 polls the buffer 10 connected to the corresponding bus 9, extracts the accumulated packets, decodes the attached transmission header, and selects the output channel to be transferred. 102 is identified, the corresponding buffer 7 is selected, and the buffer 7 is stored after confirming that there is sufficient storage space. The packets accumulated in each buffer 7 are sequentially extracted and sent to the outgoing communication path 102. Note that if storage margin cannot be found in each buffer 10 or 7, the reception transfer circuit 11 or transmission transfer circuit 12 must discard the packet to be transferred. is set so that the probability of discarding is sufficiently low.

Next, when packets arriving from each communication channel 1 include voice packets that require particularly strong real-time performance and data packets that do not require real-time performance, high priority is assigned to the voice packets. information,
Low priority information is given to data packets. The buffer 10 also includes a high priority buffer 103 for storing high priority packets, as shown in FIG.
Low priority buffer 1 that stores low priority packets
04 is provided, and an accumulation amount measuring circuit 105 is provided.
and 106 are respectively high priority buffers 103
and the amount of information (number of bytes) stored in the low priority buffer 104, and packet counters 107 and 108 count the number of packets stored in the high priority buffer 103 and low priority buffer 104, respectively. are doing. The same applies to the buffer 7.

In FIG. 2, when the reception transfer circuit 11 identifies that the packet extracted from the buffer 6 is of high priority, it transmits the high priority signal to the selected buffer 10 via the signal line 81 in the bus 8, and
A storage amount notification request signal is transmitted via the signal line 82. In the buffer 10 that has received the high priority signal and the storage amount notification request signal, the switch 10
9 returns the accumulated amount of the high priority buffer 103 measured by the accumulated amount measuring circuit 105 to the reception transfer circuit 11 via the signal line 83. Reception transfer circuit 1
1 is a high priority buffer 10 from the received storage amount.
If it is determined that buffer 3 has storage room, the high priority packet is transferred to high priority buffer 1 via signal line 84.
Accumulate in 03.

On the other hand, the switch 110 controls the packet counter 10.
If there is even one high priority packet stored in the high priority buffer 103, a signal of logical value 1 is output to the signal line 91 in the bus 9. gate 9
2 is all buffers 1 connected to bus 9.
The logical sum of the signals output from the 0 signal line 91 is taken and transmitted to the corresponding transmission transfer circuit 12 via the signal line 93.

Therefore, when a signal with a logical value of 1 is transmitted from the gate 92 via the signal line 93, the transmission transfer circuit 12 determines that a high-priority packet is accumulated in one of the corresponding buffers 10. A high priority signal is transmitted to the selected buffer 10 via the signal line 94.

In the buffer 10 that has received the high priority signal, the switch 110 notifies the transmission transfer circuit 12 of the number of high priority packets counted by the packet counter 107 via the signal line 95. When the transmission transfer circuit 12 confirms that the number of high-priority packets received from the selected buffer 10 is not 0, it transfers the high-priority packets to the high-priority buffer 10 via the signal line 96.
Extract the high priority packets stored in 3. Note that if the transfer destination buffer 7 is also differentiated by priority, the data is accumulated in the high priority buffer.

Next, in FIG.
12 is the buffer 1 selected by the reception transfer circuit 11.
The storage amount notified from 0 is compared with the threshold values transmitted from threshold circuits 113 and 114, and the comparison result is transmitted to control circuit 115. Control circuit 115
When receiving a comparison result from the comparison circuit 111 that the accumulated amount notified from the buffer 10 is equal to or greater than the threshold value for identifying the congestion state transmitted from the threshold value circuit 113, the congestion circuit 116 corresponding to the selected buffer 10 is set to the congestion state. (logical value 1). Further, the comparison circuit 112 receives a comparison result that the accumulated amount notified from the buffer 10 in the congested state is less than or equal to the threshold value (set lower than the threshold value for identifying the congested state) for identifying congestion resolution transmitted from the threshold value circuit 114. When received from the selected buffer 10
The congestion circuit 116 corresponding to is set to a non-congestion state (logical value 0). A control circuit (not shown) can identify the congestion state of the buffer 10 by referring to the congestion circuit 116 in the reception transfer circuit 11, thereby making it possible to control the required flow rate.

As is clear from the above description, according to this embodiment, each reception transfer circuit 11 and each transmission transfer circuit 1
2, the transfer of packets via the highly efficiently multiplexed buses 8 and 9 can be independently controlled via the buffer 10, making it possible to perform high-speed, large-capacity packet exchange with relatively simple control. Become. Also, high priority packets can be transferred preferentially. Furthermore, the congestion state of the buffer 10 etc. can also be identified.

Note that FIGS. 1 to 3 are only one embodiment of the present invention, and for example, the priority of packets is not limited to two types, high and low, and many other variations can be considered. In either case, the effects of the present invention remain the same. Furthermore, the congestion state of the buffer 10 is not limited to what is identified by the reception transfer circuit 11, and identification by the transmission transfer circuit 12 is also considered, but the effects of the present invention do not change even in such a case.

〔Effect of the invention〕

As described above, according to the present invention, a high-speed, large-capacity packet switch can be realized with relatively simple control.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a high-speed packet switching system according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a buffer considering the priority in FIG. 1, and FIG. FIG. 4 is a diagram showing an example of a conventional high-speed packet switching method. In the figure, 1 is a communication path, 2 is an intersection switch,
3 and 115 are control circuits, 4 is a reception circuit, 5 is a transmission circuit, 6, 7 and 10 are buffers, 8 and 9 are buses, 11 is a reception transfer circuit, 12 is a transmission transfer circuit, 81 to 84, 91 and 93 〜96
is a signal line, 92 is a gate, 101 is an input communication path, 1
02 is an outgoing communication path, 103 is a high priority buffer, 1
04 is a low priority buffer, 105 and 106 are storage amount measuring circuits, 107 and 108 are packet counters, 109 and 110 are switches, 11
1 and 112 are comparison circuits, 113 and 114
indicates a threshold circuit, and 116 indicates a congestion circuit.

Claims (1)

[Scope of Claims] 1. In a packet switch that transfers packets arriving from a plurality of communication paths to a communication path according to a destination, a first first-in, first-out buffer that accumulates packets arriving from each of the communication paths; A second first-in, first-out buffer for accumulating packets to be sent out to the first bus is provided for each of the communication channels; A second bus that multiplex connects the input terminals of two first-in, first-out buffers is provided, and the packets transmitted from the corresponding first bus are accumulated, and the packets transmitted from the corresponding second bus are
A third first-in, first-out buffer is provided between all of the first buses and all of the second buses, and a third first-in, first-out buffer is provided between each of the first first-in, first-out buffers connected to the first bus. A first transfer circuit for sequentially extracting packets stored in a buffer and storing them in the third first-in, first-out buffer corresponding to a transmission header included in the packet is provided for each of the first buses, A second buffer that sequentially extracts packets stored in each of the third first-in, first-out buffers connected to the second bus and accumulates them in the second first-in, first-out buffer corresponding to the transmission header included in the packet. A high-speed packet switching system characterized in that a transfer circuit is provided for each of the second buses. 2. The second and third first-in, first-out buffers are provided for each priority of the packet, and the first transfer circuit transfers the third first-in, first-out buffer corresponding to the priority of the packet extracted from the first first-in, first-out buffer. The second
Claim 1, wherein the transfer circuit first extracts packets from the third first-in, first-out buffer corresponding to a high priority and stores them in the second first-in, first-out buffer having a corresponding priority.
High-speed packet switching method described in Section 1. 3. The high-speed transfer circuit according to claim 1, wherein the first or second transfer circuit identifies the congestion state of each second or third first-in-first-out buffer when extracting or storing packets. Packet exchange method.