JPH0447975B2 - - Google Patents
Info
- Publication number
- JPH0447975B2 JPH0447975B2 JP58091778A JP9177883A JPH0447975B2 JP H0447975 B2 JPH0447975 B2 JP H0447975B2 JP 58091778 A JP58091778 A JP 58091778A JP 9177883 A JP9177883 A JP 9177883A JP H0447975 B2 JPH0447975 B2 JP H0447975B2
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- mosfets
- conductive pads
- straight line
- triangle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000005259 measurement Methods 0.000 claims description 16
- 239000002184 metal Substances 0.000 description 23
- 239000000523 sample Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Description
【発明の詳細な説明】
本発明は、半導体装置に関し、特に特性測定用
半導体素子を含む半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device including a semiconductor element for measuring characteristics.
最近の半導体集積回路においては、高集積化、
素子の微細化が、各種加工技術の進歩により急速
に進んでおり、半導体素子及び配線等が小さくな
り、同一の回路規模の場合、年々、そのチツプ面
積は減少している。しかし、その一方、集積回路
内に内蔵される特性測定用半導体素子は、その素
子自体は小さくなつているが、測定する時に外部
より探針を接触させる為の金属パツドは、その測
定時の探針の位置合わせの容易性を考慮すると、
小さな面積とする事ができない。又、この特性測
定用半導体素子は、探針接触作業時に他の素子や
配線等を傷つける事がないように他の素子や配線
より、ある程度の距離をおいて設ける必要があ
る。これに加えるに、例えばMOSFETの場合、
より多くのしきい値電圧を用いる回路設定がなさ
れるため、測定すべきMOSFETのパターン数が
増加してきている。 In recent semiconductor integrated circuits, high integration,
The miniaturization of elements is progressing rapidly due to advances in various processing techniques, and semiconductor elements, wiring, etc. are becoming smaller, and the chip area for the same circuit size is decreasing year by year. However, on the other hand, although the semiconductor elements built into integrated circuits for measuring characteristics have become smaller, the metal pads used to bring the probe into contact with them from the outside during measurement have become smaller. Considering the ease of needle alignment,
It cannot be made into a small area. Further, this semiconductor element for measuring characteristics needs to be placed at a certain distance from other elements and wiring so as not to damage other elements and wiring during probe contact work. In addition to this, for example, in the case of MOSFET,
As circuits are configured to use more threshold voltages, the number of MOSFET patterns to be measured is increasing.
第1図a〜cは従来の特性測定用MOSFETの
平面図、回路記号図及び金属パツドに測定用探針
を接触させた場合の断面図である。なお、第1図
aでは構造を明確に示すため酸化膜は省略してあ
る。 FIGS. 1a to 1c are a plan view, a circuit symbol diagram, and a sectional view of a conventional MOSFET for measuring characteristics when a measuring probe is brought into contact with a metal pad. Note that the oxide film is omitted in FIG. 1a to clearly show the structure.
第1図a〜cに示したように、半導体基板10
上に形成されたソース領域1及びドレイン領域2
は酸化膜5の開孔部3を通して金属パツドA及び
Bに接続している。そしてゲート電極4を形成す
るポリシリコン層は、同様に開孔部3を通して金
属パツドCに接続している。金属パツドは測定用
探針6を接触させるため一定の面積以下とするこ
とはできず、従つてMOSFETの大部分の面積は
金属パツドが占めている。 As shown in FIGS. 1a-c, a semiconductor substrate 10
Source region 1 and drain region 2 formed on
are connected to metal pads A and B through openings 3 in oxide film 5. Similarly, the polysilicon layer forming the gate electrode 4 is connected to the metal pad C through the opening 3. Since the metal pad makes contact with the measurement probe 6, the area cannot be smaller than a certain level, and therefore the metal pad occupies most of the area of the MOSFET.
従つて多くのしきい値電圧を有する回路設計が
なされた場合、その種類分の測定用MOSFETを
同一チツプ内に形成するため、測定用MOSFET
の占める割合は大きくなり、有効素子形成領域の
割合が小さくなるという欠点がある。 Therefore, when a circuit with many threshold voltages is designed, the measurement MOSFETs for those types are formed on the same chip.
The disadvantage is that the proportion occupied by the area becomes large and the proportion of the effective element forming area becomes small.
本発明の目的は、上記欠点を除去し、測定用
MOSFETの面積を小さくして有効素子形成領域
を割合を大きくし、集積度の向上した半導体装置
を提供することにある。 The purpose of the present invention is to eliminate the above-mentioned drawbacks and to
The object of the present invention is to provide a semiconductor device with an improved degree of integration by reducing the area of a MOSFET and increasing the ratio of an effective element formation area.
本発明による半導体装置は、同装置に設けられ
る特性測定用半導体素子が夫々が第1および第2
の領域とこれら領域間にゲート絶縁膜を介して形
成されたゲート電極とを有する第1、第2および
第3のMOSFETを含み、前記第1および第3の
MOSFETは同一直線上に配置され、前記第2の
MOSFETは前記直線と並行な他の直線上の前記
第1のMOSFETと第3のMOSFETとの間に配
置されており、前記第2のMOSFETのゲート電
極は前記直線に直交する方向に延びて前記第1お
よび第3のMOSFETの第1の領域同士を接続す
る第1の導電パツドに接続され、前記第1および
第3のMOSFETのゲート電極は前記直線に直交
する方向に延びて前記第2のMOSFETの第1お
よび第2の領域に各々接続された第2および第3
の導電パツドにそれぞれ接続され、さらに前記第
1および第3のMOSFETの第2の領域にそれぞ
れ接続された第4および第5の導電パツドが設け
られていることを特徴としている。 In the semiconductor device according to the present invention, the characteristic measuring semiconductor elements provided in the device are first and second semiconductor elements, respectively.
and a gate electrode formed between these regions with a gate insulating film interposed therebetween.
The MOSFETs are arranged on the same straight line, and the second
The MOSFET is arranged between the first MOSFET and the third MOSFET on another straight line parallel to the straight line, and the gate electrode of the second MOSFET extends in a direction perpendicular to the straight line. The gate electrodes of the first and third MOSFETs are connected to a first conductive pad that connects the first regions of the first and third MOSFETs, and the gate electrodes of the first and third MOSFETs extend in a direction perpendicular to the straight line. a second and a third connected to the first and second regions of the MOSFET, respectively;
The present invention is characterized in that fourth and fifth conductive pads are provided, each connected to the second region of the first and third MOSFETs.
次に、本発明の実施例を図面を用いて詳細に説
明する。 Next, embodiments of the present invention will be described in detail using the drawings.
第2図a,bは本発明の一実施例の平面図及び
回路記号図である。第2図aは第1図aの場合と
同様に酸化膜を省略してある。 FIGS. 2a and 2b are a plan view and a circuit symbol diagram of an embodiment of the present invention. In FIG. 2a, the oxide film is omitted as in the case of FIG. 1a.
第2図a,bに示すように半導体基板上にはソ
ース領域1、ドレイン領域2及びゲート電極4を
有する3個の測定用MOSFETTr1,Tr2,Tr
3が形成されており、それぞれの端子は5個の金
属パツドA〜Eに接続している。特に金属パツド
Cには第1のMOSFET:Tr1のドレイン電極、
第2のMOSFET:Tr2のゲート電極及び第3の
MOSFET:Tr3のソース電極が接続している。
このように形成された3個の測定用MOSFETに
おいては、金属パツドの占める割合は従来のもの
に比べ5/9となる。この値は測定用MOSFETの
数が更に多い場合は、3個の電極に接続する金属
パツドの数がふえるため1/3に近ずくことになる。
すなわち、測定用MOSFETの占める割合は従来
の場合の1/3近くとなり、それだけ有効素子形成
領域の割合が増加する。 As shown in FIGS. 2a and 2b, three measurement MOSFETs Tr1, Tr2, and Tr having a source region 1, a drain region 2, and a gate electrode 4 are mounted on the semiconductor substrate.
3 are formed, and each terminal is connected to five metal pads A to E. In particular, the metal pad C has the drain electrode of the first MOSFET: Tr1,
Second MOSFET: Tr2 gate electrode and third MOSFET
MOSFET: The source electrode of Tr3 is connected.
In the three measurement MOSFETs formed in this way, the proportion occupied by metal pads is 5/9 compared to the conventional one. If there are more MOSFETs for measurement, this value will approach 1/3 because the number of metal pads connected to the three electrodes will increase.
In other words, the ratio occupied by the measurement MOSFET is nearly 1/3 that of the conventional case, and the ratio of the effective element formation area increases accordingly.
次にこれらのMOSFETの特性を測定する方法
について説明する。 Next, we will explain how to measure the characteristics of these MOSFETs.
第3図a〜cは第2図a,bに示す本発明の一
実施例の特性測定方法を説明するための回路記号
図である。 FIGS. 3a to 3c are circuit symbol diagrams for explaining the characteristic measuring method of the embodiment of the present invention shown in FIGS. 2a and 2b.
まず第3図aに示すようにTr1の特性を測定
する場合は、金属パツドD,Eを短絡状態とし、
金属パツドA,B,Cにそれぞれ接地電位VE、
ゲート電位VA及びドレイン電位VBを与えるよう
に3本の測定用探針を接触させてTr1の静特性
を測定する。この場合Tr2及びTr3は何ら影響
を及ぼすことはない。 First, as shown in Figure 3a, when measuring the characteristics of Tr1, short-circuit metal pads D and E,
Ground potential V E is applied to metal pads A, B, and C, respectively.
The static characteristics of Tr1 are measured by bringing three measurement probes into contact so as to give a gate potential V A and a drain potential V B. In this case, Tr2 and Tr3 have no influence.
次にTr2を測定する場合は半導体基板を180°
回転し、第3図bに示すように金属パツドE,A
を短絡し、金属パツドB,C,DをそれぞれVB,
VA及びVEとするように測定用探針を接触させて
静特性を測定する。この場合Tr1及びTr3はTr
2の測定に影響することはない。 Next, when measuring Tr2, rotate the semiconductor substrate at 180°.
The metal pads E and A rotate as shown in Figure 3b.
short-circuit and connect metal pads B, C, and D to V B , respectively.
Measure the static characteristics by touching the measurement probe so that V A and V E. In this case, Tr1 and Tr3 are Tr
It does not affect the measurement of 2.
Tr3を測定する場合には第3図cに示すよう
に、Tr1の場合と同様に金属パツドC,D,E
がVE、VA及びVBとなるように測定用探針を接触
させて静特性を測定する。この場合もTr1及び
Tr2は測定に影響しない。 When measuring Tr3, as shown in Figure 3c, metal pads C, D, and E are used as in the case of Tr1.
The static characteristics are measured by touching the measuring probe so that V E , V A and V B are applied. In this case as well, Tr1 and
Tr2 does not affect the measurement.
第2図aに示す金属パツドA,B,C,D,E
の大きさを同一とし、各金属パツドの中心を頂点
とする三角形、例えば金属パツドABC,BCD,
CDEの頂点で形成される三角形が正三角形にな
るように形成すれば、金属パツドに接触させる探
針間の相互の位置を変える必要がなくなるため
MOSFETの特性測定を作業性よく行うことがで
きる。 Metal pads A, B, C, D, E shown in Figure 2a
A triangle with the same size and the center of each metal pad as its apex, for example, metal pads ABC, BCD,
If the triangle formed by the vertices of the CDE is formed as an equilateral triangle, there is no need to change the mutual positions of the probes in contact with the metal pad.
MOSFET characteristics can be measured with ease.
以上詳細に説明したように、本発明によれば、
測定用MOSFETの金属パツドを特性測定に影響
しないように共通に利用することによりその数を
少くし、有効素子形成領域の割合を大きくした半
導体装置が得られるのでその効果は大きい。 As explained in detail above, according to the present invention,
By commonly using the metal pads of the MOSFETs for measurement so as not to affect the characteristic measurements, the number of metal pads can be reduced and a semiconductor device with a larger proportion of the effective element formation area can be obtained, which is highly effective.
第1図a〜cは従来の特性測定用MOSFETの
平面図、回路記号図及び金属パツドに測定用探針
を接触させた場合の断面図、第2図a,bは本発
明の一実施例の平面図及び回路記号図、第3図a
〜cは第2図a,bに示す本発明の一実施例の特
性測定を説明するための回路記号図である。
1……ソース領域、2……ドレイン領域、3…
…開孔部、4……ゲート電極、5……酸化膜、6
……探針、10……半導体基板、Tr1……第1
のMOSFET、Tr2……第2のMOSFET、Tr3
……第3のMOSFET、A,B,C,D,E……
金属パツド。
Figures 1 a to c are a plan view, a circuit symbol diagram, and a sectional view of a conventional MOSFET for measuring characteristics, and a cross-sectional view when a measuring probe is brought into contact with a metal pad, and Figures 2 a and b are an embodiment of the present invention. Plan view and circuit symbol diagram, Figure 3a
-c are circuit symbol diagrams for explaining characteristic measurement of an embodiment of the present invention shown in FIGS. 2a and 2b. 1... Source region, 2... Drain region, 3...
...Opening portion, 4...Gate electrode, 5...Oxide film, 6
...Tip, 10...Semiconductor substrate, Tr1...1st
MOSFET, Tr2...Second MOSFET, Tr3
...Third MOSFET, A, B, C, D, E...
Metal pad.
Claims (1)
いて、前記特性測定用半導体素子は夫々が第1お
よび第2の領域とこれら領域間にゲート絶縁膜を
介して形成されたゲート電極とを有する第1、第
2および第3のMOSFETを含み、前記第1およ
び第3のMOSFETは同一直線上に配置され、前
記第2のMOSFETは前記直線と並行な他の直線
上の前記第1のMOSFETと第3のMOSFETと
の間に配置されており、前記第2のMOSFETの
ゲート電極は前記直線に直交する方向に延びて前
記第1および第3のMOSFETの第1の領域同士
を接続する第1の導電パツドに接続され、前記第
1および第3のMOSFETのゲート電極は前記直
線に直交する方向に延びて前記第2のMOSFET
の第1および第2の領域に各各接続された第2お
よび第3の導電パツドにそれぞれ接続され、さら
に前記第1および第3のMOSFETの第2の領域
にそれぞれ接続された第4および第5の導電パツ
ドが設けられていることを特徴とする半導体装
置。 2 前記第1、第2および第3の導電パツドの中
心を頂点とする三角形、前記第1、第2および第
4の導電パツドの中心を頂点とする三角形、なら
びに前記第1、第3および第5の導電パツドの中
心を頂点とする三角形がそれぞれ正三角形となる
ように前記第1乃至第5の導電パツドが形成され
ていることを特徴とする特許請求の範囲第1項記
載の半導体装置。[Scope of Claims] 1. In a semiconductor device including a semiconductor element for characteristic measurement, each of the semiconductor elements for characteristic measurement has a first region and a second region, and a gate electrode formed between these regions with a gate insulating film interposed therebetween. , the first and third MOSFETs are arranged on the same straight line, and the second MOSFET is arranged on the same straight line parallel to the straight line. The gate electrode of the second MOSFET extends in a direction perpendicular to the straight line and connects the first regions of the first and third MOSFETs. The gate electrodes of the first and third MOSFETs extend in a direction perpendicular to the straight line and connect to the second MOSFET.
second and third conductive pads respectively connected to the first and second regions of the MOSFET, and fourth and third conductive pads respectively connected to the second regions of the first and third MOSFETs. 1. A semiconductor device comprising: 5 conductive pads. 2. A triangle having apexes at the centers of the first, second and third conductive pads, a triangle having apexes at the centers of the first, second and fourth conductive pads, and a triangle having apexes at the centers of the first, second and fourth conductive pads; 2. The semiconductor device according to claim 1, wherein the first to fifth conductive pads are formed such that each triangle having an apex at the center of the fifth conductive pad is an equilateral triangle.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9177883A JPS59217350A (en) | 1983-05-25 | 1983-05-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9177883A JPS59217350A (en) | 1983-05-25 | 1983-05-25 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59217350A JPS59217350A (en) | 1984-12-07 |
JPH0447975B2 true JPH0447975B2 (en) | 1992-08-05 |
Family
ID=14036042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9177883A Granted JPS59217350A (en) | 1983-05-25 | 1983-05-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59217350A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5743453A (en) * | 1980-08-28 | 1982-03-11 | Nec Corp | Integrated circuit |
-
1983
- 1983-05-25 JP JP9177883A patent/JPS59217350A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5743453A (en) * | 1980-08-28 | 1982-03-11 | Nec Corp | Integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS59217350A (en) | 1984-12-07 |
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