JPH0447967Y2 - - Google Patents
Info
- Publication number
- JPH0447967Y2 JPH0447967Y2 JP1985082821U JP8282185U JPH0447967Y2 JP H0447967 Y2 JPH0447967 Y2 JP H0447967Y2 JP 1985082821 U JP1985082821 U JP 1985082821U JP 8282185 U JP8282185 U JP 8282185U JP H0447967 Y2 JPH0447967 Y2 JP H0447967Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- terminal
- integrated circuit
- terminals
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 34
- 239000004020 conductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】
〔技術分野〕
本考案は遅延線のように主にコイルとコンデン
サを構成要素に含む回路を集積回路の外に接続し
てなる混成回路に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a hybrid circuit formed by connecting a circuit, such as a delay line, whose components mainly include a coil and a capacitor to the outside of an integrated circuit.
近時ほとんどの電子回路は集積回路化される傾
向にあるが、インダクタンスを含む回路、例えば
コイルとコンデンサを組合せて構成される遅延線
の回路のように集積回路化が困難なものもあり、
全体の回路にこのような回路を含む場合には集積
回路の外部に接続する必要が生ずる。TTL素子
を用いた飽和型論理回路に遅延線を組合せてパツ
フアードデイレーラインを構成する場合もこのよ
うな例に相当する。
Recently, most electronic circuits have tended to be integrated circuits, but there are some circuits that include inductance, such as delay line circuits made up of a combination of coils and capacitors, which are difficult to integrate.
If such a circuit is included in the overall circuit, it will be necessary to connect it to the outside of the integrated circuit. This also applies to the case where a saturated logic circuit using TTL elements is combined with a delay line to form a puffed delay line.
そしてプリント基板上にコイルやコンデンサを
配置して遅延線の回路を構成し、集積回路のパツ
ケージ上にその基板を載置してパツケージの端子
を介して遅延線の回路と集積回路を接続し、外部
端子をデユアルインラインパツケージ(以下DIP
という)の外部に露呈させた混成回路は実開昭58
−89953号公報、実開昭59−67947号公報によつて
すでに公知である。 Then, a delay line circuit is constructed by arranging coils and capacitors on a printed circuit board, the board is placed on an integrated circuit package, and the delay line circuit and the integrated circuit are connected through the terminals of the package. Connect external terminals to dual inline package (hereinafter referred to as DIP)
The hybrid circuit exposed to the outside of the
This method is already known from Japanese Utility Model Application No. 89953 and Japanese Utility Model Application Publication No. 59-67947.
しかしこのような混成回路において、小さな回
路素子を、集積回路のパツケージ上に載置される
程度の狭い基板の所定位置に多数取付けて接続
し、集積回路外に別の回路を構成することは自動
機械を充分に使うことが難しいので手作業が多く
なり組立工数を要する。又回路素子の互の位置を
固定するためにわざわざ基板を用いることも混成
回路の構成要素が多くなり無駄が多い。 However, in such hybrid circuits, many small circuit elements are attached and connected at predetermined positions on a narrow board that is placed on the integrated circuit package, and it is not automatic to configure another circuit outside the integrated circuit. Since it is difficult to use machines sufficiently, there is a lot of manual labor and assembly man-hours are required. Moreover, using a substrate to fix the mutual positions of circuit elements increases the number of components of the hybrid circuit, which is wasteful.
本考案の目的は板状のコンデンサブロツクを集
積回路の外に別の回路を構成するための基板とし
て兼用すると共に、コンデンサの基板への取付作
業を不要にすることにより、混成回路の組立作業
を容易にすることにある。
The purpose of this invention is to use a plate-shaped capacitor block as a board for configuring another circuit in addition to the integrated circuit, and to eliminate the need to attach the capacitor to the board, thereby simplifying the assembly work of hybrid circuits. It's about making it easier.
本考案の混成回路は複数の独立したコンデンサ
が内部に形成してあり、夫々のコンデンサの電極
の端を側辺に露呈させてある板状のコンデンサブ
ロツクと集積回路のパツケージを重ね合せると共
にコンデンサブロツクの主表面に回路素子を固着
してあり、該回路素子、前記コンデンサ、集積回
路を該集積回路の端子を用いて相互に接続してな
ることを特徴とする。
The hybrid circuit of the present invention has a plurality of independent capacitors formed inside, and a plate-shaped capacitor block with the electrode end of each capacitor exposed on the side and an integrated circuit package are stacked on top of each other. A circuit element is fixed to the main surface of the capacitor, and the circuit element, the capacitor, and the integrated circuit are interconnected using terminals of the integrated circuit.
以下に理解を容易にするために構成を単純にし
てある第5図のパツフアードデイレーラインの回
路図を例にとり、本考案の混成回路の実施例を第
1図から第4図を参照しながら説明する。第1図
は混成回路の斜視図、第2図は第1図の長さ方向
からの正面図、第3図はコンデンサブロツクの拡
大横断面図、第4図は遅延線の回路と集積回路の
接続の説明図を夫々示している。なお第1図では
外部端子を除いた状態を示してある。
Taking as an example the circuit diagram of the packed delay line shown in FIG. 5, whose configuration is simplified for ease of understanding, the embodiments of the hybrid circuit of the present invention will be described with reference to FIGS. 1 to 4. I will explain while doing so. Figure 1 is a perspective view of the hybrid circuit, Figure 2 is a longitudinal front view of Figure 1, Figure 3 is an enlarged cross-sectional view of the capacitor block, and Figure 4 shows the delay line circuit and integrated circuit. An explanatory diagram of the connections is shown respectively. Note that FIG. 1 shows the state without external terminals.
第5図においてG1からG4まではTTL素子、
1は入力端子、2と3は出力端子、VCは電源端
子、Eはアース端子である。点線で囲まれた部分
が遅延線を構成しており、素子G1から素子G4
までは集積回路内に構成される。 In Fig. 5, G1 to G4 are TTL elements,
1 is an input terminal, 2 and 3 are output terminals, V C is a power supply terminal, and E is an earth terminal. The part surrounded by the dotted line constitutes a delay line, and is connected from element G1 to element G4.
are configured within an integrated circuit.
コンデンサブロツク10は電極12を形成した
誘電体シート、例えばセラミツクのグリーンシー
トを重ね合せて成形したものであり、内部には第
5図における2個のコンデンサC1,C2が形成
されている。コンデンサC1,C2の形成されて
いる部分の横断面には第3図に示すように電極1
2A,12Bが存在し、側辺の溝にその端を露呈
させて電極端子を形成してある。実施例ではコン
デンサC1,C2の片側がいずれもアースされる
ので、アース側の電極12Bの端を溝13Eに共
通に露呈させて電極端子14Eを形成し、ホツト
側の2組の電極12Aの端を溝13Aと溝13B
に別々に露呈させて電極端子14A,14Bを形
成してある。第3図は対向する両側辺の溝13
A、溝13C間の横断面図である。コンデンサC
1,C2の電極端子の形成されていない他の溝、
つまり溝13Eを除く溝13Cから溝13Jまで
にも端子15を形成してあり、コンデンサの電極
に直接接続する電極端子とは異りコンデンサブロ
ツク10の主表面16に形成する導体パターン1
7や集積回路のフラツトパツケージ11の端子を
接続する役割をする。 The capacitor block 10 is formed by stacking dielectric sheets, such as ceramic green sheets, on which electrodes 12 are formed, and two capacitors C1 and C2 shown in FIG. 5 are formed inside. As shown in FIG.
2A and 12B are present, and their ends are exposed in the grooves on the sides to form electrode terminals. In the embodiment, since both sides of the capacitors C1 and C2 are grounded, the ends of the electrodes 12B on the ground side are commonly exposed in the groove 13E to form the electrode terminals 14E, and the ends of the two sets of electrodes 12A on the hot side are exposed in common to the groove 13E. groove 13A and groove 13B
Electrode terminals 14A and 14B are formed by exposing them separately. Figure 3 shows grooves 13 on opposite sides.
A is a cross-sectional view between grooves 13C. Capacitor C
1, another groove in which no electrode terminal of C2 is formed;
In other words, terminals 15 are also formed from groove 13C to groove 13J, excluding groove 13E, and unlike electrode terminals that are directly connected to the electrodes of the capacitor, the conductor pattern 1 formed on the main surface 16 of the capacitor block 10
7 and the terminals of the flat package 11 of the integrated circuit.
導体パターン17は第1図、第4図に示すよう
に溝13A,13B,13Eの夫々の電極端子1
4A,14B,14Eに接続すると共に溝13C
から溝13Jまでの端子15に接続する。溝13
Gと溝13Jの端子15は裏側の主表面16の導
体パターン17により接続している。そして第5
図のコイルL1,L2、終端抵抗R1,R2に対
応する回路素子が導体パターン17に接続した状
態で主表面16に固着されており、第5図で点線
で囲み示してある遅延線の回路がコンデンサブロ
ツク10上に形成される。 The conductor pattern 17 is connected to each electrode terminal 1 of the grooves 13A, 13B, and 13E as shown in FIGS.
4A, 14B, 14E and groove 13C
Connect to the terminal 15 from the groove 13J to the groove 13J. Groove 13
G and the terminal 15 of the groove 13J are connected by a conductor pattern 17 on the main surface 16 on the back side. and the fifth
Circuit elements corresponding to the coils L1, L2 and terminating resistors R1, R2 in the figure are fixed to the main surface 16 while being connected to the conductor pattern 17, and the delay line circuit shown surrounded by dotted lines in FIG. It is formed on the capacitor block 10.
このように構成されたコンデンサブロツク10
と、G1からG4までのTTL素子の形成されて
いる集積回路のフラツトパツケージ11を第1図
のように重ね合せる。そしてパツケージ11の側
辺から水平に突出している端子を垂直に折り曲げ
て同じ英字の付されているコンデンサブロツク1
0の溝に嵌め込み電極端子や端子に半田付けす
る。例えば端子18Aは溝13A、端子18Bは
溝13B、端子18Cは溝13Cというように嵌
め込み、夫々電極端子14A、電極端子14B、
端子15に接続する。第4図ではパツケージ11
の端子の嵌め込む溝を夫々矢印で示してある。パ
ツケージ11の端子18X、端子18Yは溝に嵌
め込まれることなくコンデンサブロツク10の下
で夫々外部端子19X、外部端子19Yに接続さ
れる。端子18D、端子18E、集積回路の電源
用の端子である端子18Gも夫々外部端子19
D、外部端子19E、外部端子19Gに接続され
る。外部端子は第4図では丸印で示してあるが、
第1図に示すようにL型の水平部の先端を下側に
屈曲させた形状であり、先端に設けた溝20にパ
ツケージ11の端子の垂直部分を嵌め込み半田付
けして接続するものである。第2図は外部端子が
パツケージ11の端子に接続された状態を示して
いるが、最終的には1点鎖線で示すように全体を
樹脂封止してDIPを形成し、外部端子だけをその
外側に露呈させる構造が望ましい。 Capacitor block 10 configured in this way
and the integrated circuit flat package 11 in which TTL elements G1 to G4 are formed are stacked together as shown in FIG. Then, the terminals protruding horizontally from the sides of the package 11 are bent vertically to form a capacitor block 1 with the same alphabetic characters.
Fit it into the groove of 0 and solder it to the electrode terminal or terminal. For example, the terminal 18A is fitted into the groove 13A, the terminal 18B is fitted into the groove 13B, the terminal 18C is fitted into the groove 13C, and the electrode terminal 14A, electrode terminal 14B,
Connect to terminal 15. In Figure 4, package 11
The grooves into which the terminals fit are shown by arrows. The terminals 18X and 18Y of the package 11 are connected to the external terminals 19X and 19Y, respectively, under the capacitor block 10 without being fitted into the grooves. The terminal 18D, the terminal 18E, and the terminal 18G, which is a power supply terminal for the integrated circuit, are also connected to the external terminal 19.
D, connected to external terminal 19E and external terminal 19G. The external terminals are indicated by circles in Figure 4,
As shown in Figure 1, it has an L-shaped horizontal part whose tip is bent downward, and the vertical part of the terminal of the package cage 11 is fitted into the groove 20 provided at the tip and connected by soldering. . Figure 2 shows the state in which the external terminals are connected to the terminals of the package 11, but in the end, the whole is sealed with resin to form a DIP, as shown by the dashed line, and only the external terminals are connected to the terminals. A structure that is exposed to the outside is desirable.
このように構成した混成回路を第5図と対応さ
せると、外部端子19Dは入力端子1、外部端子
19Eはアース端子E、外部端子19Gは電源端
子Vc、外部端子19Xと外部端子19Yは出力
端子2と出力端子3の夫々の役割をする。なお実
施例に用いたコイルL1,L2はドラム状のコア
に巻線を行い、両端の鍔に導体パターン17に直
接面接続するための電極を設けたいわゆるチツプ
タイプのコイルである。又終端抵抗R1、R2も
面接続用に形成されたものである。これらの小型
の回路素子は種々のものが公知であるが、特別に
形状を限定する必要はない。又実施例では混成回
路を外部の回路に接続するための外部端子を集積
回路の端子に接続したが、必要に応じてコンデン
サブロツクの側辺に外部端子を接続することもで
きる。集積回路の端子と外部端子の接続も2個の
金属端子を接続するための他の公知技術を用いて
もよい。このように混成回路を外部に引出すため
の外部端子の接続方法は本考案の範囲内で多くの
変形を伴う。さらに集積回路のパツケージはフラ
ツトパツケージ以外でもよい。 When the hybrid circuit configured in this way corresponds to Fig. 5, the external terminal 19D is the input terminal 1, the external terminal 19E is the ground terminal E, the external terminal 19G is the power supply terminal V c , and the external terminals 19X and 19Y are the output terminals. They serve as terminal 2 and output terminal 3, respectively. The coils L1 and L2 used in the embodiment are so-called chip-type coils in which wires are wound around a drum-shaped core, and electrodes for direct surface connection to the conductor pattern 17 are provided on flanges at both ends. Furthermore, the terminating resistors R1 and R2 are also formed for surface connection. Various types of these small circuit elements are known, but there is no need to limit the shape in particular. Further, in the embodiment, the external terminal for connecting the hybrid circuit to an external circuit is connected to the terminal of the integrated circuit, but if necessary, the external terminal can be connected to the side of the capacitor block. Connections between integrated circuit terminals and external terminals may also be made using other known techniques for connecting two metal terminals. As described above, the method of connecting the external terminals for leading out the hybrid circuit to the outside involves many modifications within the scope of the present invention. Furthermore, the package of the integrated circuit may be other than a flat package.
実施例と同様の技術思想によりコンデンサブロ
ツクにはLCフイルタ等の別の回路を構成し、集
積回路と組合せて種々の混成回路を構成し得るこ
とは明らかである。 It is clear that other circuits such as LC filters can be constructed in the capacitor block based on the same technical idea as in the embodiments, and various hybrid circuits can be constructed by combining with the integrated circuit.
以上述べたように本考案の混成回路はコンデン
サブロツクの主表面に固着する回路素子と内部の
コンデンサにより集積回路に接続する回路を構成
し、集積回路のパツケージと重ね合せるものであ
り、回路素子の位置を固定するための基板は不要
であるし、又コンデンサを基板に取付ける作業も
なくなる。従つて集積回路の外に回路を接続する
場合の組立工数を節約できるし、基板を使用しな
いことにより従来よりも安価な混成回路を容易に
得ることができる。
As described above, the hybrid circuit of the present invention consists of a circuit connected to an integrated circuit using a circuit element fixed to the main surface of a capacitor block and an internal capacitor, which is superimposed on the integrated circuit package, and the circuit element is superimposed on the integrated circuit package. There is no need for a board to fix the position, and there is no need to attach the capacitor to the board. Therefore, it is possible to save assembly man-hours when connecting circuits outside the integrated circuit, and by not using a substrate, it is possible to easily obtain a hybrid circuit that is cheaper than the conventional one.
第1図は本考案の混成回路の実施例を示す斜視
図、第2図は第1図の長さ方向からの正面図、第
3図はコンデンサブロツクの拡大横断面図、第4
図は実施例における接続の説明図、第5図は実施
例の回路図である。
1……入力端子、2,3……出力端子、VC…
…電源端子、E……アース端子、10……コンデ
ンサブロツク、11……フラツトパツケージ、1
2A,12B……電極、13A,13B,13C
……溝、14A,14B,14E……電極端子、
15……端子、16……主表面、17……導体パ
ターン、18A,18B,18C……端子、19
D,19E,19G,19X,19Y……外部端
子、20……溝。
FIG. 1 is a perspective view showing an embodiment of the hybrid circuit of the present invention, FIG. 2 is a front view from the longitudinal direction of FIG. 1, FIG. 3 is an enlarged cross-sectional view of a capacitor block, and FIG.
The figure is an explanatory diagram of connections in the embodiment, and FIG. 5 is a circuit diagram of the embodiment. 1...Input terminal, 2, 3...Output terminal, V C ...
...Power terminal, E...Earth terminal, 10...Capacitor block, 11...Flat package, 1
2A, 12B... Electrode, 13A, 13B, 13C
... Groove, 14A, 14B, 14E ... Electrode terminal,
15...Terminal, 16...Main surface, 17...Conductor pattern, 18A, 18B, 18C...Terminal, 19
D, 19E, 19G, 19X, 19Y...external terminal, 20...groove.
Claims (1)
り、夫々のコンデンサの電極の端を側辺に露呈さ
せてある板状のコンデンサブロツクと集積回路の
パツケージを重ね合せると共にコンデンサブロツ
クの主表面に回路素子を固着してあり、該回路素
子、前記コンデンサ、集積回路をコンデンサブロ
ツクの側辺に固着した集積回路の端子を用いて相
互に接続してあり、集積回路の端子に接続された
外部端子が全体の樹脂封止された部分の外側に露
呈していることを特徴とする混成回路。 A plate-shaped capacitor block, in which multiple independent capacitors are formed inside, and the ends of the electrodes of each capacitor are exposed on the sides, is stacked on an integrated circuit package, and the circuit elements are placed on the main surface of the capacitor block. The circuit element, the capacitor, and the integrated circuit are connected to each other using the terminals of the integrated circuit fixed to the sides of the capacitor block, and the external terminals connected to the terminals of the integrated circuit are connected to each other. A hybrid circuit characterized by being exposed outside the resin-sealed part of the circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985082821U JPH0447967Y2 (en) | 1985-05-31 | 1985-05-31 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985082821U JPH0447967Y2 (en) | 1985-05-31 | 1985-05-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61199057U JPS61199057U (en) | 1986-12-12 |
JPH0447967Y2 true JPH0447967Y2 (en) | 1992-11-12 |
Family
ID=30630882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985082821U Expired JPH0447967Y2 (en) | 1985-05-31 | 1985-05-31 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0447967Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6052637B2 (en) * | 1979-08-20 | 1985-11-20 | 三菱電機株式会社 | remote control device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6052637U (en) * | 1983-09-16 | 1985-04-13 | 日本特殊陶業株式会社 | Ceramic package for semiconductor IC with capacitor |
-
1985
- 1985-05-31 JP JP1985082821U patent/JPH0447967Y2/ja not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6052637B2 (en) * | 1979-08-20 | 1985-11-20 | 三菱電機株式会社 | remote control device |
Also Published As
Publication number | Publication date |
---|---|
JPS61199057U (en) | 1986-12-12 |
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