JPH044760U - - Google Patents
Info
- Publication number
- JPH044760U JPH044760U JP4415190U JP4415190U JPH044760U JP H044760 U JPH044760 U JP H044760U JP 4415190 U JP4415190 U JP 4415190U JP 4415190 U JP4415190 U JP 4415190U JP H044760 U JPH044760 U JP H044760U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- terminals
- package
- terminal
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案実施例の構成斜視図、第２図、
第３図は短絡バーの接続状態を表した第１図の正
面図、およびその内部結線図、第４図は本考案の
実施対象となる半導体装置の従来構成の斜視図、
第５図は第４図の内部結線図である。図において
、
１……パツケージケース、２……端子フレーム
、４……外部接続用端子、５，５ａ，５ｂ……バ
リア、６……短絡バー。
Fig. 1 is a perspective view of the configuration of the embodiment of the present invention; Fig. 2;
3 is a front view of FIG. 1 showing the connection state of the shorting bar, and its internal wiring diagram; FIG. 4 is a perspective view of the conventional configuration of a semiconductor device to which the present invention is applied;
FIG. 5 is an internal wiring diagram of FIG. 4. In the figure, 1...Package case, 2...Terminal frame, 4...External connection terminal, 5, 5a, 5b...Barrier, 6...Short-circuit bar.
Claims (1)
を組み込み、かつ各半導体デバイスより引出した
外部接続用の端子を同一平面に並べてパツケージ
上面に配置するとともに、各端子の間を隔離して
パツケージ上面にバリアを形成した電力用半導体
装置において、各半導体デバイスの端子を種類別
に分けた上で同種の端子同士を一列に配列すると
ともに、各端子を同種の端子列内に並ぶバリアよ
りも高い位置に設置したことを特徴とする電力用
半導体装置。 Multiple sets of semiconductor devices are built into one package, and the external connection terminals drawn out from each semiconductor device are arranged on the same plane on the top of the package, and a barrier is placed on the top of the package to isolate each terminal. In the formed power semiconductor device, the terminals of each semiconductor device are separated by type, and the terminals of the same type are arranged in a row, and each terminal is installed at a higher position than the barrier lined up in the row of terminals of the same type. A power semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4415190U JPH044760U (en) | 1990-04-25 | 1990-04-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4415190U JPH044760U (en) | 1990-04-25 | 1990-04-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH044760U true JPH044760U (en) | 1992-01-16 |
Family
ID=31557196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4415190U Pending JPH044760U (en) | 1990-04-25 | 1990-04-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH044760U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019031140A1 (en) * | 2017-08-10 | 2019-02-14 | Koa株式会社 | Current measurement device |
-
1990
- 1990-04-25 JP JP4415190U patent/JPH044760U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019031140A1 (en) * | 2017-08-10 | 2019-02-14 | Koa株式会社 | Current measurement device |
| JP2019035610A (en) * | 2017-08-10 | 2019-03-07 | Koa株式会社 | Current measurement device |
| CN111183361A (en) * | 2017-08-10 | 2020-05-19 | Koa株式会社 | Current measuring device |