JPH0447422A - Bank-book printer - Google Patents
Bank-book printerInfo
- Publication number
- JPH0447422A JPH0447422A JP2154957A JP15495790A JPH0447422A JP H0447422 A JPH0447422 A JP H0447422A JP 2154957 A JP2154957 A JP 2154957A JP 15495790 A JP15495790 A JP 15495790A JP H0447422 A JPH0447422 A JP H0447422A
- Authority
- JP
- Japan
- Prior art keywords
- communication
- cpu
- communication message
- circuit
- issue number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 claims abstract description 100
- 238000007639 printing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 239000013256 coordination polymer Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- Debugging And Monitoring (AREA)
- Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
本発明は通帳プリンタに関し、特に通帳プリンタの履歴
情報保存方式に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a passbook printer, and more particularly to a history information storage method for a passbook printer.
従来技術
従来、通帳プリンタにおいては、第４図に示すように、
図示せぬ上位装置との通信がＣＰＵ４で制御され、装置
内における通帳（図示せず）の搬送がＣＰｔＪ５で制御
され、通帳への印字がＣＰＵ６て行われていた場合、Ｃ
ＰＵ４とＣＰＵ５との間の通信状態の履歴、およびＣＰ
Ｕ５とＣＰＵ６との間の通信状態の履歴が夫々の上位側
でのみ、つまりＣＰＵ４とＣＰＵ５との間の通信状態の
履歴がＣＰＵ４て、ＣＰＵ５とＣＰＵ６との間の通信状
態の履歴がＣＰＵ５で保存されていた。Prior Art Conventionally, in a passbook printer, as shown in Fig. 4,
If communication with a host device (not shown) is controlled by the CPU 4, transport of a passbook (not shown) within the device is controlled by the CPtJ5, and printing on the passbook is performed by the CPU 6,
History of communication status between PU4 and CPU5, and CP
The history of the communication state between U5 and CPU6 is stored only on the respective upper-level sides, that is, the history of the communication state between CPU4 and CPU5 is stored in CPU4, and the history of the communication state between CPU5 and CPU6 is stored in CPU5. It had been.
このような従来の通帳プリンタでは、ＣＰＵ４とＣＰＵ
５との間、およびＣＰＵ５とＣＰＵ６との間の通信状態
の履歴が夫々の上位側でのみ保存されていたので、全て
のＣＰＵ４〜６の通信状態の経緯が不明確になるという
欠点がある。In such a conventional passbook printer, CPU4 and CPU
Since the history of the communication status between CPU 5 and CPU 5 and between CPU 5 and CPU 6 was saved only on the respective upper-level sides, there is a drawback that the history of the communication status of all CPUs 4 to 6 is unclear.
発明の目的
本発明は上記のような従来のものの欠点を除去すべくな
されたもので、全ＣＰＵの通信状態の経緯を明確にする
ことができる通帳プリンタの提供を目的とする。OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional printers as described above, and an object of the present invention is to provide a passbook printer that can clarify the history of the communication status of all CPUs.
発明の構成
本発明による通帳プリンタは、上位装置との通信と、通
帳の搬送と、前記通帳への印字とを夫々制御する複数の
中央処理装置を含む通帳プリンタであって、前記複数の
中央処理装置各々に設けられ、他の中央処理装置に送出
する通信電文に、該通信電文の発行順序を示す発行順序
情報を付与する付与手段と、前記通信電文と該通信電文
に付与された発行順序情報とを通信履歴として格納する
格納手段とを有することを特徴とする。Structure of the Invention A passbook printer according to the present invention is a passbook printer including a plurality of central processing units that respectively control communication with a host device, transportation of a passbook, and printing on the passbook, the plurality of central processing units an attaching means provided in each device for attaching issuance order information indicating the issuance order of the communication telegrams to the communication telegrams to be sent to other central processing units; and the above-mentioned communication telegrams and issuance order information given to the communication telegrams. and storage means for storing this as a communication history.
実施例
次に、本発明の一実施例について図面を参照して説明す
る。Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の構成を示すブロック図であ
る。図において、ＣＰＵＩにはＣＰＵ２からの通信電文
を解析する解析回路１１と、ＣＰＵ２への通信電文を発
行する通信電文発行回路１２と、ＣＰＵ２への通信電文
に発行番号を付与する発行番号付与回路１３と、全ＣＰ
Ｕ１〜３間で送受信された通信電文およびその発行番号
を格納する履歴情報格納回路１４と、ＣＰＵ２の履歴情
報格納回路２４に格納された履歴情報を読取って履歴情
報格納回路１４に書込む履歴情報読取回路１５とが設け
られている。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the CPU includes an analysis circuit 11 that analyzes a communication message from the CPU 2, a communication message issuing circuit 12 that issues a communication message to the CPU 2, and an issue number assignment circuit 13 that assigns an issue number to the communication message to the CPU 2. and all CP
History information that reads the history information stored in the history information storage circuit 14 that stores the communication messages sent and received between U1 to U3 and their issuance numbers, and the history information storage circuit 24 of the CPU 2 and writes it into the history information storage circuit 14. A reading circuit 15 is provided.
また、ＣＰＵ２にはＣＰＵＩ、３からの通信電文を解析
する解析回路２１と、ＣＰＵＩ、３への通信電文を発行
する通信電文発行回路２２と、ＣＰＵＩ、３への通信電
文に発行番号を付与する発行番号付与回路２３と、ＣＰ
Ｕ３との間で送受信された通信電文およびその発行番号
を格納する履歴情報格納回路２４とが設けられている。The CPU 2 also includes an analysis circuit 21 that analyzes the communication message from the CPU 3, a communication message issuing circuit 22 that issues the communication message to the CPU 3, and an issue number that is assigned to the communication message sent to the CPU 3. Issue number assigning circuit 23 and CP
A history information storage circuit 24 is provided to store communication telegrams sent and received with U3 and their issuance numbers.
さらに、ＣＰＵ３にはＣＰＵ２からの通信電文を解析す
る解析回路３１と、ＣＰＵ２への通信電文を発行する通
信電文発行回路３２と、ＣＰＵ２への通信電文に発行番
号を付与する発行番号付与回路３３とが設けられている
。Furthermore, the CPU 3 includes an analysis circuit 31 that analyzes the communication message from the CPU 2, a communication message issuing circuit 32 that issues the communication message to the CPU 2, and an issue number assigning circuit 33 that assigns an issue number to the communication message to the CPU 2. is provided.
第２図は第１図のＣＰＵ１〜３間の通信状態を示す図で
あり、第３図は第１図のＣＰＵＩの履歴情報格納回路１
４に格納された履歴情報を示す図である。これら第１図
〜第３図を°用いて本発明の一実施例の動作について説
明する。2 is a diagram showing the communication state between the CPUs 1 to 3 in FIG. 1, and FIG. 3 is a diagram showing the history information storage circuit 1 of the CPUI in FIG.
4 is a diagram showing history information stored in FIG. The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.
ＣＰＵＩの通信電文発行回路１２でＣＰＵ２への通信電
文「ア」が発行され、発行番号付与回路１３でその通信
電文「ア」に発行番号「１」か付与されると、これら通
信電文「ア」および発行番号「１」がＣＰＵ２に送信さ
れるとともに、履歴情報格納回路１４に格納される。When the communication message issuing circuit 12 of the CPUI issues a communication message "A" to the CPU 2, and the issue number assigning circuit 13 assigns an issue number "1" to the communication message "A", these communication messages "A" and the issue number "1" are transmitted to the CPU 2 and stored in the history information storage circuit 14.
ＣＰＵ２ではＣＰＵＩからの通信電文「ア」か解析回路
２１で解析され、その結果ＣＰＵＩからの通信電文「ア
」の内容（たとえば通帳の搬送命令など）が実行され、
その後に通信電文発行回路２２でＣＰＵ３への通信電文
「イ」が発行されると、発行番号付与回路２３でその通
信電文「イ」に発行番号ｒ１−’Ｊが付与され、これら
通信電文「イ」および発行番号ｒｌ−ＩＪがＣＰＵ３に
送信されるとともに、履歴情報格納回路２４に格納され
る。In the CPU 2, the communication message "A" from the CPUI is analyzed by the analysis circuit 21, and as a result, the contents of the communication message "A" from the CPUI (for example, an instruction to transport a passbook, etc.) are executed.
After that, when the communication message issuing circuit 22 issues the communication message "I" to the CPU 3, the issue number assigning circuit 23 assigns an issue number r1-'J to the communication message "I". " and the issue number rl-IJ are transmitted to the CPU 3 and stored in the history information storage circuit 24.
ＣＰＵ３ではＣＰＵ２からの通信電文「イ」が解析回路
３１て解析され、その結果ＣＰＵ２からの通信電文「イ
」の内容（たとえば通帳への印字命令など）が実行され
、その終了状態が通信電文「つ」として通信電文発行回
路３２て発行されると、発行番号付与回路３３でその通
信電文「つ」に発行番号ｒｌ −ＩＪが付与され、これ
ら通信電文「つ」および発行番号ｒｌ−ＩＪがＣＰＵ２
に返信される。In the CPU 3, the communication message "I" from the CPU 2 is analyzed by the analysis circuit 31, and as a result, the contents of the communication message "I" from the CPU 2 (for example, an instruction to print on a passbook, etc.) are executed, and the end state is the communication message "I". When the communication message issuing circuit 32 issues the communication message ``tsu'', the issue number rl-IJ is assigned to the communication message ``tsu'' in the issue number assigning circuit 33, and these communication messages ``tsu'' and the issue number rl-IJ are sent to the CPU 2.
will be replied to.
ＣＰＵ２はＣＰＵ３から通信電文「つ」が返信されてく
ると、その通信電文「つ」が解析回路２１で解析され、
その結果ＣＰＵ２からの通信電文「イ」の内容の実行が
終了したと判断すると、通信電文発行回路２２で通信電
文「工」が発行され、発行番号付与回路２３てその通信
電文「工」に発行番号「１」か付与され、これら通信電
文「工」および発行番号「１」がＣＰＵＩに返信される
。When the CPU 2 receives the communication message "TS" as a reply from the CPU 3, the communication message "TS" is analyzed by the analysis circuit 21.
As a result, when it is determined that the execution of the contents of the communication message "A" from the CPU 2 has been completed, the communication message issuing circuit 22 issues the communication message "Eng", and the issuing number assigning circuit 23 issues the communication message "Eng". The number ``1'' is assigned, and the communication message ``TECH'' and the issue number ``1'' are returned to the CPUI.
このとき、ＣＰＵ２ではＣＰＵ３からの通信電文「つ」
および発行番号ｒｌ −ＩＪが履歴情報格納回路２４に
格納される。At this time, CPU2 receives the communication message "tsu" from CPU3.
and the issue number rl-IJ are stored in the history information storage circuit 24.
ＣＰＵＩはＣＰＵ２から通信電文「工」か返信されてく
ると、その通信電文「工」が解析回路２１で解析され、
その結果通信電文「ア」の内容の実行が終了したと判断
すると、通信電文「工」および発行番号「１」が履歴情
報格納回路１４に格納されるとともに、履歴情報読取回
路１５によりＣＰＵ２の履歴情報格納回路２４から通信
電文「イ」および発行番号ｒｌ −ＩＪと通信電文「つ
」および発行番号ｒｌ−ＩＪとか読出されて履歴情報格
納回路１４に格納される。When the CPU 2 sends back the message ``tech'', the CPU 2 analyzes the message ``tech'' in the analysis circuit 21.
As a result, when it is determined that the execution of the contents of the communication message "A" has been completed, the communication message "ENG" and the issue number "1" are stored in the history information storage circuit 14, and the history information reading circuit 15 stores the history of the CPU 2. The communication message "i", the issue number rl-IJ, the communication message "tsu" and the issue number rl-IJ are read out from the information storage circuit 24 and stored in the history information storage circuit 14.
よって、履歴情報格納回路１４には通信電文「ア」およ
び発行番号「１」、通信電文「工」および発行番号「１
」、通信電文「イ」および発行番号ｒｌ−ＩＪ、通信電
文「つ」および発行番号ｒｌ −ＩＪが夫々格納される
。Therefore, the history information storage circuit 14 stores the communication message "A" and the issue number "1", the communication message "Eng" and the issue number "1", and the communication message "A" and the issue number "1".
", the communication message "i" and the issue number rl-IJ, and the communication message "tsu" and the issue number rl-IJ are stored, respectively.
すなわち、ＣＰＵＩからＣＰＵ２へ送信される通信電文
「ア」およびＣＰＵ２からＣＰＵＩへ返信される通信電
文「工」に夫々発行番号「１」が付与され、ＣＰＵ２か
らＣＰＵ３へ送信される通信電文「イ」およびＣＰＵ３
からＣＰＵ２へ返信される通信電文「つ」に夫々発行番
号ｒｌ −ＩＪが付与されるので、全ＣＰＵＩ〜３の間
の通信状態の経緯を明確に知ることができる。In other words, the issue number "1" is assigned to each of the communication message "A" sent from the CPUI to the CPU2 and the communication message "Technology" sent back from the CPU2 to the CPUI, and the communication message "I" sent from the CPU2 to the CPU3 is assigned the issue number "1". and CPU3
Since the issue number rl-IJ is assigned to each communication telegram "tsu" sent back from the CPU 2 to the CPU 2, it is possible to clearly know the history of the communication status among all the CPUs 3.
このように、ＣＰＵＩ〜３の間で送受信される通信電文
に、該通信電文の発行順序を示す発行番号を付与し、そ
の通信電文と発行番号とを通信履歴として格納するよう
にすることによって、全ＣＰＵＩ〜３の通信状態の経緯
を明確にすることができる。In this way, by assigning an issue number indicating the issuing order of the communication messages to the communication messages sent and received between the CPUI and 3, and storing the communication messages and issue numbers as a communication history, It is possible to clarify the history of the communication status of all CPUI-3.
尚、本発明の一実施例ではＣＰＵＩとＣＰＵ２との間で
送受信される通信電文「ア」、「工」に発行番号「１」
を付与し、ＣＰＵ２とＣＰＵ３との間で送受信される通
信電文「イ」、「つ」に発行番号ｒｌ−ＩＪを付与して
いるが、全ＣＰＵＩ〜３の間で送受信される通信電文「
ア」〜「工」の発行順に発行番号（たとえば「１」〜「
４」）を付与するようにしてもよく、これに限定されな
い。In addition, in one embodiment of the present invention, the issue number "1" is assigned to the communication messages "A" and "TE" sent and received between the CPUI and the CPU2.
, and issuance numbers rl-IJ are assigned to the communication messages "i" and "tsu" sent and received between CPU2 and CPU3, but the communication telegrams "i" and "tsu" sent and received between all CPUs
Issue numbers in the order of issuance from ``A'' to ``ENG'' (for example, ``1'' to ``ENG''
4"), but is not limited to this.
発明の詳細
な説明したように本発明によれば、複数のＣＰＵの間で
送受信される通信電文に゛、該通信電文の発行順序を示
す発行順序情報を付与し、それら通信電文と発行順序情
報とを通信履歴として格納するようにすることによって
、全ＣＰＵの通信状態の経緯を明確にすることかできる
という効果がある。As described in detail, according to the present invention, issuance order information indicating the issuance order of the communication messages is added to the communication messages transmitted and received between a plurality of CPUs, and the issuance order information is attached to the communication messages and the issuance order information. By storing the information as a communication history, there is an effect that the history of communication status of all CPUs can be clarified.
第１図は本発明の一実施例の構成を示すブロック図、第
２図は第１図のＣＰＵ間の通信状態を示す図、第３図は
第１図のＣＰＵＩの履歴情報格納回路に格納された履歴
情報を示す図、第４図は従来例の構成を示す図である。
主要部分の符号の説明
１〜３・・・・・・ＣＰＵ
１１．２１．３１・・・・・・解析回路１２．２２．３
２・・・・・通信電文発行回路１３．２３．３３・・・
・・・発行番号付与回路１４．２４・・・・・・履歴情
報格納回路１５・・・・・・履歴情報読取回路FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the communication state between the CPUs shown in FIG. 1, and FIG. FIG. 4 is a diagram showing the configuration of a conventional example. Explanation of symbols of main parts 1 to 3...CPU 11.21.31...Analysis circuit 12.22.3
2...Communication message issuing circuit 13.23.33...
...Issuance number assigning circuit 14.24...History information storage circuit 15...History information reading circuit
Claims (1)
の印字とを夫々制御する複数の中央処理装置を含む通帳
プリンタであって、前記複数の中央処理装置各々に設け
られ、他の中央処理装置に送出する通信電文に、該通信
電文の発行順序を示す発行順序情報を付与する付与手段
と、前記通信電文と該通信電文に付与された発行順序情
報とを通信履歴として格納する格納手段とを有すること
を特徴とする通帳プリンタ。(1) A passbook printer including a plurality of central processing units that respectively control communication with a higher-level device, transport of a passbook, and printing on the passbook, the printer being provided in each of the plurality of central processing units; adding means for adding issuance order information indicating the issuance order of the communication messages to the communication messages to be sent to the central processing unit of the communication message; and storing the communication messages and the issuance order information attached to the communication messages as a communication history. A passbook printer comprising a storage means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2154957A JPH0447422A (en) | 1990-06-13 | 1990-06-13 | Bank-book printer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2154957A JPH0447422A (en) | 1990-06-13 | 1990-06-13 | Bank-book printer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0447422A true JPH0447422A (en) | 1992-02-17 |
Family
ID=15595604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2154957A Pending JPH0447422A (en) | 1990-06-13 | 1990-06-13 | Bank-book printer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0447422A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8198086B2 (en) | 2007-03-30 | 2012-06-12 | Kyushu University, National University Corporation | Method for production of three-dimensional structure of cells |
-
1990
- 1990-06-13 JP JP2154957A patent/JPH0447422A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8198086B2 (en) | 2007-03-30 | 2012-06-12 | Kyushu University, National University Corporation | Method for production of three-dimensional structure of cells |
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