JPH0445865B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a signal processing device that processes data in a pipeline manner.

(Prior Art) Conventionally, signal processing devices constituting digital signal processing systems such as SONA are required to realize high-speed pipeline processing while generating complex data addresses specific to signal processing. Typically, the signal processing device includes a program memory that stores an operating program, a data memory that stores processing data, an address generator that generates an address for accessing the data memory, and arithmetic processing of the data on the data memory. It is composed of arithmetic processing units that perform data processing, and realizes data pipeline processing.

On the other hand, a typical example of processing in the system is a beam former that realizes phased array beam formation. This beam former is a process of forming a beam by adding a delay amount specific to each sensor to the outputs of a large number of sensors in a phased array. In addition, this beamformer can be realized by using a circular address to access the data memory in the signal processing device, controlling the write address and read address, and reproducing the function of a shift register on the data memory. The amount can be given as a displacement of the read address relative to the write address.

However, the amount of delay and the displacement of the address determined from the amount of delay are values unique to each sensor, and are difficult to obtain by normal calculation. For this reason, it was necessary to provide a dedicated address displacement table corresponding to each sensor, that is, an address table. In addition, conventional methods for creating such an address table include providing a dedicated address table memory and an address counter for the address table memory, but these methods are extremely uneconomical due to the hardware configuration of the signal processing device. It was missing.

(Object of the Invention) The present invention has been made to solve these problems, and by storing the address table in the program memory, the dedicated address table can be stored without impairing the conventional pipeline processing function. Address table memory and address counters have been removed to reduce the amount of hardware required, eliminating the need for dedicated hardware operations during program development and maintenance, and creating a versatile system that can be used as part of normal program operations. A data processing device is provided.

(Structure of the Invention) The present invention provides a signal processing device that includes a program memory that stores a control program and a data memory that stores processed data, and that requires an address table to generate an address for the data memory. An address generating means and a plurality of registers are provided, and the address generating means includes a modulo register and a current address counter, and a macro instruction consisting of an instruction code, an address of the address table, etc. store the address table,
The arithmetic processor decodes the macro instruction, sets the address table and addresses in the macro instruction in an address counter provided in the arithmetic processor, and then sequentially updates the set addresses by +1. The address table in the program memory is read out and output as the first address, and the address generating means further performs a modulo calculation etc. from the first address and the values of the modulo register and current address counter, and then outputs the address table in the data memory as the address of the data memory. A second address is generated, and the registers are configured to generate a second address when reading the first address and when generating the second address.
The first address and the second address are temporarily stored and held, respectively, and the address counter is sequentially updated, the first address is read from the program memory and temporarily stored, and the second address is generated by the address generation means. This data processing device is characterized in that it continuously generates data memory addresses by executing the operations of generating and temporarily storing them in a pipeline manner in parallel every machine cycle.

Embodiments of the present invention will be described in detail below with reference to the drawings.

(Embodiment) FIG. 1 is a block diagram showing a data processing device as an embodiment of the present invention. In the figure, 10 is an arithmetic processor, 20 is a program memory, 30 is a data memory, 40 is an address generator, 41 is an input register, 42 is an address generation means, 43 is an output register, 50 is a bidirectional bus switch, 60 is a is the data bus. 70 is a PM address for accessing the program memory, and is supplied from the arithmetic processor 10 to the program memory 20.
80 is a program memory 20 and an input register 41
A bus 90 connected to the bus switch 50 and the bus switch 50 is a DM address for accessing the data memory 30, and is supplied to the data memory 30 from the output register 43. The data bus 60 includes an arithmetic processor 10, a data memory 30, and an address generation means 42.
and the bus switch 50. The output of the input register 41 is supplied to an address generating means 42, and the output of the address generating means 42 is supplied to an output register 43.

Next, the present invention will be explained using a beamformer as an example. FIG. 2 shows an example in which the input data of the beamformer, that is, the sensor output of the K channel sampled at the sampling period Δt, is stored in the data memory by cycling from address 0 to address KN-1 at intervals of Δt. X _k,-i (i = 0, 1, ..., N-1) is the sensor output of channel k at time -i Δt, that is, X _k,0 is the data at the current time, and X _k,-i means data past the current time by i·Δt. The write address for storing input data to the data memory will be explained below. Assuming that the write address IA k of data X _k,0 at the current time is IA _k , IA _k is expressed by the following equation.

IA _k = k.N ,
Convert the value of J to a cyclic address from 0 to N-1. N is the cyclic period, and is a power of 2 expressed as N=2 ^M (M is an integer). J is the sampling period Δt
sensor output data sampled at IA _k for every Δt
This is the current address that is updated by -1 every time the address is stored. As a result, IA _k always indicates the address of the current data, that is, the latest data.

The above operation will be explained with reference to FIG. The sensor output of the K channel is sampled and transmitted from an input device (not shown) via a data bus 60 at intervals of Δt.
The data is written to the data memory 30. The address of the data memory 30 is generated by the address generating means 42 and supplied via the output register 43 by the DM address 90. The cyclic period N is N=
It is assumed that the integer M given by ^2M is stored in advance in a modulo register (not shown) in the address generating means 42 from the arithmetic processor 10 via the data bus 60. Further, the current address J is the content of a current address counter (not shown) in the address generation means 42, and is initialized to, for example, 0 at the time of initial setting, and then immediately before writing the data of the K channel to the data memory 30. -1 update.

Next, calculation of a beamformer used as an example of the present invention will be explained. FIG. 3 shows the relationship between instructions on the program memory 20 and the address table.

The instructions shown in the figure are 2 at address a and address a+1.
This is a macro instruction consisting of words, and this instruction is used as a beamformer instruction. The first word of this beamformer command is composed of an instruction code and the number of sensor channels K, and the second word indicates the start address FA of the address table. Therefore, the order:
An address table of K consecutive words starting from address FA is required.

Each address table is composed of a channel number k and an address displacement D _k corresponding to the delay amount of channel k. The bit width of the address table is P
Then, the upper PM bits are assigned to the channel number k, and the lower M bits are assigned to the address change D _k , resulting in k.2 ^M + D _K , or k.N + D _k .
It is structured in the form of However, N and M are the same as the above values represented by N= ^2M .

Next, the operation of the beamformer command will be explained with reference to FIG. First, a PM address 70 within the arithmetic processor 10 is generated. The contents of an address counter (not shown) are read from the program memory 20 as an instruction at address a shown in FIG. The instruction at address a read from the program memory 20 is sent to the bus 80, bus switch 50 and data bus 60.
The signal is input to the arithmetic processor 10 via , and is decoded as a beamformer command with K channels.

Next, the address counter is updated by +1 to address a+1, and the leading address FA of the address table, which is the instruction at address a+1 shown in FIG. . The address counter is updated by +1 again and temporarily saved in the stack as address a+2, and becomes the first address of the address table.
FA is stored in the address counter. next,
The address counter increases by +1 every machine cycle.
PM the updated value from FA to FA+K-1
Address table k・N+D _k (k=0 to K-1) sent via address 70 and stored at addresses FA to FA+K-1 in program memory 20
and input register 41 via bus 80.
Store in. The address table is outputted from the input register 41 with a delay of one machine cycle and supplied to the address generation means 42.

The address generating means 42 uses the modulo register to divide the input P-bit address into upper PM bits (corresponding to the above-mentioned k and N) and lower M bits (corresponding to the above-mentioned D _k ). , the current address J is added to the lower M bits, and then combined with the upper PM bits again to generate a read address for the data memory 30.

WA _k = kN + (J + D _k ) mod N ... (2) The read address WA _k generated by the address generating means 42 is stored in the output register 43, and is outputted to the output register 43 with a delay of one machine cycle.
The data memory 30 is accessed via the DM address 90. The contents of the data memory 30 at the read address WA _k are as follows:
In Fig. 2, X _k,-i (i=D _k ) is
_Dk ·Δt is past data, meaning delayed data of D _k ·Δt. X _k,-Dk (k=0 to K-1) read from the data memory 30 is the data bus 6
The signal is input to the arithmetic processor 10 via 0, and the arithmetic operation is performed to obtain a beamformer result.

Finally, the value (address) a+2 temporarily saved on the stack is stored in the address counter,
Next instruction (two-word instruction at address a+2 and address a+3)
Move on to execution.

With the above configuration, a read address can be generated every machine cycle. Further, the configuration is such that the generation of the address for reading the address table in the program memory can be done by simply incrementing the address counter. Therefore, addresses can be generated in a pipeline manner, and the program memory and data memory can be processed independently and in parallel.

(Effects of the Invention) By storing the address table on the program memory, the present invention eliminates the need for a dedicated address table memory and address counter.
It is possible to reduce hardware and make program management easier. By supplying the address table to an address generator, complex address generation depending on the array structure of a sonar or the like can be easily performed. By providing an input register and an output register at the input and output of the address generating means of the address generator, there is an advantage that from reading the address table to generating a DM address and calculating processing data can be executed in a pipeline manner.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data processing device that is an embodiment of the present invention, FIG. 2 is a diagram showing an example of a data arrangement on a data memory, and FIG. 3 is a diagram showing the relationship between instructions on a program memory and an address table. FIG. 10... Arithmetic processor, 20... Program memory, 30... Data memory, 40... Address generator, 41... Input register, 42... Address generation means, 43... Output register, 50... Bus switch, 60...Data bus, 70...PM address, 80...Bus, 90...DM address.

Claims (1)

[Claims] 1. A signal processing device comprising a program memory for storing a control program and a data memory for storing processed data, and requiring an address table for generating addresses of the data memory, comprising: an arithmetic processor and an address generator; and a plurality of registers, and the address generation means includes a modulo register and a current address counter, and the address table includes a macro instruction including an instruction code, an address of the address table, etc. on the program memory. and store the
The arithmetic processor decodes the macro instruction, sets the address of the address table in the macro instruction in an address counter provided in the arithmetic processor, and then sequentially updates the set address by +1. The address table in the program memory is read out and output as a first address, and the address generating means further performs a modulo operation etc. from the first address and the values of the modulo register and current address counter, and then outputs the address table in the data memory as the address of the data memory. generating a second address, and causing the plurality of registers to temporarily store and hold the first address and the second address, respectively, when reading the first address and generating the second address; The updating operation of the address counter, the operation of reading the first address from the program memory and temporarily storing it, and the operation of generating the second address by the address generation means and temporarily storing it are performed in parallel every machine cycle. A data processing device characterized in that data memory addresses are continuously generated by pipeline-like execution.