JPH0445250Y2 - - Google Patents
Info
- Publication number
- JPH0445250Y2 JPH0445250Y2 JP16524086U JP16524086U JPH0445250Y2 JP H0445250 Y2 JPH0445250 Y2 JP H0445250Y2 JP 16524086 U JP16524086 U JP 16524086U JP 16524086 U JP16524086 U JP 16524086U JP H0445250 Y2 JPH0445250 Y2 JP H0445250Y2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- metal
- metal casing
- metal plate
- thermal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 57
- 229910052751 metal Inorganic materials 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 37
- 239000000919 ceramic Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000001816 cooling Methods 0.000 claims description 18
- 239000003507 refrigerant Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- SNAAJJQQZSMGQD-UHFFFAOYSA-N aluminum magnesium Chemical compound [Mg].[Al] SNAAJJQQZSMGQD-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 239000002241 glass-ceramic Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Description
【考案の詳細な説明】
〔概要〕
半導体チツプを装着したセラミツク基板と該基
板を覆つて設けられる金属筐体との間に、熱膨張
係数の差や締め付けの際に発生する応力を緩和す
る方法として、セラミツク基板を熱膨張係数の近
似した金属を介して超弾性を示す金属板に半田付
けし、Ｏリングを介して金属筐体と気密封止する
半導体装置の冷却構造。[Detailed description of the invention] [Summary] A method for alleviating the difference in coefficient of thermal expansion and stress generated during tightening between a ceramic substrate mounted with a semiconductor chip and a metal casing provided to cover the substrate. A cooling structure for a semiconductor device in which a ceramic substrate is soldered to a metal plate exhibiting superelasticity via a metal with a similar coefficient of thermal expansion, and hermetically sealed with a metal casing via an O-ring.
本考案は冷媒を使用して冷却する半導体装置の
冷却構造に関する。
The present invention relates to a cooling structure for a semiconductor device that uses a refrigerant to cool the device.
情報処理装置の処理能力を向上する方法として
多数の半導体素子から構成されている半導体チツ
プは単位素子の小形化と共に構成素子数の増大が
行われている。 2. Description of the Related Art As a method of improving the processing capacity of information processing devices, semiconductor chips, which are composed of a large number of semiconductor elements, are being made smaller in size and the number of constituent elements is increased.
すなわち、単位素子を形成する電極寸法や導体
パターン幅は極度に縮小されており、一方素子数
は増大してLSIやVLSIが実用化されている。 That is, the electrode dimensions and conductor pattern widths that form unit elements have been extremely reduced, while the number of elements has increased, and LSI and VLSI have been put into practical use.
また、プリント配線基板への実装方法も改良さ
れ、従来は半導体チツプ毎にハーメチツクシール
パツケージに格納してあり、これを配線基板に搭
載していたが、今後の形態としてはパツシベーシ
ヨン技術の進歩により、複数のLSIチツプをセラ
ミツクなどの回路基板に装着してLSIモジユール
を作り、これを取替え単位として配線基板に装着
する方法が採られている。 In addition, the mounting method on printed wiring boards has also been improved. Previously, each semiconductor chip was housed in a hermetically sealed package and mounted on the wiring board, but the future format will be based on advances in packaging technology. Therefore, a method has been adopted in which multiple LSI chips are mounted on a circuit board made of ceramic or the like to create an LSI module, which is then mounted on a wiring board as a replacement unit.
一方、このように単位素子の小形化と高密度化
が進むに従つて、半導体チツプの発熱量も膨大と
なり、従来の空冷方法では素子の温度を最高使用
温度範囲内に保持することは不可能になつた。 On the other hand, as unit elements become smaller and more dense, the amount of heat generated by semiconductor chips also increases, making it impossible to maintain the element temperature within the maximum operating temperature range using conventional air cooling methods. It became.
すなわち、今までLSIチツプの発熱量は最高で
も４ワツト程度であつたが、VLSIにおいては10
ワツト程度に達しようとしている。 In other words, up until now, the maximum amount of heat generated by an LSI chip was about 4 watts, but in VLSI, the amount of heat generated is about 10 watts.
It is about to reach the level of Watsuto.
以上のことから、半導体チツプの冷却方法は従
来の空冷や強制空冷に代わつて冷媒を使用する冷
却方法が必要となつている。 In view of the above, there is a need for a method of cooling semiconductor chips that uses a refrigerant instead of conventional air cooling or forced air cooling.
〔従来の技術〕
冷媒を用いた半導体チツプの冷却方法について
は現在は研究或いは試験段階であつて、冷却構造
としては未だ確立された技術は存在しない。[Prior Art] Methods for cooling semiconductor chips using refrigerants are currently in the research or testing stage, and there is no established technology for cooling structures yet.
第３図は多数の半導体チツプを装着してなる半
導体装置の従来の冷却構造であつて、同図Ａは断
面図、また同図Ｂは平面図である。 FIG. 3 shows a conventional cooling structure for a semiconductor device equipped with a large number of semiconductor chips, in which FIG. 3A is a sectional view and FIG. 3B is a plan view.
すなわち、LSIやVLSIなどの半導体チツプ１
は多層配線が施されているセラミツク基板２の表
面に装着されており、セラミツク基板２の裏面に
設けられている多数のコンタクトホールにリード
端子３が融着されて半導体チツプ１の電子回路が
取り出されている。 In other words, semiconductor chips such as LSI and VLSI1
is mounted on the surface of a ceramic substrate 2 on which multilayer wiring is applied, and lead terminals 3 are fused to a number of contact holes provided on the back surface of the ceramic substrate 2, and the electronic circuit of the semiconductor chip 1 is taken out. It is.
一方、放熱用のフイン４を備えた上部金属筐体
５と下部金属筐体６とはＯリング７を用いてネジ
８で締め付けるよう形成されている。 On the other hand, an upper metal casing 5 and a lower metal casing 6 having heat dissipation fins 4 are formed so as to be tightened with screws 8 using O-rings 7.
ここで、下部金属筐体６の中央部はセラミツク
基板２の装着可能なマージン部を残して窓開けさ
れており、このマージン部にセラミツク基板２が
半田付けされる構造をとつている。 Here, a window is opened in the center of the lower metal casing 6, leaving a margin where the ceramic substrate 2 can be attached, and the ceramic substrate 2 is soldered to this margin.
そして、上部金属筐体５の中には各種のフルオ
ロカーボンや液体窒素（N2）、またヘリウム
（He）ガスなどの冷媒９が封入されるか或いは循
環する構造が考えられている。 A structure in which a refrigerant 9 such as various fluorocarbons, liquid nitrogen (N2), or helium (He) gas is sealed or circulated in the upper metal casing 5 has been considered.
然し、かかる冷却構造をとる半導体装置を動作
させて評価テストを行つたところ、次のような原
因で下部金属筐体６とセラミツク基板２との接合
部で気密漏れが起き易いことが判つた。 However, when a semiconductor device having such a cooling structure was operated and evaluated, it was found that airtight leakage easily occurs at the joint between the lower metal casing 6 and the ceramic substrate 2 due to the following reasons.
セラミツク基板２と下部金属筐体６との間で
熱膨張の差に起因して発生する応力。 Stress generated due to the difference in thermal expansion between the ceramic substrate 2 and the lower metal casing 6.
冷媒を封止してある場合、電力印加の際に冷
媒の温度上昇により生ずる内圧の上昇。 If the refrigerant is sealed, an increase in internal pressure caused by the temperature rise of the refrigerant when power is applied.
ネジ８の締付けが均一に行われないことによ
る起こる応力。 Stress caused by uneven tightening of the screws 8.
これらのことから、セラミツク基板２と下部金
属筐体６とを直接に半田付けする構造は適当でな
いことが判つた。 From these facts, it has been found that a structure in which the ceramic substrate 2 and the lower metal casing 6 are directly soldered is not appropriate.
以上記したように多数の半導体チツプを搭載し
たセラミツク基板を金属筐体に装着し、その中に
冷媒を封入して冷却する冷却構造において、セラ
ミツク基板を直接に金属筐体に半田付けすると接
合部での破壊が起きやすく、気密漏れを生じ易い
ことが問題である。
As described above, in a cooling structure in which a ceramic substrate mounted with a large number of semiconductor chips is mounted on a metal casing and cooled by sealing a refrigerant therein, if the ceramic substrate is directly soldered to the metal casing, the joints The problem is that it is easy to break down and cause airtight leaks.
〔問題点を解決するための手段〕
上記の問題は垂直方向に配置した超弾性金属板
を挟んで上下の対称位置に前記セラミツク基板と
熱膨張係数の近似した金属板を熔接した金属部材
があり、該金属部材の一端に前記セラミツク基板
を半田付けすると共に、他端をボルト締めにより
前記上部金属筐体と固定する下部金属筐体部にＯ
リングを用いて気密封止する構造をとる半導体装
置の冷却構造により解決することができる。[Means for solving the problem] The above problem is solved by the fact that there is a metal member in which a metal plate having a thermal expansion coefficient similar to the ceramic substrate is welded to the ceramic substrate at a vertically symmetrical position with a superelastic metal plate placed vertically in between. , the ceramic substrate is soldered to one end of the metal member, and the other end is fixed to the upper metal casing by bolting.
This problem can be solved by a cooling structure for a semiconductor device that uses a ring for airtight sealing.
本考案はセラミツク基板を直接に下部金属筐体
に半田付けする構造を改め、セラミツク基板と熱
膨張係数の近似した金属を用いて半田付けすると
共に、中間に超弾性をもつ金属を介在させること
によつて、側面と表面などあらゆる方向から加わ
る歪を総て吸収するようにしたものである。
The present invention has changed the structure in which the ceramic substrate is directly soldered to the lower metal casing, and is now soldered using a metal with a thermal expansion coefficient similar to that of the ceramic substrate, and a superelastic metal is interposed in between. Therefore, it is designed to absorb all the strain applied from all directions, including the sides and the surface.
ここで、セラミツクス基板としてはガラスセラ
ミツクス多層基板、アルミナ多層基板、ガラス入
りイミド多層基板などが用いられており、この熱
膨張係数はそれぞれ4.4×10-6／℃，8.6×10-6／
℃，13×10-6／℃である。 Here, as the ceramic substrate, a glass ceramic multilayer substrate, an alumina multilayer substrate, a glass-filled imide multilayer substrate, etc. are used, and their thermal expansion coefficients are 4.4×10 -6 /°C and 8.6×10 -6 /°C, respectively.
℃, 13×10 -6 /℃.
ここで、微細パターンを含む多層基板を形成す
るには焼成温度が900℃以下ですむガラスセラミ
ツク基板が最も適し、一般に用いられている。 Here, in order to form a multilayer substrate including a fine pattern, a glass ceramic substrate, which requires a firing temperature of 900° C. or lower, is most suitable and is generally used.
一方、金属筐体の構成材料としてはアルミニウ
ム・マグネシウム（Al・Mg）合金などが一般的
に用いられており、JIS Ａ 5052（Al・Mg合金）
の熱膨張係数は21×10-6／℃である。 On the other hand, aluminum-magnesium (Al-Mg) alloys are commonly used as constituent materials for metal casings, and JIS A 5052 (Al-Mg alloys) are commonly used.
The coefficient of thermal expansion of is 21×10 -6 /°C.
本考案はこのように約一桁違う熱膨張係数の接
合に原因する応力を緩和あるいは吸収する方法と
して熱膨張係数がセラミツク基板に近似している
金属板を用い、また超弾性金属板を用いて伸長と
収縮により発生する応力を吸収するようにした。 The present invention uses a metal plate with a thermal expansion coefficient similar to that of a ceramic substrate and a superelastic metal plate as a method to alleviate or absorb the stress caused by bonding with thermal expansion coefficients that differ by about one order of magnitude. It is designed to absorb stress caused by expansion and contraction.
第２図は本考案に係る半導体冷却構造の断面図
で、第１図は部分拡大断面図である。 FIG. 2 is a sectional view of the semiconductor cooling structure according to the present invention, and FIG. 1 is a partially enlarged sectional view.
すなわち、垂直方向に配置した超弾性金属板１
０を挟んで上下対称位置に熱膨張係数がセラミツ
ク基板２と近似する金属板１１を熔接したものを
準備しておき、この一端にセラミツク基板２を鑞
付けなどの方法で接合し、また他端は下部金属筐
体６の上に置き、Ｏリング７を配し、従来と同様
にネジ８を用いて上部金属筐体５と下部金属筐体
とを気密封止し固定する。 That is, the superelastic metal plate 1 arranged in the vertical direction
A metal plate 11 having a coefficient of thermal expansion similar to that of the ceramic substrate 2 is welded at vertically symmetrical positions across 0, and the ceramic substrate 2 is bonded to one end by a method such as brazing, and the other end is welded. is placed on the lower metal casing 6, an O-ring 7 is arranged, and the upper metal casing 5 and the lower metal casing are hermetically sealed and fixed using screws 8 as in the conventional case.
このような構造をとるとセラミツク基板２と金
属板１１とは熱膨張係数が近似していることか
ら、この間では熱膨張係数の差による破壊は起こ
らず、また金属筐体５，６との熱膨張係数の差に
より生ずる応力は超弾性金属板１０の形成により
吸収できるので、従来のような破壊は無くなり、
信頼性の高い冷却構造が実用化できる。 With such a structure, the ceramic substrate 2 and the metal plate 11 have similar coefficients of thermal expansion, so no damage will occur between them due to the difference in coefficient of thermal expansion, and there will be no heat exchange between them and the metal casings 5 and 6. The stress caused by the difference in expansion coefficients can be absorbed by the formation of the superelastic metal plate 10, so the conventional breakage is eliminated.
A highly reliable cooling structure can be put into practical use.
超弾性金属板１０の構成材料としてはチタン
（Ti）−51％ニツケル（Ni）合金を使用した。
A titanium (Ti)-51% nickel (Ni) alloy was used as a constituent material of the superelastic metal plate 10.
また、半導体チツプを搭載するセラミツク基板
２の構成材料として熱膨張係数が4.4×10-6／℃
のガラスセラミツクスを用いているので金属板１
１の構成材料として膨張係数が4.5×10-6／℃の
42アロイ（Ni42％あとFe）を用いた。 Furthermore, the thermal expansion coefficient of the ceramic substrate 2 on which the semiconductor chip is mounted is 4.4×10 -6 /℃.
Since glass ceramics are used, metal plate 1
1 has an expansion coefficient of 4.5×10 -6 /℃.
42 alloy (42% Ni and Fe) was used.
ここで、超弾性金属板１０と金属板１１との熔
接は最大出力が400WのパルスNd−YAGレーザ
溶接機を用いて行い、またセラミツク基板２と金
属板１１との接合法としては、第１図に示すよう
にセラミツク基板２の裏面の接合部に銅（Cu）
ペーストを印刷焼成してメタライズした後、メツ
キ処理して厚さ約5μmのNiメツキ層１２を形成
し、金属板１１と半田付けした。 Here, the superelastic metal plate 10 and the metal plate 11 are welded using a pulsed Nd-YAG laser welding machine with a maximum output of 400W. As shown in the figure, copper (Cu) is applied to the joint on the back side of the ceramic substrate 2.
After printing and firing the paste and metallizing it, plating was performed to form a Ni plating layer 12 with a thickness of about 5 μm, which was soldered to the metal plate 11.
そして、セラミツク基板２をつけた金属部材１
３の片方にある金属板１１を従来のように下部金
属筐体６と積層し、Ｏリング７を介して上部金属
筐体５とネジ８で封止することにより冷却構造が
完成する。 Then, a metal member 1 with a ceramic substrate 2 attached thereto.
The cooling structure is completed by laminating the metal plate 11 on one side of the housing 3 with the lower metal housing 6 as in the conventional manner, and sealing the upper metal housing 5 with the screw 8 via the O-ring 7.
この場合は金属筐体内に１気圧のHeガスを封
入し、Heリークデテクタを用いて気密性を試験
したところ１×10-8atm cc／ｓ以下の高い気密
性をもつことが確認され、また−55℃〜＋125℃
の温度サイクルを10サイクル行つたが気密性に変
化は認められず、高い信頼性をもつことが確認で
きた。 In this case, 1 atm of He gas was sealed in the metal casing, and when the airtightness was tested using a He leak detector, it was confirmed that it had a high airtightness of 1×10 -8 atm cc/s or less. −55℃～＋125℃
After 10 temperature cycles, no change in airtightness was observed, confirming high reliability.
本考案によれば、金属筐体とセラミツク基板と
の熱膨張係数の差に起因する応力を容易に変形が
可能な超弾性金属板により吸収することができる
ことから接合部の破損による気密漏れはなくな
り、超寿命で信頼性の高い気密容器の形成が可能
となる。
According to the present invention, the stress caused by the difference in thermal expansion coefficient between the metal casing and the ceramic substrate can be absorbed by the easily deformable superelastic metal plate, eliminating airtight leakage due to damage to the joint. , it becomes possible to form a highly reliable airtight container with a long life.
第１図は本考案に係る金属筐体とセラミツク基
板との部分拡大断面図、第２図は本考案に係る半
導体装置の冷却構造の断面図、第３図は従来の半
導体装置の冷却構造で、Ａは断面図、Ｂは平面
図、である。
図において、１は半導体チツプ、２はセラミツ
ク基板、５は上部金属筐体、６は下部金属筐体、
７はＯリング、８はネジ、１０は超弾性金属板、
１１は金属板、１３は金属部材、である。
FIG. 1 is a partially enlarged cross-sectional view of a metal casing and a ceramic substrate according to the present invention, FIG. 2 is a cross-sectional view of a cooling structure for a semiconductor device according to the present invention, and FIG. 3 is a conventional cooling structure for a semiconductor device. , A is a sectional view, and B is a plan view. In the figure, 1 is a semiconductor chip, 2 is a ceramic substrate, 5 is an upper metal casing, 6 is a lower metal casing,
7 is an O-ring, 8 is a screw, 10 is a superelastic metal plate,
11 is a metal plate, and 13 is a metal member.
Claims (1)
セラミツク基板２を金属筐体に装着し、冷媒を用
いて冷却する構造として、 垂直方向に配置した超弾性金属板１０を挟んで
上下の対称位置に前記セラミツク基板２と熱膨張
係数の近似した金属板１１を熔着した金属部材１
３があり、該金属部材１３の一端に前記セラミツ
ク基板２を半田付けすると共に、他端をボルト８
締めにより上部金属筐体５と固定する下部金属筐
体６にＯリング７を用いて気密封止する構造をと
ることを特徴とする半導体装置の冷却構造。[Scope of Claim for Utility Model Registration] A superelastic metal plate 10 vertically arranged in a structure in which a ceramic substrate 2 on which a semiconductor device chip 1 such as an IC or LSI is mounted is attached to a metal casing and cooled using a refrigerant. A metal member 1 in which a metal plate 11 having a thermal expansion coefficient similar to that of the ceramic substrate 2 is welded to a vertically symmetrical position with the ceramic substrate 2 in between.
3, the ceramic substrate 2 is soldered to one end of the metal member 13, and the other end is connected to a bolt 8.
A cooling structure for a semiconductor device, characterized in that a lower metal casing 6 is fixed to an upper metal casing 5 by tightening and is hermetically sealed using an O-ring 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16524086U JPH0445250Y2 (en) | 1986-10-28 | 1986-10-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16524086U JPH0445250Y2 (en) | 1986-10-28 | 1986-10-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6370157U JPS6370157U (en) | 1988-05-11 |
| JPH0445250Y2 true JPH0445250Y2 (en) | 1992-10-23 |
Family
ID=31095098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16524086U Expired JPH0445250Y2 (en) | 1986-10-28 | 1986-10-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0445250Y2 (en) |
-
1986
- 1986-10-28 JP JP16524086U patent/JPH0445250Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6370157U (en) | 1988-05-11 |
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