JPH0445031B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal readout method for a solid-state imaging device.
This provides a solid-state imaging device in which all of the main electrodes serve as address lines or signal readout lines, with particularly excellent weak light detection sensitivity, more stable and uniform image detection, and a low power consumption, high-speed signal readout method. be.

The present invention can be applied to television cameras for broadcast stations, video cameras for home use, electronic still cameras, etc., as well as astronomical observation instruments that utilize high sensitivity and physical and chemical measuring instruments that utilize high speed.

[Conventional technology]

Conventional static induction phototransistor (SIPT)
It is called. ), the source and drain of the SIPT serve as signal readout lines or address lines, respectively, and the structure and signal readout method of the two-dimensional solid-state image pickup device using the gate storage method are disclosed in Japanese Patent Application Laid-open No. 199277-1983. "2
such as those disclosed in "Dimensional solid-state imaging device",
Various proposals have been made.

FIG. 4a shows an example of the configuration and signal readout method of a conventional two-dimensional solid-state imaging device. FIG. 4b shows a timing chart of the read pulse.

One of the n×m pixels arranged in a two-dimensional matrix, C _ij , consists of one SIPT and a capacitor. The drain of SIPT of pixel C _ij is connected to the signal readout line SL _i , the source is connected to the buried line BL _j , and the gate is connected to the vertical address line through the capacitor.
Connected to GL _j . Signal readout line SL _i
A precharge transistor Q _P is connected to
It is connected to the precharge power supply through this _QP . All gates of this Q _P are made common, and a precharge pulse φ _P is applied. Furthermore, SL _i is connected to a switch transistor Q _S through a transfer transistor Q _T , and Q _S is further connected to a video power supply V v through a common load resistor R _L , with the point where Q _S is connected to R _L The output terminal is V _put . Q _T has all gates in common, and transfer pulse φ _T is applied. The gate of Q _S is led to a horizontal shift register 42 . The output is obtained by a voltage drop across R _L by charging a transfer capacitor C _T commonly connected to Q _T and Q _S with Vv while Q _S is in a conductive state. Furthermore, the buried line BL _j is grounded through the buried line selection transistor Q _B ,
The gate of Q _B connected to BL _j is connected to GL _j ,
GL _j is led to a vertical shift register 41.

The reading method will be explained with reference to FIG. 4b. First, at time t ₁ , the transfer pulse φ _T
As a result, the transfer transistor Q _T becomes conductive, and the signal readout line SL _i is connected to the transfer capacitor C _T . At time t ₂ , the signal readout line SL _i and the transfer capacitor _CT are charged by V _P through the precharge transistor Q _P by the precharge pulse. Next, at time _t3 , the vertical address pulse φ _Gj is output from the vertical shift register 31, thereby causing the pixel connected to the vertical address line GL _j to
C _1j to C _oj discharge according to the amount of incident light. At this time, among the embedded line selection transistors Q _B , only the one connected to the selected BL _j is in a conductive state, and all others are in a cut-off state. Since φ _Gj and φ _T are cut off at the same time at time t ₄ , the pixel C _1j ,...,
The optical information of C _oj is stored as the discharge amount of the transfer capacitor _CT . At t ₅ , t ₆ , t ₇ , . _. . , t ₈ , one horizontal line of output is sequentially obtained from the V _put terminal by the read pulses φ _S1 , . The same procedure is then repeated to read out another horizontal line.

FIG. 4c shows another example of the configuration and signal readout method of a conventional two-dimensional solid-state imaging device. Figure 4d
shows the timing chart of the read pulse.

One of the n×m pixels arranged in a two-dimensional matrix, C _ij , consists of one SIPT and a capacitor. The source of SIPT of pixel C _ij is connected to the signal readout line SL _i , the drain is connected to the buried line BL _j , and the gate is connected to the vertical address line through the capacitor.
Connected to GL _j . _The signal readout line SL _i is grounded through the reset transistor Q _R
The gates of are all set in common and the reset pulse φ _R
is applied. Furthermore, SL _i is connected to the switch transistor Q _S through the transfer transistor Q _T.
Q _S is further connected to the video power supply Vv through a common load resistor R _L , and the point where Q _S is connected to R _L is an output terminal V _put . Q _T has all gates in common, and transfer pulse φ _T is applied. The gate of Q _S is led to a horizontal shift register 42 . The output connects the transfer capacitor C _T commonly connected to Q _T and Q _S ,
When making Q _S conductive and discharging through R _L ,
Obtained by the voltage drop across R _L. Furthermore, the buried line BL _j is a buried line selection transistor.
Connected to power supply V _DD through Q _B. The gate of Q _B is connected to GL _j , _which is guided to the vertical shift register 31 and a vertical address pulse φ _Gj is applied thereto.

The reading method will be explained with reference to FIG. 4d. First, at time _t1 , the transfer transistor _QT becomes conductive due to the transfer pulse, and the signal readout line _SLI is connected to the transfer capacitor _CT . At time _t2 , the signal readout line SL _i and the transfer capacitor _CT are brought to the ground potential through the reset transistor Q _R by the reset pulse φ _R . Next, at time t ₃ , the vertical address pulse φ _Gj is output from the vertical shift register 31, thereby causing the pixels C _1j , . . . , connected to the vertical address line GL _j
C _oj is biased by V _DD through a buried line selection transistor Q _B connected to buried line BL _j , and charges C _T according to the amount of incident light. By simultaneously cutting off φ _Gj and φ _T at time t ₄ , the optical information of the pixels C _ij , . . . , C _oj is stored as the charge amount of the transfer capacitor _CT . _t5 , _t6 , _t7 ,
..., _t8 , one horizontal line's output is sequentially obtained from the V _put terminal by the read pulses φ _S1 , . . . , φ _So from the horizontal shift register 42. The same procedure is then repeated to read out another horizontal line.

[Problem that the invention seeks to solve]

The two-dimensional solid-state imaging device using the above-mentioned SIPT is
It is a high-speed, low-power consumption, large-capacity solid-state imaging device that can utilize the high light sensitivity inherent in SIPT, and has excellent weak light detection sensitivity. This is because all three of the three main electrodes of the SIPT that constitute the pixel serve as address lines or signal readout lines. Focusing on the buried line BL _j, which is one of the address lines, the gate of the buried line selection transistor Q _B connected to this BL _j is connected to the vertical address line GL _j . This situation is shown in FIG. A corresponds to the example of the reading method shown in FIG. 4a, and b corresponds to the example of the reading method shown in FIG. 4c. In FIG. 5, C _BL represents the capacitance of one row of buried lines with respect to ground. In both cases of FIGS. 5a and 5b, a vertical address pulse φ _Gj as shown in c is applied to the vertical address line GL _j .
When φ _Gj is applied, in SIPT, φ _Gj is applied through the gate capacitor to the gate where the gate has reached a certain potential due to the accumulation of holes due to photoexcitation, and a current corresponding to the amount of incident light flows between the source and drain. At the same time, Q _B also becomes conductive due to φ _Gj , but
The operation speed of Q _B is slower than that of SIPT. Furthermore, the capacitance that the buried line BL _j has with respect to ground
There are also delays due to the influence of C _BL . That is, when selecting by φ _Gj , in a, C _BL must be discharged to set the potential of BL _j to the ground potential, and in b, C _BL must be charged. In the case of b, the potential of Q _B is also affected by the substrate bias effect, and cannot be sufficiently biased unless V _G is increased. From the characteristics of SIPT of one pixel, V _G is optimal between 1.5V and 3V, so Q _B
If the threshold value of is 1V, the bias voltage V _DS to SIPT is only about 1V even if V _DD is sufficiently large. The operation of SIPT is highly dependent on the address pulse to the gate and the bias voltage V _DS .
There was a problem that SIPT could not be operated under optimal conditions. In other words, if the value of V _G is set too large, the output in the dark state will increase, making it impossible to obtain a large dynamic range, and the same holds true even if V _DS is small. Furthermore, the current amplification factor of SIPT increases with V _DS .

[Means for solving problems]

The problem mentioned above is the capacitance that the buried line selection transistor Q _B and the buried line have with respect to ground.
In order to solve the problem of delay in SIPT operation due to C _BL and SIPT not being sufficiently biased, the vertical address line and the gate address of the buried line selection transistor Q _B are separated.

The method of operation will be explained with reference to FIG. Figure 2a corresponds to Figure 4a, and Figure 2b corresponds to Figure 4b.
It corresponds to A vertical address pulse φ _Gj is applied to the vertical address line GL _j , and φ _Bj is applied to the gate of the buried line selection transistor Q _B. At this time, φ _Bj is input earlier than φ _Gj by an amount τ to compensate for the delay of Q _B. This situation can be seen in the fourth
Shown in Figure c. Further, the pulse height V _G of φ _Gj and the pulse height V _B of φ _Bj are respectively determined appropriately.
In particular, in case b, the pulse height V _G of the address pulse to the gate of SIPT and the bias voltage V _DS can be independently controlled.

[Effect]

Although the signal readout method for a solid-state imaging device according to the present invention requires a more complicated readout circuit than the conventional one, it is possible to operate the SIPT that constitutes a pixel under optimal conditions.
The pulse φ _Gj input to the gate of SIPT and the bias voltage V _DS of SIPT can be controlled independently. Therefore, it is possible to provide a solid-state imaging device with higher sensitivity.

〔Example〕

An embodiment of the signal readout method for a solid-state imaging device according to the present invention is shown in FIG.

FIG. 1a shows one of the embodiments, and FIG. 1b shows a timing chart of the read pulse. First, the configuration of this solid-state imaging device will be explained. One of the n×m pixels arranged in a two-dimensional matrix C _ij consists of one SIPT 1 and a gate capacitor 2 .
The drain of the SIPT of this pixel C _ij is connected to the signal readout line SL _i , the source is connected to the buried line BL _j , and the gate is connected to the vertical address line GL _j through the gate capacitor. BL _j and GL _j are parallel and SL _i
is orthogonal to The signal readout line SL _i is connected to a precharge transistor Q _Pi , and is connected to a precharge power supply V _P through this Q _Pi .
Q _Pi has a common gate and a precharge pulse Q _P is applied. Further, SL _i is connected to a switch transistor Q _Si through a transfer transistor Q _Ti . All gates of Q _Ti are made common, and transfer pulse φ _T is applied. A suitable capacitor C _Ti is provided at the connection between Q _Ti and Q _Si , and Q _Si is connected to the video power supply Vv through a common load resistor R _L . The Q _S gate is guided to the horizontal shift register 12 and a read pulse φ _Si is applied thereto. The output is obtained from the V _put terminal by the voltage drop across R _L when C _Ti is charged by V v with Q _Si in the conductive state. Embedded line BL _j
is grounded through the buried line selection transistor Q _Bj . The gate of Q _Bj is guided to the vertical shift register 12, and a buried line selection pulse φ _Bj is applied thereto. Vertical address line _GLj is led to vertical shift register 11, and vertical address pulse _φGj is applied thereto.

Next, the operation will be explained with reference to FIG. 1b. The vertical shift register 11 sequentially outputs vertical address pulses φ _G1 , ..., φ _Gn , but as shown in FIG.
Now, it shows φ _Gj and the following φ _Gj+1 . At time t ₁ , transfer pulse φ _T
is input, and after the transfer transistor Q _Ti becomes conductive, at time t ₂ , the precharge pulse φ _P causes the signal readout line SL _i and the transfer capacitor C _Ti to be connected through the precharge transistor Q _P. Charge by V _P. Next, the time
At _t3 , only the buried line _BLj is brought to the ground potential by the buried line selection pulse _φBj . Immediately thereafter, at time _t4 , each SIPT of the pixels C _1j to _{C oj} connected to the vertical address line GL _j by the vertical address pulse φ _Gj discharges according to the amount of incident light. Here, the interval between t ₃ and t ₄ is approximately the time when BL _j is grounded by φ _Bj . φ _Gj at time t ₅ ,
By cutting off φ _Bj and φ _T at the same time, the pixel C _1j ~
The optical information of C _oj is stored as the amount of discharge in the corresponding transfer capacitors C _T1 to C _Tn . Thereafter, at times t ₆ , t ₇ , t ₈ ..., t ₉ , the horizontal shift register 13 receives read pulses φ _S1 , φ _S2 ,
By sequentially generating φ _S3 ..., φ _So , sequentially conducting Q _S1 , ..., Q _So , and charging C _Ti with the video power supply Vv through the load resistor R _L , the output is sequentially output from the V _put terminal. can get. When one horizontal row of optical information has been output in this way, the same procedure is repeated to read out the optical information of C _1j+1 , . . . , C _oj+1 next.

Another embodiment is shown in FIG. 1c. d shows the timing chart of the read pulse. First, the configuration of this solid-state imaging device will be explained. One of n×m pixels arranged in a two-dimensional matrix
C _ij consists of one SIPT1 and a gate capacitor2. The source of SIPT of this pixel C _ij is connected to the signal readout line SL _i , the drain is connected to the buried line BL _j ,
The gate is connected to the vertical address line GL _j through the gate capacitor. BL _j and GL _j are parallel,
Orthogonal to SL _i . The signal readout line SL _i is grounded through a reset transistor Q _Ri , and all gates of Q _Ri are made common and a reset pulse φ _R is applied. Further, SL _i is connected to a switch transistor Q _Si through a transfer transistor Q _Ti . All gates of Q _Ti are made common, and transfer pulse φ _T is applied. Q _{Ti
A suitable capacitor C Ti is provided at the} connection _between The connected point becomes the output terminal V _put .
A read pulse φ _Si is applied to the gate of the switch transistor Q _Si through the horizontal shift register 13 . The buried line BL _j is connected to the power supply V _DD through the buried line selection transistor Q _Bj . The gate of Q _Bj is guided to the vertical shift register 12, and a buried line selection pulse φ _Bj is applied thereto. Vertical address line _GLj is led to vertical shift register 11, and vertical address pulse _φGj is applied thereto.

The operation will be described with reference to a timing chart of read pulses in FIG. 1d. The vertical shift register 11 receives vertical address pulses φ _G1 ,...
..., φ _{Gn are} output sequentially, and _FIG . At time t ₁ , the transfer transistor Q _Ti becomes conductive due to the transfer pulse φ _Ti , and at time t ₂ , the reset pulse φ _R causes the signal readout lines SL _i and C _Ti to be connected through the reset transistor Q _Ri . Both are at ground potential. At time _t3 , first, only _BLj is biased through _QBj by _VDD by the embedded line selection pulse _φBj . At this time, φ _{Bj is set} so that the potential of BL _j becomes a predetermined value.
The value of and V _DD are determined. Immediately thereafter, at time _t4 , pixel _C1j is connected to vertical address line _GLj by vertical address pulse _φGj .
~C _oj Each SIPT discharges according to the amount of incident light.
Here, the interval between t ₃ and t ₄ is approximately the time required for the potential of BL _j to be charged to the aforementioned predetermined value. time
By simultaneously cutting off φ _Gj , φ _Bj , and φ _T at t ₅ , the optical information of pixels C _1j to _{C oj} is changed to the corresponding C _T1 ,
..., will be stored in C _To . After that, t ₆ , t ₇ , t ₈ ...
..., _t9 , the horizontal shift register 13 sequentially generates read pulses φ _S1 , φ _S2 , φ _S3 ..., φ _So , and Q _S1 ,
..., Q _So are sequentially made conductive to discharge the charge stored in C _Ti through R _L , C _1j ,...
..., the optical information of C _oj is output. When one horizontal row of optical information is output in this way, then C _1j+1 ,...,
The same procedure is repeated to read out the optical information of C _oj+1 .

In Figure 1 a and d, Q _Pi , Q _Ri , Q _Ti , Q _Si ,
Q _Bj are all indicated as MOS transistors, but
All of these do not need to be MOS transistors; SIT, bipolar transistors,
Of course, a switching transistor such as a JFET may also be used.

FIG. 3 shows an example of the structure of one pixel constituting this solid-state imaging device. a is its surface structure,
b schematically represents the cross-sectional structure taken along the line A-A' in a. In the example of the structure shown here, an n-channel SIPT made on a p-type Si substrate 318, a conductive transparent electrode 311 such as doped polysilicon, a transparent insulating film 312 such as SiO ₂ , and a p ⁺ gate of the SIPT. One pixel is constituted by a MOS capacitor 316.

In Figure 3a, vertical address line GL _j 3
5 is perpendicular to SL _i 39, so SL _i 39 becomes the signal readout line. Therefore, in this configuration example,
In the embodiment shown in Figure 1a, the SIPT is an inverted motion;
In the embodiment shown in FIG. 1c, the SIPT is an upright motion. Conversely, if the configuration is such that GL _j is perpendicular to the embedded line, then in the embodiment shown in Figure 1a,
SIPT is an upright motion, and in the embodiment shown in Figure 1c
SIPT is a handstand motion. At this time, of course,
The embedded line becomes a signal readout line.

Hereinafter, SIPT will be explained as an upright movement.

FIG. 3a shows the surface structure of one pixel centering on pixel C _ij . The part surrounded by the dashed line in the figure corresponds to this. 35 is a vertical address line GL _j ,
34 represents the embedded line BL _j and 39 represents the signal read line SL _i . BL _j 34 and GL _j 35 are parallel,
And it is orthogonal to SL _i 39. Each intersection is insulated from each other by an insulator such as SiO ₂ or PSG. Furthermore, in the figure, the signal readout line SL _i-1 31, the embedded line BL _j-1 33,
A vertical address line GL _j+1 37 is also shown.
32, 36, 38, and 310 are highly conductive substances such as Al-Si, and are SL _i-1 31 and GL _j 3, respectively.
5. Provided to reduce the resistance of GL _j+1 37 and SL _i 39.

In FIG. 3b, n ⁺ region 314 is the source region of SIPT, n ⁺ region 315 is the drain region, n ⁺
A region 317 is a channel region, and a region 313 is a separation region which separates adjacent pixels from each other. Although not shown in the figure, vertically adjacent pixels in FIG. 3a are also provided with isolation regions. The source region 314 is electroded by a conductive transparent electrode 319 made of doped polysilicon or the like and connected to the signal readout line 39 . The buried drain region 315 is continuous in the direction perpendicular to the plane of the paper and forms a buried line, but this can be improved by attaching a highly conductive electrode 34 such as Al-Si from the surface. The resistance of the embedded line is reduced. Gate capacitor electrode 311
are connected to vertical address lines 35 made of the same material.

As explained above in the pixel configuration, all the wiring is on the surface, so it is easy to fabricate the switch transistors provided for readout on the same chip. When the switch transistor is configured as an n-channel MOS transistor on a p-well, the potential of the p-well is the same as that of the p-substrate 318. A reverse bias may be applied to the p-substrate in order to prevent holes excited by long-wavelength light penetrating deep into the substrate from being diffused. Even in such a case, the substrate bias effect can be compensated for by the pulse voltage of φ _B in the present invention.

〔Effect of the invention〕

The signal readout method of the solid-state imaging device of the present invention is as follows:
By making the address pulse of the buried line selection transistor independent of the vertical address line, the delay due to the capacitance of the buried line selection transistor and the buried line with respect to the address pulse is compensated for, and the effect of substrate bias is compensated for. I can do it. This allows SIPT to be used under optimal conditions and is a readout method with high sensitivity and wide dynamic range.

FIG. 6 is a diagram showing the effect of the invention, and shows the photoelectric conversion of one pixel when the structure shown in FIG. 3 is operated according to the readout method shown in FIG. Examples of characteristics are shown. The size of one pixel is
65μm×65μm, power supply voltage V _DD = 3V, load resistance
R _L = 10kΩ, optical integration time (period from one address to the next address) T _LI = 11ms, wavelength 655nm (red)
, and the horizontal axis is the amount of incident light Pi
[μW/cm ² ], and the vertical axis shows the difference in output voltage V _put from the dark state ΔV _put [mV]. In the reading method of the present invention, φ _B is further set to 5V, and φ _G is input 100 ns faster. When φ _G =3V, the present invention provides an output that is more than twice as large at saturation output as compared to the conventional example. Furthermore, when φ _G =5V in the conventional example, the sensitivity is reduced to about 0.7 times, indicating that SIPT is not operating optimally. The threshold voltage of the buried line select transistor is, in this example,
Although the threshold voltage is 1V, it is desirable that the threshold voltage be somewhat large to prevent malfunctions due to strong incident light. In this way, the present invention can utilize the high photosensitivity of SIPT, and in this example, it is possible to read out from a weak light of 10 ^-2 μw/cm ² to light of 10 μw/cm ² or more with good linearity.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, in which a shows an example of the configuration, b shows the operating waveform of the readout, c shows another example, and d shows the operating waveform of the readout,
FIG. 2 is a diagram for explaining the operation of the present invention.
corresponds to Figure 1 a, b corresponds to Figure 1 c, and c
3 is a diagram showing a vertical address pulse, FIG. 3 is an example of the configuration of one pixel, a is a diagram showing a surface structure, b is a diagram showing a cross-sectional structure, and FIG. 4 is a diagram for explaining a conventional technique.
a is a configuration example, b is a diagram showing the operation waveform of the readout, c is another configuration example, d is a diagram showing the operation waveform of the readout, and FIG. 5 is a diagram for explaining the problems of the conventional technology. In the figure, a corresponds to Figure 4 a,
b corresponds to FIG. 4c, c is a diagram showing a vertical address pulse, and FIG. 6 is a diagram to show the effect of the present invention, which was confirmed through trial production and experiments. 1... Electrostatic induction phototransistor, 2... Gate capacitor, C _ij (i=1~n, j=1~m)...
...Pixel, GL _j (j=1 to m)...Vertical address line, SL _i (i=1 to n)...Signal readout line, BL _j (j=1 to m)...Embedded line, Q _Bj
(j=1~m)...Embedded line selection transistor, Q _Pi (i=1~n)...Precharge transistor, V _P ...Precharge power supply, Q _Ti (i=1
~n)...Transfer transistor, Q _Si (i
=1~n)...Switch transistor, V _put ...Output terminal, R _L ...Load resistance, Vv...Video power supply,
φ _Bj (j=1~m)...Embedded line selection pulse, _φGj (j=1~m)...Vertical address pulse,
Q _Ri (i=1~n)...reset transistor,
_VDD ...Power supply.

Claims (1)

[Claims] 1. Pixels C _ij composed of electrostatic induction phototransistors and gate capacitors are arranged in an n×m matrix, and vertical address lines GL _j (j=1 to m) are arranged.
are commonly connected to the gates of the static induction transistors constituting the pixel C _ij (i=1 to n) via the gate capacitor, and are connected to the signal readout line.
SL _i (i=1 to n) is commonly connected to the drain of the electrostatic induction phototransistor constituting the pixel C _ij (j=1 to m), and the embedded line BL _j (j=
1 to m) are commonly connected to the sources of the electrostatic induction phototransistors constituting the pixels C _ij (i=1 to n), and are connected to the embedded lines BL _j (j=1 to m).
is grounded through switch transistor Q _Bj ,
The signal readout lines SL _i (i=1 to n) are commonly connected to a precharge power supply through a switch transistor Q _Pi , and the switch transistors
The gates of Q _Pi are connected in common, and the signal readout line SL _i (i=1 to n) is connected in common to the output terminal via two series-connected switch transistors Q _Ti and switch transistor Q _Si . , a load resistor and a video power supply are connected between the output terminal and the ground, and the switch transistors Q _Ti (i=1 to n) all have gates in common. First, the embedded line BL _j (j=1~m)
A signal readout method for a solid-state imaging device, characterized in that an address pulse to the switch transistor _QBj connected to the vertical address line _GLj is inputted earlier by a predetermined time independently of an address pulse to the vertical address line GLj. 2 Pixels C _ij composed of electrostatic induction phototransistors and gate capacitors are arranged in an n×m matrix, and vertical address lines GL _j (j=1 to m) are arranged.
are commonly connected to the gates of the electrostatic induction phototransistors constituting the pixels C _ij (i=1 to n) via the gate capacitors, and the signal readout lines SL _i (i=1 to n) are connected to the gates of the electrostatic induction phototransistors constituting the pixels C ij (i=1 to n). _ij (j=1~
m) is commonly connected to the sources of the electrostatic induction phototransistors constituting the buried line BL _j
(j=1 to m) are commonly connected to the drains of the electrostatic induction phototransistors constituting the pixels C _ij (i=1 to n), and the embedded lines BL _j (j
=1~m) are commonly connected to a predetermined power supply through a switch transistor _QBj , the signal readout line SL _i (i=1~n) is grounded through a switch transistor _QRi , and the gate of the switch transistor _{QRi is} are connected in common, and furthermore, the signal readout line SL _i (i=1 to n) is commonly connected to an output terminal via two series-connected switch transistors Q _Ti and switch transistor Q _Si , and A load resistor is connected between ground and the switch transistor
Q _Ti (i=1 to n) is first connected to the switch transistor Q _Bj connected to the embedded line BL _j (j=1 to m) in the case of vertical addressing in a solid-state imaging device in which all gates are made common. A signal readout method for a solid-state imaging device, characterized in that the address pulse is inputted to the vertical address line _GLj independently of the address pulse and earlier by a predetermined time.