JPH09116817A - Solid-state image pickup device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce solid-pattern noise and a chip size by providing plural photoelectric conversion elements and switch means connected to the output terminals and resetting the photoelectric conversion elements with output voltage. SOLUTION: When the pulse of a high level is impressed on a terminal 122, and the pulse of the high level is impressed to a terminal 121, NMOS transistors MR11-MR12 and MR321 and R322 become on-states at respective timings. The photodiodes D21 and D22 of the image elements are reset to voltage Vres given to the terminal 123. After resetting terminates, the respective pulses of the terminals 122 and 121 drop to low levels and the accumulation operation of a photo carrier is started. Thus, the solid-state pattern noise and the chip size can be reduced by repeating such operation and setting next reset voltage by a previous read signal level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device having a reduced chip size (FPN) and a small chip size, and a driving method thereof.

[0002]

2. Description of the Related Art Conventionally, in a solid-state image pickup device, a photoelectric conversion element is basically composed of a metal-oxide-semiconductor MOS structure,
These photoelectric conversion elements are lined up in a one-dimensional form, line sensors are arranged in a two-dimensional form, and area sensors are lined up. They will become more technologically and socially in the future image era, such as video cameras and copiers. Development is expected.

An example of a solid-state image pickup device using such a photoelectric conversion element is shown in FIGS. FIG. 10 is a diagram showing the overall circuit configuration. In the figure, pixels 21-11 to 21
-Mn is formed in a matrix on the same substrate, and each pixel thereof is provided in an n-channel normally-on type (depletion type) SIT (static induction transistor) 22 as an image sensor and its floating gate 23. It is configured by a gate capacitor 24 and a p-channel enhancement type control transistor 25 having a source-drain passage connected to the floating gate 23 (each pixel is shown by a broken line in the figure).

The drain of the SIT (group
Board) video voltage V_DApplied, and arranged in the X direction
21-m1 of pixel groups 21-11 to 21-1n in each row;
Each row has a gate capacitor of ~ 21-mn SIT.
, 26-m connected to the vertical scanning circuit.
Direct shift register) 27 for row selection signal φ_G1,…, Φ
_GmIs applied. In addition, the pixel group 2 of each column arranged in the Y direction
1-11 to 21-m1; ...; 21-1n to 21-mn
The source of SIT is each column line 28-1, ..., 28-n
And connect these column lines to each column select transistor 2
9-1, ..., 29-n, common video line 30 and
The output Vout is output via a load resistor 31 having one of them grounded.
At that time, each column selection transistor 29-1, ..., 29-n
A horizontal scanning circuit (horizontal shift register) 32 for the gate of
Column selection signal φ_S1,…, Φ_SnAre sequentially applied.

Further, the control gate line 33 and the overflow drain line 3 are respectively connected to the gate and drain of the control transistor 25 constituting each pixel.
4 is connected to apply the control gate signal φ _C and the control drain voltage V _C.

FIG. 11 is a plan view showing the structure of four pixels adjacent to each other, and FIG. 12 is a sectional view taken along the line AA '. In this configuration example, in order to increase the area efficiency of the pixels formed on the substrate 40, four adjacent pixels are formed vertically and horizontally in the figure. The substrate 40 constitutes the drain of the SIT, and uses an n ⁺ or n-type semiconductor to grow an n ⁻ epitaxial layer 41 on the substrate 40, and an isolation region made of a buried insulator or the like on the epitaxial layer 41. 42 is formed to electrically and optically separate adjacent pixels. In each pixel, the gate and source of the SIT constitutes with a p ⁺ diffusion layer 43 and n ⁺ diffusion layer 44 formed on the surface of the epitaxial layer 41, respectively, the n ⁺ diffusion layer 44 through the wiring layer 45 made of polysilicon, for example Corresponding column lines 28-i, 28-
A row line electrode 46- made of, for example, polysilicon, which is connected to (i + 1) and forms row lines 26-i, 26- (i + 1) on the p ⁺ diffusion layer 43 via a gate oxide film.
i, 46- (i + 1) is deposited, and the row line electrode is p ⁺
A gate capacitor is formed in a portion facing the diffusion layer 43.

The p ⁺ diffusion layer 43 of each pixel is formed so as to extend to the central portion of four pixels adjacent to each other, and that portion serves as the source of the control transistor 25 of each pixel shown in FIG. On the surface of the epitaxial layer 41 in the central portion of the four pixels, the drain of the control transistor 25 of the four pixels is formed separately from the p ⁺ diffusion layer 43 forming the gate 23 of the SIT of each pixel and the source of the control transistor 25. A common p ⁺ diffusion layer 47 is formed, and the overflow drain line 34 is connected to the p ⁺ diffusion layer 47 via the wiring electrode 48. In addition, the control gate line 33 is formed on the surface of the epitaxial layer 41 between the p ⁺ diffusion layer 47 and the p ⁺ diffusion layer 43 via the gate oxide film.
The control gate electrodes 49 of the control transistors 25 of the four pixels forming the above are commonly provided.

The operation of this configuration example will be described below with reference to the signal waveform diagram of the timing chart shown in FIG.
Also in the present configuration example, the row line 26-
1 to 26-m are sequentially selected, and column lines 28-1 to 28-n are sequentially selected under the selection of each row line. Pixel signals are sequentially read out by the XY address method selected in this way, and the signal read-out period t in each row line is read.
During the horizontal blanking period t _{BL in} which the selection of the next row line is started after _H is completed, all the pixels in the row line are reset at the same time. 23 potential V _G (2,
The operation of 2) will be described with reference to FIG. In the potential V _G (2, 2) of the floating gates 23 of the pixels 21-22 shown in the bottom of FIG. 13, the solid line represents the potential when light is incident during imaging, and the broken line is the light that is not incident during imaging. Represents the electric potential of.

Referring to FIG. 13, at timing t ₁ , when row selection signal φ _G2 applied to row line 26-2 attains voltage Vφ _G , floating of each SIT connected to line 26-2 of this row. The potential of the gate 23 is approximately Vφ _G , and more specifically, the capacitance of the gate capacitor 24 is C
Assuming that the parasitic diffusion capacitance of the _G and p ⁺ diffusion layers 43 is C _J , {C _G / (C _J + C _G )} Vφ _G increases.

At timing t ₂ , the column selection signal φ _S2
Becomes high level and the column line 28-2, that is, the pixel 21
When −-22 is selected, a signal current depending on the potential V _G (2,2) of the floating gate 23 of the pixel 21-22 at that time is applied to the column line 28-2 and the column selection transistor 2.
9-2 and the video line 30, the current flows to the load resistance 31, and the voltage drop of the load resistance 31 reads the output signal V _OUT . In this signal reading, since the photocharges normally stored in the floating gate 23 are retained as they are, non-destructive reading is performed.

Next, the selection of the final line 28-n is completed, and all the pixels 21-2 connected to the row line 26-2.
The control gate signal φ applied to the control gate line 33 at the timing t ₃ when the signal reading of 1 to 21-2n is completed, that is, at the start of the horizontal blanking period t _BL.
The control transistor 25 to the negative voltage of _C is a voltage -Buifai _C to conductive (ON). At this time, the surface potential under the control gate electrode 49 changes from φ _S (0) to φ _S (−Vφ _C ), and the gate potential V _G (2,2) is forced to the potential φ _S (−Vφ _C ). is clamped, thereby photoelectric charge Q _P accumulated in the gate by light irradiation of the reading after the gate potential is reset is exhaled. Where the control gate signal φ _C
Voltage -Vφ _C of the control gate electrode 49 is equal to the surface potential φ _S (-Vφ _C ) of the SIT pinch-off voltage V _GO , and the control drain voltage V _GO.
It is set so that φ _S (−V φ _C )> V _C with respect to _C.

Timing t_Four, Ie horizontal blankin
Period t_BLAt the end of, the row selection signal φ_G2Low
Set to bell and control gate signal φ_CIs zero volts
You. In this way, the gate potential V_G(2,2) is V
_G(2,2) = φ_S(-Vφ _C) -Vφ_GDown to
After that, depending on the amount of incident light during the imaging period until the next read
Photoelectric integration is performed, for example, Q_P/ C_G(= ΔV
_GP) Only rises.

In this configuration example, the control gate signal φ _C is not applied only to the electrodes of the control gate line 33 of the pixel connected to the selected row line, but all the other pixels in the non-selected state. It is also applied to the electrode of the control gate 33. Therefore, the control gate signal φ _C becomes the voltage −Vφ.
_{At C} , the surface potential under the electrode of the control gate 33 of the non-selected pixel becomes substantially equal to φ _S (−Vφ _C ), that is, the pinch-off voltage V _{GO of} SIT, as in the selected pixel.
Some of equal accumulation of photoelectric charges in the non-selected pixel, it rise [Delta] V _GP of by the gate _{potential, φ S (-Vφ C) -Vφ} G + ΔV GP> φ S (-V
φ _C ), that is, even if ΔV _GP > Vφ _G , the potential φ _S (−V
φ _C ), that is, the photocharge corresponding to the gate potential exceeding the pinch-off voltage V _{GO of} SIT is swept out to the overflow drain line 34 through the channel under the control gate electrode. Moreover, since the overflow operation of this excess charge is performed for all the non-selected pixels every time the row line is switched, the potential of the floating gate may exceed the pinch-off voltage V _{GO due} to strong incident light. Therefore, the occurrence of the half-selection signal phenomenon can be effectively prevented. This can also be regarded as equivalently performing blooming control.

Further, each pixel is reset by clamping the potential of the floating gate 23 of SIT to φ _S (−Vφ _C ) by the control gate signal φ _C, so that the residual photocharge at the time of resetting is performed. It can be completely lost. Therefore, according to the present configuration example, it is possible to completely control the afterimage phenomenon that is often observed when the pn junction between the gate and the source of the SIT is biased in the forward direction and reset.

[0015]

However, the above-mentioned conventional example has a problem that solid pattern noise (hereinafter referred to as FPN), which is one of the drawbacks of the amplification type solid-state image pickup device, is large. Further, when considering the use of the detector as a light amount detector, it is necessary to extract the target object with high accuracy even in the dim light, and a so-called external light removing function is required.

In order to solve such problems, for example, Japanese Patent Laid-Open No. 06-21422 and Japanese Patent Application No. 05-2878.
No. 54, and Japanese Patent Application No. 05-28 in FIG.
A specific circuit example disclosed in No. 7854 will be shown.

In this conventional example, the unit pixel is NP.
It is composed of three devices, an N-transistor 51, a capacitor 52, and a PMOS transistor 53, and is arranged two-dimensionally with two pixels in the vertical direction and two pixels in the horizontal direction in FIG. Further, above the pixel portion driven by the vertical shift register I, a memory element driven by the vertical shift register II having the same structure as the pixel is also provided with an NPN transistor 71 and a capacitor 7.
2. The PMOS transistor 73 is composed of three devices, which are arranged in two rows and two columns. Further, a buffer means composed of a clamp capacitor 87, an NPN transistor 89 and an NMOS transistor 91 is provided between the pixel and the memory element, and is connected via switches 81 and 83.

The operation of the circuit example of FIG. 14 will be briefly described. First, in the pixel portion, an operation of accumulating optical carriers is performed, and when the signal is read out in units of rows, the clamp capacitance 8
7, output to the emitter terminal of the NPN transistor 89 through the buffer means. At this time, when the vertical shift register II is operated and the memory element is reset, since the read signal from the pixel is output to the emitter terminal of the memory element, the base potential of each memory element is different from the read signal. A voltage higher by about Vbe is written.

Next, the pixel is reset again, and after the second accumulation operation, the vertical shift register II is operated,
When the signal previously written in the memory element is read, the signal is inverted by the clamp circuit, and then the optical signal of the pixel is read again, in the clamp circuit, [signal by second accumulation]-[signal by first accumulation] ] Voltage can be obtained, this signal is written in the memory element by the same method as described above, and then the memory element is read again to the storage capacitor 57 which is the storage capacitor this time. After that, the horizontal shift register is operated to serially output each signal to the terminal 66.
Output to

In this case, although the FPN can be reduced and the external light can be removed, two memory elements and two vertical shift registers as many as the number of constituent pixels are required. The above-mentioned image pickup device has a drawback that the chip size becomes larger.

[0021]

The present invention has been made to solve the above-mentioned drawbacks, and the present solid-state imaging device has a plurality of photoelectric conversion elements, processing means provided at the output terminals thereof, and the processing. It is characterized in that it has switch means for connecting the output of the means to the output terminal of the photoelectric conversion element, and means for resetting the photoelectric conversion element with the output voltage of the processing means.

In the solid-state image pickup device, the photoelectric conversion element accumulates carriers generated by receiving light energy on the control electrode of the transistor, and outputs a signal based on the accumulated carriers from the main electrode region. It is a photoelectric conversion element. Further, in the above solid-state image pickup device, the switch means is a MOS transistor.

In the solid-state image pickup device according to the present invention, a plurality of photoelectric conversion elements, a clamp capacitance connected to a column output line of the photoelectric conversion element and a switch means, and the output of the clamp capacitance to the output end of the switch means. It is characterized by comprising reset means for resetting the photoelectric conversion element connecting terminals, and transfer means for transferring the output end of the switch means to an output line.

Further, in the present solid-state image pickup device, the transfer means stores the charge of the photoelectric conversion element via the switch means, and the charge of the charge is stored in the output line as a timing signal from the horizontal scanning circuit. It is characterized in that it is provided with a transfer switch means for transferring in time series. In the solid-state imaging device, the photoelectric conversion element is a bipolar photoelectric conversion element or an electrostatic induction photoelectric conversion element.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings together with each embodiment.

(First Embodiment) FIG. 1 shows the configuration of the first embodiment of the present invention. In order to simplify the description of this example, a one-dimensional photoelectric conversion device including two pixels will be described. Of these, one pixel part is a photodiode and two NMOS
It is composed of transistors. That is, the pixel portion is composed of photodiodes D21 and D22, NMOS transistors M121 and M122 whose gates receive the outputs thereof, and switching NMOS transistors M321 and M322. Further, the pixel output is the vertical output lines v1, v
Switch NMOS transistors MR41, M through 2
The pixel output is through switch NMOS transistors MR31, MR3 through R42, capacitors CC1, CC2 which are clamp capacitors, voltage followers MR81, MR82.
2 through the switch NMOS transistor M
R61, MR62, storage capacitors C1, C which are storage capacitors
2, switch NMOS transistors MR71, MR72
Is output to the terminal 141 through the horizontal output line vh and the voltage follower MR83.

The operation of this embodiment will be briefly described below with reference to the timing chart of FIG. First, at time t1, a high-level pulse is applied to the terminal 122, and then at time t2, a high-level pulse is applied to the terminal 121. At each timing, the NMOS transistors MR11, MR12 and MR321, MR32 are applied.
2 is turned on, and the photodiode D2 of each pixel
1, D22 are reset to the voltage Vres applied to the terminal 123. When the reset is completed, at time t3 and t4, the pulse of each of the terminals 122 and 121 falls to the Low level, and the photocarrier accumulation operation (first accumulation operation) is started. Here, in the photoelectric conversion element in this embodiment, electrons are transferred to the NMOS transistor M12.
1, M122 is accumulated on the gates, and the larger the amount of incident light is, the lower the gate potential is due to the negative charge of electrons.

When the accumulation operation is completed and the optical signal of each pixel is read out, at time t5, a high level pulse is applied to the terminal 126 to make the NMOS transistor MR4.
1, after turning on MR42, at time t6,
When a high level pulse is applied to the terminal 124 to bring the NMOS transistors MR21 and MR22 into the 0N state, the transistors M121 and M122 and MR21 and M of each pixel are
Inverting amplifiers are formed between R22, and the optical signals stored on the photodiodes D21 and D22 are output to the vertical output line v.
1, v2 and are stored in the clamp capacitors CC1 and CC2.

At the time t7, when the read operation of the optical signal is completed, this time, at the time t8, the pulse of the terminal 127 is made to fall, and the NMOS transistors MR51 and M51.
When R52 is turned off, the amplifier-side nodes N1 and N2 of the capacitors CC1 and CC2 are in a floating state at the potential applied to the terminal 128.

Thereafter, at time t9, H is applied to the terminal 122.
When the igh level pulse is applied and the vertical output lines v1 and v2 are reset, the voltage followers MR81, MR82
The voltages at the input points N1 and N2 of the terminal are swayed to the negative side via the capacitors CC1 and CC2, and at the times t10 and t11, the voltage at the terminal 1
26, 122 of the pulse is lowered, both ends of the capacitors CC1, CC2 are floated, and the reset MOS transistor MR1
1, after turning off MR12, at time t12,
When a high level pulse is applied to the terminal 125, the node N
The potentials of 1 and N2 are voltage followers MR81 and MR82.
Is output to the vertical output lines v1 and v2 through the operational amplifier of the above, and when a high-level pulse is applied to the terminal 121 at time t13, each pixel outputs the vertical output lines v1 and v2.
It is reset to the potential of.

After that, at the time t14, after the reset is completed, each pixel starts the second accumulation operation. Then, after the time t15, t16 and the accumulation operation is completed, the optical signal is read out again at the time t17, t18, t19, t20, t21, t22. At this time, a high level pulse is applied to the terminal 129 at the time t19. When applied, node N1,
The signal voltage of N2 is NMOS transistors MR61, MR
The data is read out to the holding capacitors C1 and C2 through 62, and then the horizontal scanning circuit 140 is operated to set the time t23, t24,
The signals of the storage capacitors C1 and C2 are serially output from the horizontal output line vh through t25, t26, t27, t28, t29, t30, and t31.
In addition, output terminal 14 via voltage follower MR83
The data is read out to 1 and the series of operations is completed.

As described above, in the present invention, the reset / accumulation / read operation is performed twice per cycle,
Moreover, in order to set the reset voltage of the sensor for the next time based on the previous read signal level, for example, if the dark state is set at the time of the first signal accumulation, or if the accumulation time is set to be negligible, the darkness of each pixel will be reduced. A signal from which the FPN including the current component has been removed can be obtained.

Considering the use as a detector for photoelectric conversion, even when external light is directly incident on the light-receiving surface of a pixel, if a subject is irradiated with light from a light source such as an LED during the second accumulation period, The external light component can be removed, and the detection accuracy can be significantly improved.

In this embodiment, the nodes N1 and N of the clamp portion are
Although an operational amplifier is provided in FIG. 2, there is no problem even if another buffer means such as a source follower or an emitter follower is used instead of the operational amplifier.

(Second Embodiment) FIG. 3 shows a circuit diagram of the second embodiment. This embodiment is different from the first embodiment in that photoelectric conversion elements are arranged in a two-dimensional array of vertical 2 pixels and horizontal 2 pixels, except that pixels are driven by the output of a vertical shift register. The same as in the first embodiment. Further, according to this embodiment, the memory cell 71 in FIG.
Since ~ 73 and the vertical shift register II are unnecessary, the chip size can be greatly reduced.

In the present 2 × 2 pixel sensor, each pixel is composed of a photodiode and three NMOS transistors, terminals VR1 and VR2 are supplied with the scan reset voltage from the vertical shift register, and terminals VT1 and VT2 are vertically shifted. The scan trace voltage from the register is supplied,
The high-level pulses of the horizontal lines h1 and h2 are sequentially supplied, the pixels from one horizontal line are read out, and the pixels of the next horizontal line are read out. Other timings operate in the same manner as in the first embodiment.

As described above, in the first and second embodiments, the pixel portion stores the photocarrier in the gate electrode of the NMOS transistor, and further uses the above-mentioned type of transconversion element in which the NMOS transistor is used as an inverting amplifier at the time of reading. , A MOS photoelectric conversion element, CMD, AMI,
The same operation and function can be realized by using other photoelectric conversion elements such as SIT. For example, in FIG. 4, SITs are used as photoelectric conversion elements and are arranged two-dimensionally with vertical 3 pixels and horizontal 3 pixels, and the pixels are driven by the output of the vertical shift register. Since the operation is almost the same as that of the first embodiment, it will be omitted.

In FIG. 4, SI is used as the photoelectric conversion element.
T (static induction transistors) QS11 to QS33 are used. For reading the signal from the SIT of the sensor, the output of the vertical scanning circuit 50 is set to an intermediate level voltage, the clamp operation is performed, and then the clamp output. Is fed back to the source of SIT through the NMOS transistors NM31 to 33. After that, when the output of the vertical scanning circuit 50 is set to the high level, the gate voltage VGS of SIT is: VGS = FB + ΦB (4) However, FB ... The output of the Darlington transistor after clamping ΦB ... Between the gate and the source of SIT It becomes a built-in potential and the reset voltage of the clamp capacitors CC1 to CC3 (terminal 1
By setting 07) to an appropriate value, new signal accumulation can be performed from the clamp output voltage.

It is needless to say that a plurality of photoelectric conversion elements arranged in a matrix may be used as the two-dimensional area sensor in this embodiment as well. Further, the reset / accumulation / readout operation is performed twice per cycle for each horizontal drive line, and the operation of setting the reset voltage of the next sensor based on the previous read signal level is the same as the above embodiment. In this way, the FPN having a two-dimensional pattern can be removed, and a high-density image signal with low noise and high S / N can be obtained.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
2 is a schematic circuit diagram of the embodiment of FIG. In this embodiment, a bipolar photoelectric conversion element is used as a photoelectric conversion element, and three photoelectric conversion elements are arranged one-dimensionally.

The operation of this embodiment will be briefly described with reference to the timing chart of FIG.

First, at time t0, the terminal 100 goes low.
When a level pulse is applied, the PMOS transistor M
At the same time when PR becomes conductive, the NMOS transistor MNR
1 is turned off, and the power supply voltage is applied to the emitter terminal of the NPN transistor QR from the voltage divided by the resistors R1 and R2 to VBE.
A voltage dropped as much as VRES appears. At this time, since the terminal 103 is at the low level, VRES> PMOS transistors MP11 to MP14
VTH (where VTH is the threshold voltage of each PMOS transistor), the resistors R1 and R2 are set so that the PMOS transistors MP11 to MP14 become conductive, and the base regions of the photoelectric conversion elements have been described above. It is reset to the emitter voltage of the NPN transistors QS1 to QS3 (first reset). After that, when the pulse of the terminal 100 becomes High level at time t1, the PMOS transistor MPR and the NPN transistor QR are turned off and the NMOS transistor MNR1 becomes conductive, so that the emitter terminal of the NPN transistor QR becomes GND potential and the PMOS transistors MP11 to MP14. Turns off, and the first reset ends.

Thereafter, at time t2, Hig is applied to the terminal 104.
When the h-level pulse is applied, the NMOS transistors MN11 to MN13 are rendered conductive, and the emitter potentials of the NPN transistors QS1 to QS3 of each pixel are reset to the reset potential (GND in the figure), and then at time t3, the terminal 103 When a high-level pulse is applied to the PMOS transistors MP11 to MP14, the base potentials of the NPN transistors QS1 to QS3 rise due to capacitive coupling through the base capacitors Cx1 to Cx3, and the base potentials between the base and emitter are increased. Voltage is forward biased, NP
The N transistors QS1 to QS3 perform an emitter follower operation, and holes on the base region in the floating state are recombined, and as a result, the base voltage is reset (second reset). When this reset ends, the pulse of the terminal 103 falls to the Low level at time t4,
This time, the base potential of each pixel is shifted to the negative side, the voltage between the base and the emitter is in the reverse bias state, and the accumulation operation is started at this point.

Next, after a lapse of a predetermined accumulation time, when the pulse at the terminal 106 is lowered to the low level at time t5, the PMOS transistors MP21 to MP23 are turned on and the clamp capacitors Cc1 to Cc3 become the voltage applied to the terminal 107. Will be reset. Then, at time t6, the pulse of the terminal 104 is lowered to the Low level, and NM
The OS transistors MN11 to MN13 are turned off, and the NPN
After the emitters of the transistors QS1 to QS3 are brought into a floating state, at time t7, the terminal 103
When a high level pulse is applied to the pixel, the base potential of each pixel is shifted to the positive side via the base capacitors Cx1 to Cx3, and the base-emitter voltage of the NPN transistors QS1 to QS3 of each pixel becomes a forward bias state. The signals photoelectrically converted in each pixel and accumulated in the base region are
It is read to the output lines v1 to v3 and supplied to the clamp capacitors Cc1 to Cc3 via the NMOS transistors MN21 to MN23.

When the read operation is completed in this way, at time t8, the pulse at the terminal 106 is raised and the PMO
After turning off the S transistors MP21 to MP23 and leaving the bases of the Darlington transistors D1 to D3 in a floating state, when a High level pulse is applied to the terminal 104 at time t9, the output lines v1 to v3 are reset and at the same time. The base and emitter potentials of the transistors D1 to D3 connected in Darlington through the clamp capacitors Cc1 to Cc3 are shifted to the negative side by an amount corresponding to the signal of each pixel. Further, thereafter, at time t10, the terminal 10
The pulse of 8 is dropped, and the NMOS transistor MN21
~ MN23 is turned off, the clamp capacitors Cc1 to Cc3 are disconnected from the output lines v1 to v3, the pulse of the terminal 104 is lowered, and then the first reset is performed again at time t11, and then this time t12. At terminal 109 Hi
Applying gh level pulse, NMOS transistor MN
After turning on 31 to 33 and applying a high level pulse to the terminal 103 at time t13, the bases of the NPN transistors QS1 to QS3 of each pixel are N.
The second with respect to the emitter potential of the Darlington transistors D1 to D3 via the MOS transistors MN31 to 33.
Is reset according to the signal voltage obtained by the previous accumulation. At this time, the higher the previously read signal voltage is, the lower the voltage value is reset.

Then, after the second reset and the second signal accumulation are completed, the base potentials of the Darlington transistors D1 to D3 are initialized at the times t16 to t17, the pulse of the terminal 109 is lowered at the time t18, and the terminal 11
After applying a high level pulse to 0 and turning on the NMOS transistors NM41 to 43, at time t19, when the pulse of the terminal 103 is raised, the voltage corresponding to the signal of each pixel is read out to the capacitors CT1 to CT3. Be done.
Then, after the time t22, a start pulse is input to the horizontal scanning circuit from the terminal 111 and a scanning pulse is input to the terminal 112, so that the pixel signal is read out in time series to the output terminal 115. Although not shown in the figure, the output terminal 115 is provided with output buffer means.

As described above, in the present invention, the reset / accumulation / readout operation is performed twice per cycle, and the reset voltage of the next sensor is set based on the previous read signal level. , For example, if the first signal accumulation is set to a dark state, the FPN-removed signal can be obtained, and even if the subject is exposed to external light during the first signal accumulation, the external light component is removed. You can

In the above description, the first and second accumulations are carried out.
The signals obtained in₁, V _TwoThen (V_Two−
V₁) Signal is output.
Drive circuit timing is only partially converted (V₁+
V_Two) Signal can also be obtained. According to this,
First, the signal V obtained in the first accumulation₁Read out the result
When the result signal amount is insufficient, V₁Again for the signal of
The second accumulation can be performed and the exposure amount (accumulation time)
Easy to optimize.

In the above embodiment, the pixel is described as a one-dimensional three pixel, but even if a plurality of pixels are arranged as the line sensor, this peripheral circuit can be configured in the same manner, and particularly the clamp capacitor. The Darlington transistor, the NMOS transistor, and the PMOS transistor in the periphery thereof may be provided for each column, thus performing the reset / accumulation / read operation twice per cycle.
A predetermined effect can be obtained.

(Fourth Embodiment) FIG. 7 shows a fourth embodiment of the present invention.
2 is a schematic circuit diagram of the embodiment of FIG. This embodiment is different from the third embodiment in that photoelectric conversion elements are arranged two-dimensionally with vertical 3 pixels and horizontal 3 pixels, except that the pixels are driven by the output of a vertical shift register. This is exactly the same as in Example 1.

In other words, the timing signal to the terminal 103 of the third embodiment supplies a predetermined voltage to the terminal 103 in this embodiment, and the start signal terminal 101 and the vertical scanning timing terminal to the vertical scanning circuit. According to the timing of 102, the supply voltage of the terminal 103 is switched to read the read signal for each horizontal drive line.
Then, the reset / accumulation / readout operation is performed twice per cycle for each horizontal drive line, and the reset voltage of the next sensor is set based on the previous read signal level.

Therefore, in the third embodiment, the so-called line sensor FPN can be removed, and in the fourth embodiment, the two-dimensional pattern FPN can be removed.
Actually, it is not limited to 3 rows and 3 columns, and for example, as a high-density area sensor of 640 rows and 460 columns, low noise and high S /
It is possible to obtain N high-density image signals.

Further, according to this embodiment, the memory cells 71-73 and the vertical scanning circuit II shown in FIG. 14 are not required, so that the chip size can be greatly reduced.

(Fifth Embodiment) In the third and fourth embodiments, the Darlington-connected NPN transistors are used for the outputs of the clamp capacitors Cc1 to Cc3, but the OP amplifiers OP1 to OP3 shown in FIG. 8 are used. But no problem at all.

In this embodiment, the OP amplifiers OP1 to OP are provided.
P3 is incorporated as a voltage follower and has a high input impedance and an extremely low effective output resistance. Therefore, a predetermined voltage is supplied to the terminal 107, a timing pulse is supplied to the terminal 106 to turn on / off the PMOS transistor, The read level can be transferred accurately. Also in this embodiment, the reset / accumulation / readout operation is performed twice per cycle for each horizontal drive line, and the reset voltage of the next sensor is set based on the previous read signal level. .

(Sixth Embodiment) FIG. 9 shows a sixth embodiment of the present invention.
The following shows an example. This embodiment is different from the fourth embodiment in that
This is a modified version of the transfer switch NM41-4.
3, holding capacity (clamping capacity) CT1 which is a signal storage capacity
3 is deleted and a load resistance RL is provided on the horizontal output line. With this configuration, some capacitance and
Since the switch can be deleted, the chip size can be reduced, and the base capacitance CX11 to CX13 to the clamp capacitance C can be reduced.
The transfer to C1 to CC3 is read at a normal speed, and high speed scanning is possible when the charges of the clamp capacitors CC1 to CC3 are output.

Here, the resistance value R during signal reading
When the signal voltage is VS, the current flowing through L is given by VS / RL (1), while the read time is ΔT, the change ΔVB of the base voltage of the Darlington transistor during the read operation is It is represented by.

ΔVB = (VS / RL) × (HFE ² × ΔT / CC) (2) where HFE is the current amplification factor of the NPN transistor, CC
Is the capacitance value of the clamp capacitors CC1 to CC3.

Therefore, if the load resistance RL, the signal holding (clamping) capacitance CC, etc. are set so that the value of the expression (2) becomes sufficiently small, a stable output can be obtained. In FIGS. 5, 7 and 8, the transfer gain AT from the storage capacitor CT to the stray capacitance CH such as the horizontal output line is given by AT = CH / (CT + CH) ... (3), in order to increase this. In addition, since it is necessary to increase the storage capacitance CT, in this embodiment, the chip size can be further reduced by directly outputting the charges stored in the clamp capacitance to the horizontal output line.

In each of the above embodiments, the photoelectric conversion element is a photodiode, a bipolar photoelectric conversion element, or an electrostatic induction photoelectric conversion element, but other photoelectric conversion elements may be used. Of course.

[0061]

According to the present invention, in a solid-state image pickup device, even when a large number of photoelectric conversion elements are integrated in order to secure high resolution, it is possible to reduce the solid pattern noise and the chip size. Can play.

Further, when considering the use of the detector as a light quantity detector, the chip size can be reduced while enhancing the so-called external light removing function of extracting the target object with high accuracy even in the dim light.

[Brief description of the drawings]

FIG. 1 is a schematic equivalent circuit diagram according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 5 according to one embodiment of the present invention.

FIG. 3 is a schematic equivalent circuit diagram according to an embodiment of the present invention.

FIG. 4 is a schematic equivalent circuit diagram according to an embodiment of the present invention.

FIG. 5 is a schematic equivalent circuit diagram according to an embodiment of the present invention.

FIG. 6 is a timing chart illustrating the operation of FIG. 5 according to the exemplary embodiment of the present invention.

FIG. 7 is a schematic equivalent circuit diagram according to an embodiment of the present invention.

FIG. 8 is a schematic equivalent circuit diagram according to an embodiment of the present invention.

FIG. 9 is a schematic equivalent circuit diagram according to an embodiment of the present invention.

FIG. 10 is a schematic equivalent circuit diagram of a conventional solid-state imaging device.

FIG. 11 is a plan view of the periphery of a pixel by a conventional solid-state imaging device.

FIG. 12 is a schematic sectional view of a conventional solid-state imaging device.

FIG. 13 is a timing chart illustrating the operation of the conventional solid-state imaging device.

FIG. 14 is a schematic equivalent circuit diagram of a conventional solid-state imaging device.

[Explanation of symbols]

 21 pixels 22 SIT 23 floating gate 24 gate capacitor 25 control transistor 26 row line 27 vertical scanning circuit 28 column line 29 each column selection transistor 30 video line 31 load resistor 32 horizontal scanning circuit QS1 to QS3 pixel transistor CX1 to CX3 gate capacitance CC1 to CC3 Clamp capacity CT1 to CT3 Storage capacity

Claims (9)

[Claims] 1. A solid-state image pickup device comprising a plurality of photoelectric conversion elements, processing means provided at an output terminal thereof, and switch means for connecting an output of the processing means to an output terminal of the photoelectric conversion element. A solid-state imaging device comprising means for resetting the photoelectric conversion element with the output voltage of the above. 2. The solid-state imaging device according to claim 1, wherein the photoelectric conversion element accumulates carriers generated by receiving light energy on a control electrode of a transistor, and accumulates the carriers from a main electrode region of the transistor. A solid-state image pickup device, which outputs a signal based on the carrier. 3. The solid-state image pickup device according to claim 1, wherein the switch means is a MOS transistor. 4. A photoelectric conversion element arranged in a plurality of columns, a clamp capacitance connected to a column output line of the photoelectric conversion element and a switch means, and an output terminal of the clamp capacitance is connected to an output terminal of the switch means. A solid-state imaging device comprising: reset means for resetting the photoelectric conversion element; and transfer means for transferring the output end of the switch means to an output line. 5. The solid-state imaging device according to claim 4, wherein the transfer unit horizontally scans the output line with the storage capacitor storing the charge of the photoelectric conversion element via the switch unit and the charge of the storage capacitor. A solid-state imaging device comprising transfer switch means for transferring in time series in accordance with a timing signal from a circuit. 6. The solid-state imaging device according to claim 4, wherein the photoelectric conversion element is a bipolar photoelectric conversion element or an electrostatic induction photoelectric conversion element. 7. A plurality of photoelectric conversion elements, a processing means provided at an output terminal thereof, and a switch means for connecting one output of the processing means to an output terminal of the photoelectric conversion element,
The other one is a method for driving a solid-state imaging device that outputs pixel signals, in which the photoelectric conversion element is reset by the output voltage of the processing means, and after the reset, the switch means is turned off to output the pixel signal output. A method for driving a solid-state imaging device, comprising: 8. The method for driving a solid-state imaging device according to claim 7, wherein the photoelectric conversion element accumulates carriers generated by receiving light energy on a control electrode of the transistor, and a main electrode region of the transistor. A method for driving a solid-state imaging device, which is a photoelectric conversion element that outputs a signal based on the carrier accumulated from the photoelectric conversion element. 9. The method for driving a solid-state image pickup device according to claim 7, wherein the processing means transfers the output of the photoelectric conversion element to a storage capacitor, and the charge of the storage capacitor is connected to the switch means. A method for driving a solid-state imaging device, which is characterized in that pixel signals are output.