JPH0444692A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To unnecessitate a dummy memory cell by adopting two transistors and one capacitor as memory cells. CONSTITUTION:In the circuit diagram of the semiconductor memory, the fact of composing memory cell parts 45-50 are composed of two transistors and one capacitor is different from conventional one, and a dummy word line and the dummy memory cell are unnecessitated. As the configuration, in the semiconductor memory crossing the two bit lines at every two paired bit lines in the middle of the paired bit lines, two gates among transfer gates 27-38 are connected to one word line in paired bit lines 1a, 1b, 2a, 2b, 3a and 3b, and the sources of the respective transfer gates are connected to capacitors 39-44.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device, and particularly to a semiconductor memory device that prevents signal read errors.

[Conventional technology]

FIG. 2 is a circuit diagram of a dynamic semiconductor memory device in which a memory cell is constructed of a conventional one-transistor l-capacitor. Bit line pair (1a, lb), (2a2b)
, (3a, 3b) have multiple capacitors +41
, +5).

(6), (71, (8), (9), and a transformer 7 cable 40 for connecting the bit line and the capacitor.
(1, Gυ, @6 (to) a4), (to) are connected, and memory cells C16, σ, (181°, CO, O) are configured with one transistor and one capacitor, respectively. In addition, the dummy word line (52) has dummy memory cells (53), (54), (54), which have the same configuration as the memory cells 0G, ση, a8° concave, m, and o, respectively.
(55) is connected.

In this dynamic semiconductor memory device, in FIG.
For example, bit line pair (2a), r2b) is selected and its operation will be explained in the following case.

First, for writing, a positive voltage is applied to the word line, transfer gate a2 is made conductive, and after electrons are supplied from the bit line, transfer gate Q2
If it is made non-conductive, electrons will be accumulated in the capacitor (6) and information L'' will be written.If electrons are not supplied from the bit line (M), the capacitor (6) will be empty of electrons and information will not be written. 'H.' will be written.

Mayu, for reading, bit line pair (2b), (2b
> is set to a predetermined potential yp (precharge potential), and then set to a floating state and the transfer gate @ is opened, the electrons stored in the capacitor (6) and the electrons present in the bit line (2a) are averaged. If the bit line (2a) potential is slightly lower than 9.
．． In the case of information ~H'', the potential of the bit lFM (2a) rises a little. This is compared with the potential of the bit line (2b) serving as a reference potential, and the difference is amplified by the sense amplifier 6.

Next, consider the signal voltages that appear on each bit line pair when reading signals. As shown in FIG. 3, each bit line is assumed to have a capacitance CBB relative to the adjacent bit line by 08% relative to the ground voltage (fixed potential) via the cell plate or substrate.

If the memory cell capacity is C8, the write voltage is V when writing H'' to the memory cell.If it is 0, C3Voo,
'The charge that becomes 0 at the time of writing is stored.

Set the bit line precharge level to VCC■, and set the cell plate voltage to V. If P, for example, the bit line pair (2a), r2b) is selected, and the bit line (mu) is selected.
H'' bit line is #L'', the potential of bit line (lb) is -
Consider the case where the potential of the bit line (3a) is v2''.

The displacement of the bit line (2a) before and after reading is CBVp +CB (VOOVOP) =CBVH+
CB (VHVop) + CBB (VH-VL)
−+−CBB(VH-V, ) −−−−−(1)
The displacement before and after the readout of the bit line
L-voP)+CBBrV, -VH)-1-08Bff
, -V2) ------+2) Using the above equation 11), the above equation (2), and the fact that VP= +/2Vcc.

l/2Csvoo=C box (VH-vL)+C3(vH-
vL)+2 CBB(VH-V,) + CBB(VH
-VL-V, -1-V2) ---(3) The above formula (3) is obtained. In the above equation (3), when the read potential difference becomes the smallest due to the influence of bit line noise,
, = vL, and v2 = vH.

At this time, I/2C8voo=(vH-■,)(CB+Cs+4C
BB)...(4), and the read potential difference becomes.

As memory cells become more highly integrated and the bit line pinch becomes smaller, the bit line capacitance CBB increases, the read potential difference decreases, the read margin decreases, and the soft error resistance deteriorates, eventually resulting in malfunction. The problem arises.

As a conventional version of this 5 that has been improved to address the problem,
There is a method in which two bit lines of every other bit line pair are crossed in the middle of the bit line pair. This method attempts to suppress a decrease in the read potential difference due to an increase in the amount of bit line interrogation. Next, a description will be given of how noise in capacitance between adjacent bit lines is reduced by this method.

FIG. 4 is a circuit diagram of an improved conventional dynamic semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. 60-254489. In the figure, 4 (51) represents the intersection of the bit line pair.

FIG. 5 corresponds to FIG. 3 above and shows the capacitance for each bit line. For the sake of explanation, the bit line is divided into a part A and a part B, each having a total length l. Therefore, the bit line capacitance of each part is I/2CB,
It is I/2CBB. Consider a bit line pair (2a), (2b) which is a bit m pair having an intersection 0 potential ri of the bit line (2a).

CBVP+C3(Voo-voP)=CBVH+C3(
VH-voP)-t-CBB(VH-V,)+Cp(V
H-V, ) +cprv, -v, )-(6) In a semiconductor memory device having a Sotho line configuration, a memory cell is configured with two transistors and one capacitor.

[Effect]

The semiconductor memory device of the present invention has a memory cellular configuration with two transistors and one capacitor, so that even if a change in potential occurs due to p-bit line capacitance noise with a large read potential difference, the read bit line and the reference If the bit line potential level is reversed, the dummy memory cell becomes unnecessary.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of a semiconductor memory device which is an embodiment of the present invention. The difference from the improved conventional one shown in FIG. Word lines and dummy memory cells are no longer needed.

As for the configuration, in a semiconductor memory device in which two bit lines of every other bit line pair intersect in the middle of bit a pair, bit line pairs (Ia), (lb), (2m)
.

In (2b), (M), and (3b), two transfer gates are provided for each word line @, C
9,cl! a.

ω, (111,((2,(33,Gya, C(S,
Cla, @, @ (D gate connected, the source of each tra/sphere gate is a capacitor), [, uI
l, iW, icl, -.

Next, consider the signal voltage that is applied to each bit line pair when reading a signal in the dynamic semiconductor memory device described above.However, in this embodiment, only the memory cells are different from the improved conventional example. , the diagram showing the capacitance relationship of each bit line with respect to FIG. 1 is the same as FIG. 5.

For example, considering the read potential difference between bit line pair (2a) and (2b), the change in potential of bit line (2a) is as follows: CBVP+C8'Voo=CBVH+C8'(v!(-)
■,)+... (a) Due to potential change of bit line (2b).

CBVP-C8'Voo-C8VL+C8'(VL-V
H) + αG 01 and OυEk2C3′■. . =CB(vH-vL)+2C8'(vH
-VL)+= (vf(-VL)(CB+2 C8'
+30BB)"Ql Therefore, the read potential difference is as follows.Comparing the above equation B and the above equation (9), C8' is doubled in one molecule part, but in this - equation, C8'
' is quite small compared to CB. It can be seen that Cs''co has quadrupled in the one molecule portion, and the read potential difference has been greatly improved.

Also, according to this embodiment, the capacitance of the memory cell capacitor is 0.
8' is reduced to 1/4 of the conventional one shown in FIG. 2, and the bit line crosses only once even in a cold state, thereby further improving the conventional improvement example without using dummy memory cells. It is possible to obtain the same effect of preventing reduction in read potential difference due to noise between bit lines as in the bit line double crossing method disclosed in Japanese Patent Publication No. 63-26895.

In the bit line crossing method disclosed in Japanese Unexamined Patent Publication No. 63-26895, the read potential difference VH-VL, which is calculated in the same manner as in this embodiment, is the same for any bit line.

Note that in the above embodiment, an NMO8 type O8 amplifier is used as the sense amplifier.
An 8-type sense amplifier may also be used.

Furthermore, in the above embodiments, the configuration in which the bit line pairs do not have an intersection and the configuration in which every other bit line pair has an intersection have been described, It can be placed anywhere on the bit line.

In a semiconductor memory device having a power line configuration, a memory cell is constructed of two transistors and one capacitor.

[Effect]

In the semiconductor memory device of the present invention, by configuring a memory cell with two transistors and one capacitor, even if a change in potential occurs due to capacitance noise between υ bit lines with a large read potential difference, the read bit line and If the potential level of the reference bit line is reversed, the dummy memory cell becomes unnecessary.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of a semiconductor memory device which is an embodiment of the present invention. It differs from the improved conventional one shown in FIG. 4 in that the memory cell section -, M, (471, decoy, mω) is composed of two transistors and one capacitor, and also has a dummy word line. and dummy memory cells are no longer needed.

As for the configuration, in a semiconductor memory device in which two bit lines of every other bit line pair intersect in the middle of the bit line pair, bit line pairs (Ia), (lb), (2a)
.

In (2b), (3a>, (3b), two transfer gates are provided for one word line, respectively.
28. +29°ω, (111, ■*cl*Mt”, (
The gates of (to), (b), and (to) are connected, and the source of each transfer gate is connected to the capacitor), m, snoring,
vomit, +43. (Foundation) is connected to.

Next, consider the signal voltages applied to each bit line pair during signal reading in the dynamic semiconductor memory device. However, since this embodiment differs only in the memory cells from the improved conventional example, the diagram showing the capacitance relationship of each bit line with respect to FIG. 1 is the same as FIG. 5.

For example, considering the read potential difference between the bit line pair (2a) and (2b), the potential change of the bit line (2a) is CBV, +C3'voo=CBVH+Cs'(vH-v
L) +... (A) What is the potential change of the bit line (A)?

CBVp CB' V()() =C5VL+C8
'(2C3'Voo= CB(VH-V,) + 2C8' from VLVHl + αG 01 and Oυ
(VH-VL) -1-1 (VH -vL) (CB+208'+30BB)...oη Therefore, the read potential difference is.

When comparing the above formula and the formula (9), C8' is doubled in the denominator part, but in this decoy formula, C8
' is quite small compared to CB. It can be seen that in the 5 molecule part, Cs''co has increased by 4 times, and the read potential difference has been greatly improved.

Furthermore, according to this embodiment, even when the capacitance 08' of the memory cell capacitor is reduced to 1/4 of that of the conventional capacitor shown in FIG. Bit line 2 shown in Japanese Patent Application Laid-Open No. 63-26895, which is a further improvement over the conventional improvement example, even if it is not used.
It is possible to obtain the same effect of preventing reduction in read potential difference due to noise between bit lines as in the cross-over method.

In the bit line crossing method disclosed in Japanese Unexamined Patent Publication No. 63-26895, the read potential difference VL for performing calculations similar to that of this embodiment is the same for any bit line.

In the above embodiment, an NMO8 type O8 amplifier is used as the sense amplifier.
An 8-type sense amplifier may also be used.

Furthermore, in the above embodiments, a configuration in which the bit line pairs do not have an intersection and a configuration in which every other bit line pair has an intersection have been described. It can be placed anywhere on the line.

Furthermore, the memory cell capacitor used in the above embodiment is as follows:
It can be applied to capacitors of any shape without particular limitation.

〔Effect of the invention〕

As described above, according to the present invention, in a semiconductor memory device in which two bit lines of every other bit line pair have a folded bit line configuration, two transistors and one capacitor are used as memory cells, so that the bit This has the effect of reducing the influence of noise from adjacent bit lines via line capacitance on the read potential difference, and eliminating the need for dummy memory cells.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device that is an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional semiconductor memory device, and FIG. 3 is a diagram showing the capacitance relationship of each bit line in the circuit of FIG. Explanatory diagram,
FIG. 4 is a circuit diagram of a semiconductor memory device which is the first improved example of the conventional technology, FIG. 5 is an explanatory diagram showing the capacitance relationship of each bit line in the circuit of FIG. 4, and FIG. 6 is the second improved conventional example. FIG. 2 is a circuit diagram of an example semiconductor memory device. In the figure, ~QB is a sense amplifier, G~ (to) is a transfer gate, ~t44Fi capacitor, -~
ω indicates a memory cell, and (51) indicates a bit line intersection. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] It has a memory cell array consisting of a plurality of word lines and bit lines and memory cells located at their intersections, and the two bit lines form a pair and input to one sense amplifier that detects the potential difference between the bit lines. Further, in a semiconductor memory device having a configuration in which the bit line pairs have bit line intersections in every other bit line pair, the memory cell storing one bit is gated by one capacitor and the same word line. control, one of the sources and drains of the transistors of each memory cell is connected to one of the bit lines of the bit line pair, and the remaining source and drain of each of the transistors are the electrodes of the capacitor. A semiconductor memory device comprising two M/S transistors connected to a film.