JPH044432U - - Google Patents
Info
- Publication number
- JPH044432U JPH044432U JP4531890U JP4531890U JPH044432U JP H044432 U JPH044432 U JP H044432U JP 4531890 U JP4531890 U JP 4531890U JP 4531890 U JP4531890 U JP 4531890U JP H044432 U JPH044432 U JP H044432U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- integrated circuit
- semiconductor integrated
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4531890U JPH044432U (enExample) | 1990-04-27 | 1990-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4531890U JPH044432U (enExample) | 1990-04-27 | 1990-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH044432U true JPH044432U (enExample) | 1992-01-16 |
Family
ID=31559385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4531890U Pending JPH044432U (enExample) | 1990-04-27 | 1990-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH044432U (enExample) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229510A (ja) * | 1987-03-18 | 1988-09-26 | Fujitsu Ltd | クロツク・スキユ−計算方式 |
-
1990
- 1990-04-27 JP JP4531890U patent/JPH044432U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229510A (ja) * | 1987-03-18 | 1988-09-26 | Fujitsu Ltd | クロツク・スキユ−計算方式 |