JPH04440B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital color demodulation circuit suitable for use in a color television receiver capable of double-speed scanning.

Generally, screen display using interlaced method is
When there are 525 scanning lines, one field is composed of 262.5 lines, and by sending this at 60Hz,
Surface frizz is suppressed. Further, in order to obtain vertical resolution, the next field is scanned with a shift of 1/2 scan line interval.

However, in this case, even though macroscopically the number of images is 60 per second, microscopically one scanning line lights up every 1/30 second, and the display cycle is 1/30. Seconds. Therefore, the light emission of this one scanning line is visually perceived as flicker. That is, line flicker exists.

In order to reduce this line flicker, the display period of one scanning line may be made shorter than 1/30 seconds. Therefore, color television receivers have been proposed that perform double-speed scanning with twice the horizontal frequency. In this case, the display period of both surface lines is 1/
60 seconds, and no surface flicker or line flicker is felt.

In order to perform double-speed scanning in which the horizontal frequency is doubled, the interlaced color television signal is converted to a non-interlaced color television signal in which the horizontal frequency is doubled and then supplied to the picture tube. be done.

As a method for this double speed conversion, a method has been proposed in which a luminance signal and a carrier color signal are separated from a color television signal and then each is converted. FIG. 1 shows an example.

In the figure, 1 indicates an input terminal, to which a color television signal S _V is supplied. This color television signal S _V is transmitted by the brightness/color separation circuit 2.
and is separated into a luminance signal Y and a carrier color signal C.

The carrier color signal C is supplied to an analog color demodulation circuit 3, and the color demodulation circuit 3 outputs a red difference signal R-Y.
and a blue color difference signal B-Y is obtained. These red color difference signals R-Y are supplied to a double speed conversion circuit 4, where they are subjected to double speed conversion. That is, the double speed conversion circuit 4, for example,
1H memories (random access memories with storage capacity for pixels of one horizontal period (1H), that is, one scanning line) 4c and 4d, for convenience of explanation, control writing to and reading from both memories, respectively. It is composed of switch circuits 4b and 4e, etc. The switch circuit 4b is switched to the memory 4c and 4d side every 1H, and the switch circuit 4e is switched to the opposite side. In addition, the switch circuit 4b
The memory selected by the switch circuit 4e is supplied with a write clock pulse having the above-mentioned pixel timing, and the memory selected by the switch circuit 4e is supplied with a read clock pulse of twice the frequency.

The red difference signal R-Y from the color demodulation circuit 3 is A-D.
After the analog signal is converted into a digital signal by the converter 4a, it is sent every 1H via the switch circuit 4b.
The red difference signal R-Y for 1H is supplied and written to the memories 4c and 4d for each 1H, and the red difference signal R-Y for 1H is written to the immediately preceding 1H from the memories 4d and 4c.
is read out twice in succession with a period of 1/2H, and is supplied to the DA converter 4f via the switch circuit 4e. Therefore, the D-A converter 4f
The horizontal frequency is doubled, and a red difference signal R-Y' which has been converted to a double speed is obtained, which is supplied to the matrix circuit 6.

Further, the blue color difference signal B-Y is supplied to the double speed conversion circuit 5. This double speed conversion circuit 5 is constructed in the same manner as the above-mentioned double speed conversion circuit 4, and from this double speed conversion circuit 5, the horizontal frequency is doubled and a double speed converted blue color difference signal B-Y' is obtained. The signal is supplied to the matrix circuit 6.

Further, the luminance signal Y obtained from the luminance/color separation circuit 2 is supplied to the double speed conversion circuit 7. In this case, although not shown, the double speed conversion circuit 7 is composed of, for example, a 1H memory, a switch circuit, a delay circuit, etc., and its output side receives the signal of each scanning line of the luminance signal Y and the signals of the scanning lines before and after it. The arithmetic mean of is 1/2
The horizontal frequency obtained alternately with a period of H is 2.
The luminance signal Y′ is obtained by multiplying the speed by two times. Then, this double-speed converted luminance signal Y' is supplied to the matrix circuit 6.

Output terminals 6a, 6b, and 6c of this matrix circuit 6 output red, green, and blue primary color signals R', G', which are doubled in horizontal frequency and converted to double speed.
B' are obtained and supplied to a picture tube (not shown), where they are subjected to double-speed scanning to produce a non-interlaced display as described above.

In this way, in the example shown in FIG. Each of the difference signal B-Y systems has double-speed conversion circuits 4 and 5, and since the A-D converter 4a used in these conversion circuits 4 and 5 is expensive, the device as a whole is expensive. There was an inconvenience.

In view of this, the present invention has a relatively simple structure including one double-speed conversion circuit, and is designed to obtain double-speed converted red difference signals and blue difference signals from ordinary carrier color signals. This paper attempts to propose a digital color demodulation circuit.

Hereinafter, one embodiment of the color demodulation circuit according to the present invention will be described with reference to FIG. This second
In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 2, a luminance signal Y obtained from a luminance/color separation circuit 2 is supplied to a matrix circuit 6 via a double speed conversion circuit 7, similar to the conventional example shown in FIG. On the other hand, the carrier color signal C is supplied to the A-D converter 8 and converted from an analog signal to a digital signal.

Further, the carrier color signal C is supplied to the burst gate circuit 9, from which a burst signal of frequency fsc (fsc is the color subcarrier frequency of approximately 3.58 MHz) is obtained, and this burst signal is passed through the frequency multiplier 10 to 4
The signal is multiplied by 4, and the frequency of the signal multiplied by 4 is divided by 5 by a frequency divider 11. Therefore, a signal with a frequency of 4/5 fsc is obtained from the frequency divider 11, and this is sent to the phase adjustment circuit 1.
2 to the A/D converter 8 as a sampling pulse Ps.

This sampling pulse Ps is adjusted by the phase adjustment circuit 12 to obtain an appropriate phase, which will be described later, that is, as shown in FIG. 4B.
The phase is set as shown in .

Here, we will explain why the sampling frequency is set to 4/5 fsc and how its phase is selected.

The carrier color signal of the NTSC color television signal is formed by quadrature two-phase modulation using the red difference signal R-Y and the blue difference signal B-Y. of reference phase
The sample values are -RY, -B-Y, R-Y, B-Y at four sample phases of 0°, 90°, 180°, and 270°, and only the color difference signals are separated. It can be taken out in the form. That is, when the carrier color signal is sampled at a frequency of 4fsc with such a sampling phase, the sampled values themselves become ±R-Y and ±B-Y, and the two color difference signals are separated and each line has 455 It will have pixels.

Here, if the number of pixels in one line can be reduced, the memory capacity will be smaller, the circuit scale will be smaller, and the sampling frequency will be lower, so the device speed can be lowered, which is overall advantageous.

The color difference signal has a bandwidth of 500kHz, and according to the sampling theorem, it must be sampled at a frequency of 1MHz or higher. The sampling frequency is fs, the horizontal frequency is
If fh is the number of pixels in one line, M=fs/fh>63 (1). This equation (1) means that for a color difference signal having a band of 500 kHz, the number of pixels in one line should be 63 or more.

As mentioned above, when the carrier color signal of an NTSC color television signal is sampled at a frequency of 4 fsc and at a predetermined phase, the color difference signals of the red difference signal R-Y and the blue difference signal B-Y are You can get 455 of each.

If one out of these 455 pixels is sampled at a rate of 1 out of every N, the obtained number M of pixels is M=455/N (2). For ease of processing, M is preferably an integer, and from equation (2) and equation (1) above, N and M are: When N=1, M=455 When N=5, M =91 When N=7, M=65...(3) There are three cases, but when N=1, the number of pixels is not compressed in any way and there is no meaning. 1 when N=7
The number of pixels M in the line is 65, but this is sampling at the very edge of the Nyquist rate, and the filter (low-pass filter) after DA conversion is too severe to be practical.

In the end, it is appropriate that the number of pixels in one line is 91 when N=5. This is equivalent to sampling each color difference signal using equation (1): fs=91×2/455fsc=2/5fsc≈1.43MHz (4). In other words, the sampling frequency for the carrier color signal may be set to 4/5 fsc.

Next, let's talk about the phase of this 4/5fsc sampling pulse.

What is shown in Fig. 4A is the result when the carrier color signal C is sampled with a 4fsc sampling pulse at sampling phases of 0°, 90°, 180°, 270°, etc. with respect to the burst reference phase. , indicates the sample value, −RY,
-B-Y, R-Y, B-Y, . . . two color difference signals are sequentially separated and obtained. In this example, the phase of the 4/5fsc sampling pulse is shown in Figure 4B.
The phase is as shown in . In other words, the phase is such that one out of every five sampled values is sampled as shown in A in the figure.

Sampling pulse Ps supplied to A-D converter 8
is selected as described above, the A-D converter 8 outputs the red difference signal ± as shown in FIG. 4C.
A signal in which the R-Y and blue color difference signals ±B-Y are obtained alternately with a period of 5/4 fsc is output, and this signal is supplied to the double speed converter 13. This double speed converter 13 is similar to the double speed converter circuit 4 shown in FIG.
1H memories 13a and 13b, and a switch circuit 13 as a write control circuit and a read control circuit.
It consists of c and 13d. switch circuit 13c
and 13d, a horizontal synchronization signal P _H separated by a synchronization separation circuit (not shown) is supplied as a switching control signal. And the switch circuit 13c is 1H
The switch circuit 13d is switched to the memory 13a and 13b side each time, and the switch circuit 13d is switched in the opposite direction.
Furthermore, the memory selected by the switch circuit 13c receives a write clock pulse W _P (shown in FIG. A signal with an output frequency of 4/5fsc is supplied, and
The memory selected by the switch circuit 13d includes:
Read clock pulse R _P with twice the frequency
(shown in FIG. 4D), that is, a signal obtained by multiplying the signal output from the phase adjustment circuit 12 by two by the multiplier 14 is supplied.

Since the double speed converter 13 is configured as described above, the signal shown in FIG. 4C output from the A-D converter 8 is transmitted via the switch circuit 13c
Every 1H, 1H worth of signals are supplied to 1H memories 13a and 13b for writing, and the 1H worth of signals written to the previous 1H from 1H memories 13b and 13a are sent twice in a row with a period of 1/2H. This is read out and output from the switch circuit 13d. That is, the horizontal frequency is doubled by this switch circuit 13d, and the double speed conversion is performed in FIG. 4E.
A signal C′ as shown in is obtained.

This signal C' is supplied to the input side of the switch circuit 15. A control signal P _SW1 having a period of 5/4 fsc as shown in FIG. 4F is supplied to the switch circuit 15 from the non-inverting output terminal Q of the flip-flop circuit 30, and its switching is controlled. In the flip-flop circuit 30, the signal from the multiplier 14 (the fourth
A signal P _R ) shown in Figure D is supplied as a trigger signal to control its state. switch circuit 15
are connected to the output terminals 15a and 15b, respectively, at the high and low levels of the control signal _PSW1 . Therefore, the output terminal 15a receives red color difference signals R-Y and - as shown in FIG. 4G.
A signal _SRY in which R-Y is obtained alternately with a period of 5/4 fsc is obtained, and the output terminal 15b receives blue color difference signals B-Y and -B- as shown in FIG. 4H.
A signal S _BY in which Y is obtained alternately with a period of 5/4 fsc is obtained, and both color difference signals are separated.

The signal _SRY obtained at the output terminal 15a is supplied to one input side of the switch circuit 16. Further, this signal S _RY is converted into an inverted signal _RY as shown in FIG.
is supplied to the other input side of the . The switching of this switch circuit 16 is controlled by a control signal P _SW2 having a period of 5/2 fsc as shown in FIG. 4K. This control signal P _SW2 is formed by supplying the signal P _SW1 (shown in FIG. 4F) obtained at the non-inverting output terminal Q of the flip-flop circuit 30 to the flip-flop circuit 18 as a trigger signal.

This switch circuit 16 has its output side connected to one input side and the other input side at the high level and low level of the control signal P _SW2 , respectively, and outputs the signal S _RY and the inverted signal _RY (fourth From FIGS. G and I), only the positive polarity red difference signals RY are alternately selected in each case, and unipolar red difference signals are successively derived. Therefore, this switch circuit 1
6, a double-speed converted red difference signal R-Y' as shown in FIG.

Further, the signal S _BY obtained at the output terminal 15b is supplied to one input side of the switch circuit 20. Further, this signal S _BY is converted into an inverted signal _BY in the inverting circuit 21 as shown in FIG. This switch circuit 20 receives a control signal P _SW3 as shown in FIG. 4L.
The switching is controlled by. This control signal
P _SW3 is formed by supplying a signal obtained at the inverting output terminal of the flip-flop circuit 30 to the flip-flop circuit 22 as a trigger signal.

This switch circuit 20 has its output side connected to one input side and the other input side at the high level and low level of the control signal P _SW3 , respectively, and outputs the signal S _RY and the inverted signal _SY (fourth From FIGS. H and J), only the positive polarity blue difference signals B-Y are alternately selected, and unipolar blue difference signals are successively derived. Therefore, this switch circuit 2
0, a double-speed converted blue color difference signal B-Y' as shown in FIG.

In the end, in this example as well, the red, green, and blue primary color signals R', G', and B', which have been converted at double speed, are obtained at the output terminals 6a, 6b, and 6c of the matrix circuit 6.

As described above, according to the color demodulation circuit of the present invention, one system of double-speed conversion circuit and a carrier color signal are sampled at a predetermined frequency to generate red difference signals and blue difference signals of positive and negative polarity, respectively. It has a relatively simple configuration that includes a sampling circuit for separating and means for unifying the polarity of the signals by alternately deriving the input signal and output signal of the inverting circuit at a period corresponding to the sampling frequency. A digital color demodulation circuit is obtained that can demodulate a red difference signal and a blue difference signal that have been converted at double speed from the carrier color signal.

As a result, the color demodulation circuit according to the present invention is suitable for use as a color demodulation circuit in a color television receiver that performs double-speed scanning.

Next, FIGS. 5, 6, and 7 show other embodiments of the present invention. These figures 5 and 6
In the figures and FIG. 7, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the case shown in FIG. 5, the polarity of the output of the A-D converter 8 is reversed every two sample values as shown in FIG. Inverting circuit 24 and switch circuit 25 in front
Then, the polarity is unified and the switch circuit 25
-R-Y and - in Fig. 4C are on the output side of
This is done so that B-Y becomes R-Y and B-Y, respectively. And this signal is
After being double-speed converted by the double-speed converter 13, the switch circuit 15 separates the red difference signal RY and the blue difference signal B-Y, and the red color signal is double-speed converted by the D-A converters 19 and 23, respectively A difference signal R-Y' and a blue difference signal B-Y' are obtained.

Furthermore, in the case shown in FIG. 6, the polarity of the signal double-speed converted by the double-speed converter 13 is reversed every two sample values as shown in FIG. 4E.
The polarities are unified by the inverting circuit 24 and the switch circuit 25', and -R-Y and -B-Y in FIG. 4E are connected to the output side of the switch circuit 25'.
are made into R-Y and B-Y, respectively. Then, this signal is separated into a red difference signal R-Y and a blue difference signal B-Y by a switch circuit 15, and is then sent to a D-A converter 19 and 2.
3, a red difference signal R-Y' and a blue difference signal B-Y', which have been double-speed converted, are obtained.

Furthermore, the switch circuit 2 shown in FIG.
5', the signal which has been double-speed converted and whose polarity has been unified is supplied to the DA converter 26 and converted into an analog signal. -Y and blue difference signal B-Y, and double-speed converted red difference signal RY' and blue difference signal B-Y' are obtained from analog switches 27 and 28, respectively.

As mentioned above, in these examples in FIGS. 5 to 7, the double speed converted red and blue difference signals R
-Y' and B-Y' are obtained, and the same effect as in the example of FIG. 2 can be obtained. And these fifth
- The example shown in FIG. 7 has the advantage that it can be configured with only one inverting circuit. Furthermore, in the example in Figure 7,
Only one D-A converter is required.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional color signal double speed conversion circuit, FIG. 2 is a block diagram showing an embodiment of a color demodulation circuit according to the present invention, and FIGS. 3 and 4 are respectively blocks according to the present invention. Diagrams for explanation, FIG. 5, FIG. 6, and FIG. 7 are configuration diagrams showing other embodiments of the present invention, respectively. 8 is an A-D converter, 13 is a double speed converter, 15,
16 and 20 are switch circuits, 17 and 21, respectively.
19 and 23 are inverting circuits, respectively, and DA converters 19 and 23, respectively.

Claims (1)

[Claims] 1. A sample for separating a red difference signal and a blue difference signal of positive and negative polarity by sampling a carrier color signal at a frequency that is the quotient of a frequency four times the color subcarrier and a predetermined odd number. a doubling speed conversion circuit including a pair of line memory circuits, a pair of control means for respectively controlling writing and reading to and from the line memory circuits, at least one inverting circuit, and a double speed converting circuit comprising: signal polarity unification means including a switch circuit for time-divisionally deriving input signals and output signals at a period corresponding to the sampling frequency; A color demodulation circuit designed to obtain a difference signal.