JPH0443775A - Signal processor for charge-coupled device - Google Patents

Abstract

PURPOSE:To always obtain excellent noise suppression effect by selecting a changeover means an output terminal of a delay line at a 1st drive frequency to the position of a resistive element and to the position of ground side at a 2nd drive frequency and sampling and extracting a valid signal voltage of a differential amplifier means. CONSTITUTION:A signal charge subjected to photoelectric conversion by an image pickup area 101 is vertically transferred to a horizontal shift register 102 and horizontally transferred and outputted from an output circuit 103. An output signal from the output circuit 103 is fed to a delay line 108 via a buffer circuit 104 and a resistor 105 and its output terminal is selectively connected to ground or a resistor 111 by a switch circuit 109. Then an output signal of a CCD is delayed by the delay line 108 to make a feed through-period of the delay signal and the signal period of the delay signal are made coincident and a level difference of both the periods is obtained by utilizing the reflection of the delay line 108 or the differential amplifier 107. Thus, excellent noise suppression effect is obtained independently of the drive frequency of CCD.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a charge coupled device signal processing device.

[Conventional technology]

In the current television standard system, the frame rate is 30 frames/second, and a charge-coupled image sensor (hereinafter referred to as
(denoted as COD), the horizontal clock rate is determined by this frame rate, the number of scanning lines, and the number of horizontal pixels.In normal operation, the horizontal clock rate is constant, but in recent years, there has been a demand for diversification of images and higher image quality. The frame rate of the image was increased to 60% for slow motion shooting and sequential scanning.
In order to output as fast as one frame per second or to enlarge the time axis of a part of the screen (so-called electronic zoom function),
A method of driving by varying the horizontal clock rate is often used. When driving by changing the horizontal clock rate, the signal processing circuit also needs to operate by changing the sampling rate according to the clock rate.

Figure 4 shows the conventional correlated double sampling method (hereinafter referred to as CD
In FIG. 4, which shows an example of a signal processing circuit that performs noise removal using a signal processing circuit (denoted as S), signal charges photoelectrically converted in an imaging region 101 are vertically transferred to a horizontal shift register 102, and then transferred to an output circuit 103. It is output from Output circuit 1
The output signal of 03 is inputted via a buffer circuit 404 to a clamp circuit 412 composed of a clamp capacitor 405, a switch circuit 408, and a reference voltage source 409. The clamped CCD output signal is sampled and held by a sample and hold circuit 413 including a switch circuit 407 and a hold capacitor 410 via a buffer circuit 406 . Here, the pulses applied to the clamp circuit 412 and the sample and hold circuit 413 are controlled by the pulse generator 411 according to the driving frequency of the CCD.

Next, the operation of the conventional example at a normal frame rate (30 frames/second) will be explained using the time chart shown in FIG. One period of the output signal A of the CCD includes a reset period 201 in which the reset transistor is turned on, and then a feed-through period 202 in which the floating diffusion layer is kept at a constant potential.
, and a signal period 203 in which signal charges are sent from the charge transfer path to the charge detection section. The effective signal voltage is detected as the difference VP between the potential during the feedthrough period 202 and the potential during the signal period 203 in the charge detection section. A clamp pulse D is applied to the clamp circuit 412 during the feedthrough period 202 of each pixel period Tp, and the feedthrough level is clamped to a constant potential Vop. and,
Thereafter, a sample-and-hold pulse E is applied to the signal period 203, and the effective signal voltage VP is sampled and held by an operation of 0 or more, so that the difference in potential between the feed-through period 202 and the signal period 203 can be taken out as the effective signal voltage VP. At the same time, the W sound component superimposed during the rainy period can be removed.

Next, the operation at twice the normal frame rate (60 frames/second) will be explained using the time chart shown in FIG. When the frame rate doubles, the horizontal chronograph rate also doubles, so it is clamped at twice the frequency (period 1/2, TP) in the clamp circuit 412, and then the effective signal voltage ■, are sampled and held at the same period (1/2·Tp>).

[Problem to be solved by the invention]

In the signal processing circuit that performs noise removal using the conventional CDS method described above, an effective signal voltage is extracted by a clamp operation and a sample-hold operation. In clamp operation, the feedthrough level must be clamped to a constant potential VcP within the application time of the clamp pulse. Therefore, as the signal period becomes faster and the signal period becomes shorter, the clamp time constant must be reduced (that is, hard clamping). )There is a need to. However, if the clamp time constant is made small, the low-frequency attenuation characteristics of the clamp circuit deteriorate, making it impossible to obtain a sufficient suppressing effect on the low-frequency components of output amplifier noise. Therefore, in a signal processing circuit using the CDS method, it is difficult to always obtain a good noise suppression effect regardless of the driving frequency.

An object of the present invention is to provide a signal processing circuit for a charge-coupled device that always exhibits a good noise suppression effect even when the driving frequency is doubled or halved.

[Means for Solving the Problems] A charge-coupled device signal processing circuit of the present invention includes a charge-coupled device that outputs a signal having a signal period and a feed-through period corresponding to a drive frequency, and a charge-coupled device that outputs a signal having a signal period and a feedthrough period corresponding to a drive frequency, and a signal processing circuit that suppresses signal delay and reflection. buffer amplification means for impedance matching the signal from the charge-coupled device to the delay line and outputting the signal, and connecting the output end of the delay line to a resistive element side and a ground side whose output end is grounded and impedance matched. and a differential differential that has one input connected to the branch output of the buffer amplification means and the other input connected to the input terminal of the resistive element of the switching means, and outputs a difference signal between both inputs. an amplifying means; and a sampling means connected to an output end of the differential amplifying means and outputting a sampled signal at a predetermined timing; The delay time of the delay line is set so that the signal period of the output signal of the charge-coupled device and the feed-through period of the delayed signal input to the delay line, reflected at the output end, and returned to the input end overlap. , the switching means is configured such that the output end of the delay line is connected to the resistive element side at a first driving frequency, and connected to the ground side at a second driving frequency that is 1/2 of the first driving frequency. , and the effective signal voltage of the differential amplification means is extracted by the sampling means.

[Effect]

In the present invention, by delaying the CCD output signal using a delay line, the feed-through period of the delayed signal and the signal period of the delayed signal are matched, and the potential difference during the rainy period is reflected by the delay line or by using a differential amplifier. and ask. Therefore, a good noise suppression effect can be obtained regardless of the driving frequency of the CCD without any clamping operation.

Furthermore, since two types of delay times, τ and 2τ (τ: delay time of the delay line) can be obtained using one delay line, it is possible to adapt to two drive frequencies with a relatively simple circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a signal processing device for a charge-coupled image sensor according to the present invention. In FIG. 1, signal charges photoelectrically converted in an imaging region 101 are vertically transferred to a horizontal shift register 102 and then horizontally transferred to an output circuit 1.
Output from 03. The output signal of the output circuit 103 is supplied to the delay line 1o8 via a buffer circuit 104 and a resistor 105. Further, the output terminal of the delay line is selectively connected to the ground or a grounded resistor 111 by the switch circuit 109. Here, the impedance of each resistor 105, 11.1 is equal to the characteristic impedance of the delay line 108, and the voltage appearing at the input end of the delay line is equal to the characteristic impedance of the buffer circuit 106.
The voltage at the input terminal of the resistor 111 is input to the negative input terminal of the differential amplifier 107 via the buffer circuit 110 (signal S3). The effective signal voltage v5 of the output signal S5 of the differential amplifier 107 is sampled by a sampling circuit 112 controlled by a pulse generator 113.

Next, the operation of this embodiment when the CCD is operated at a frame rate of 30 frames/second and 60 frames/second, for example, will be explained using the time charts of FIGS. 2 and 3.

FIG. 2 shows a case where the delay line 108 is operated at 30 frames/second, and the output end of the delay line 108 is grounded via a switch circuit 109. The output signal of the buffer circuit 104 is input to the delay line 108 via the resistor 105 (
The signal S1) reaches the output terminal after being delayed by the delay time τ. Here, the output terminal is grounded via the switch circuit 109, so the signal that reaches the output terminal has its phase reversed, is reflected (total reflection), and is delayed again by the delay time τ before reaching the input terminal (signal S2), where the total delay time 2
τ is set so that the signal period 203 of the input signal S1 of the delay line 108 and the feed-through period 202 of the signal S2 reflected and reaching the input terminal again overlap (that is, about half of one pixel period: 2τ=1/2・Tp). A signal obtained by mixing the signals S1 and S2 appears at the input end of the delay line 108, and is input to the positive input terminal of the differential amplifier 107 via the buffer circuit 106 (signal S3).
Here, the negative input terminal of the differential amplifier 107 is at ground level. Then, the sampling circuit 112 receives a sampling pulse from the pulse generator 113 with one pixel period T.
The effective signal voltage Vs of the output signal S3 of the differential amplifier 107 is sampled.

FIG. 3 shows a case where the delay line 108 is operated at 60 frames/second, and the output end of the delay line 108 is connected via a switch circuit 109 to a resistor 111 whose characteristic impedance is equal to the characteristic impedance of the delay line 108. Here, since impedance matching is perfectly achieved at the output end, no reflection occurs at all, and a signal obtained by delaying the signal S1 input to the delay line 108 by the delay time τ appears at the output end.

Therefore, no reflected wave from the output end occurs at the input end of the delay line 106, and the output signal from the CCD remains unchanged!
appear. Then, the input signal S1 of the delay line 108
is input to the positive input terminal of the differential amplifier 107 (signal S
3) The signal delayed by the delay time τ by the delay line 108 is input to the negative input terminal of the differential amplifier 107 (signal S4), where the frame rate is doubled to 30 frames/second. Therefore, one pixel period of the CCD output signal is 1/2 of that in the case of 30 frames/second.
・Becomes TP. Therefore, the delay time τ of the delay line 108 is half of one pixel period 1/2·Tp in this case (that is, τ = 1/4·Tp), so the feed-through period 202 of the delayed signal S4 is equal to the input signal S3. signal period 20
Next, the difference between the input signal S3 and the delayed signal S4 is taken by the differential amplifier 107, and the effective signal voltage Vs is obtained in the output signal S5 during the period in which the feedthrough period 202 and the signal period 203 overlap. appears every pixel period and is sampled by the sampling circuit 112.

By the above operation, the potential difference between the feedthrough period and the signal period, which are the effective signal voltages of the CCD, is superimposed on the rain period at two drive frequencies with frame rates of 30 frames/second and 60 frames/second, respectively. Sampling can be performed while removing noise components.

〔Effect of the invention〕

As described above, according to the present invention, the potential difference between the feedthrough period and the signal period can be determined using a simple circuit including a delay line and a differential amplifier without a clamp operation. Therefore, regardless of the driving frequency of the CCD, it is possible to sufficiently remove noise components and accurately sample only the effective signal voltage.

Furthermore, according to the present invention, calculations can be performed by setting the delay time of the delayed signal to the delay time τ of the delay line and the delay time 2τ, which is twice the delay time τ of the delay line. Good noise suppression corresponding to the driving frequencies of two CCDs having a relationship of 2 is possible.

In addition, in this example, the frame rate is 3o frames/
Although operation at a drive frequency corresponding to 60 frames/second is shown, it is possible to adapt to any drive frequency by changing the setting of the delay time of the delay line. Also, 1
It is also possible to adapt to changing the drive frequency by doubling or halving it in any period within the horizontal scanning period (=IH).

[Brief explanation of drawings]

Fig. 1 is a configuration diagram showing one embodiment of the present invention, Fig. 2, Fig. 3
The figures are a time chart for explaining the operation of the embodiment shown in Fig. 1, Fig. 4 is a configuration diagram showing a conventional signal processing circuit, and Fig. 5 is a block diagram showing the conventional signal processing circuit.
6 are time charts for explaining the operation of the conventional example shown in FIG. 4. 101... Imaging area, 102... Horizontal shift register, 103, , output circuit, 104, 106 110
．． 404,406...Buffer amplifier, 105°11
1...Resistor, 107...Differential amplifier, 108...
Delay line, 109.407.408...Switch circuit, 112...Sampling circuit, 113°41
DESCRIPTION OF SYMBOLS 1... Pulse generator, 405, 407... Capacitor, 409... Reference voltage source, 412... Clamp circuit, 413... Sample hold circuit.

Claims (1)

[Claims] A charge-coupled device that outputs a signal having a signal period and a feed-through period corresponding to a driving frequency, a delay line that delays and reflects the signal, and impedance matching of the signal from the charge-coupled device to the delay line. buffer amplification means for outputting; switching means for switching and connecting the output end of the delay line between a resistor element side whose output end is grounded and whose impedance is matched and a ground side; and one input to a branch output of the buffer amplification means. differential amplification means that is connected to the output terminal of the differential amplification means and whose other input is connected to the input end of the resistance element of the switching means and outputs a difference signal between both inputs; sampling means for outputting a signal, the signal period of the output signal of the charge coupled device via the buffer amplification means and the output terminal input to the delay line with respect to the first driving frequency of the charge coupled device The delay time of the delay line is set so that the feed-through period of the delayed signal reflected by and returned to the input end overlaps, and at the first drive frequency, the output end of the delay line is connected to the resistive element side. , the switching means is switched so as to be connected to a ground side at a second drive frequency that is 1/2 of the first drive frequency, and the effective signal voltage of the differential amplification means is extracted by the sampling means. Features of a charge-coupled device signal processing device.