JPH044340U - - Google Patents
Info
- Publication number
- JPH044340U JPH044340U JP4212490U JP4212490U JPH044340U JP H044340 U JPH044340 U JP H044340U JP 4212490 U JP4212490 U JP 4212490U JP 4212490 U JP4212490 U JP 4212490U JP H044340 U JPH044340 U JP H044340U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- information processing
- processing device
- processing devices
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims description 16
- 238000012790 confirmation Methods 0.000 claims description 4
- 230000006854 communication Effects 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 claims 1
- 230000007175 bidirectional communication Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Description
第１図はこの考案の一実施例によるデジタル情
報処理装置の構成図、第２図は従来のデジタル情
報処理装置の構成図である。
１は双方向データバス、２は主系情報処理装置
、３は冗長系情報処理装置、４ａ及び４ｂはデー
タ交信回路、５ａは情報処理回路、５ｂは冗長系
情報処理回路、６は故障検出回路、７は入出力停
止回路、８は冗長系起動用デイスクリート信号線
、９は冗長系起動回路、１０はセンサー情報処理
回路、１１ａ及び１１ｂは同期回路、１２ａ及び
１２ｂは自系正常動作確認回路、１３ａ及び１３
ｂは冗長系入出力抑止回路、１４ａ及び１４ｂは
全入出力停止回路、１５ａ及び１５ｂは主系交換
回路である。なお、図中、同一符号は同一または
相当部分を示す。
FIG. 1 is a block diagram of a digital information processing apparatus according to an embodiment of this invention, and FIG. 2 is a block diagram of a conventional digital information processing apparatus. 1 is a bidirectional data bus, 2 is a main information processing device, 3 is a redundant information processing device, 4a and 4b are data communication circuits, 5a is an information processing circuit, 5b is a redundant information processing circuit, 6 is a failure detection circuit , 7 is an input/output stop circuit, 8 is a discrete signal line for redundant system startup, 9 is a redundant system startup circuit, 10 is a sensor information processing circuit, 11a and 11b are synchronization circuits, 12a and 12b are self-system normal operation confirmation circuits , 13a and 13
b is a redundant system input/output suppression circuit, 14a and 14b are all input/output stop circuits, and 15a and 15b are main system switching circuits. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
理装置間並びに単数あるいは複数台のセンサとの
間で、データの交信を行う回路と、上記データ交
信回路を用いたデータ交信により、複数台の情報
処理装置の同期をとる回路と、上記データ交信回
路を用いて各情報処理装置からの出力を比較し、
主系情報処理装置と自系情報処理装置の正常動作
を確認する回路と、上記動作確認回路により正常
と確認された情報処理装置の内、一系のみを主系
とし、それ以外の冗長系の情報処理装置からの上
記の同期及び動作確認の為のデータ交信以外の入
出力を抑止する回路と、上記動作確認回路により
自系を異常と判断した場合、自系の入出力をせべ
て抑止する回路と、予め定められた間隔で主系を
交換する回路とを有することを特徴としたデジタ
ル情報処理装置。 A circuit that communicates data between three or more information processing devices and one or more sensors using a bidirectional communication means, and a circuit that communicates data between three or more information processing devices and one or more sensors; Compare the output from each information processing device using a circuit for synchronizing the information processing devices and the data communication circuit,
A circuit that confirms the normal operation of the main information processing device and its own information processing device, and of the information processing devices that are confirmed to be normal by the above operation confirmation circuit, only one system is designated as the main system, and the other redundant systems are A circuit that suppresses input/output other than the data communication for synchronization and operation confirmation from the information processing device, and a circuit that suppresses input/output of the own system if it is determined that the own system is abnormal by the above operation confirmation circuit. What is claimed is: 1. A digital information processing device comprising: a circuit for exchanging the main system at predetermined intervals; and a circuit for exchanging the main system at predetermined intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4212490U JPH044340U (en) | 1990-04-20 | 1990-04-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4212490U JPH044340U (en) | 1990-04-20 | 1990-04-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH044340U true JPH044340U (en) | 1992-01-16 |
Family
ID=31553390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4212490U Pending JPH044340U (en) | 1990-04-20 | 1990-04-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH044340U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0447622U (en) * | 1990-08-24 | 1992-04-22 |
-
1990
- 1990-04-20 JP JP4212490U patent/JPH044340U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0447622U (en) * | 1990-08-24 | 1992-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB1108540A (en) | Process back-up system | |
| JPH044340U (en) | ||
| JP2528225Y2 (en) | Electronic interlocking device | |
| JPH0755179Y2 (en) | Parallel multiple electronic interlocking device | |
| KR100202398B1 (en) | Isdn device control system having duplication structure | |
| JPS6073753A (en) | Runaway processing system of microprocessor | |
| JPH08206Y2 (en) | Parallel multiple electronic interlocking device | |
| JPH037177B2 (en) | ||
| JPH11143846A (en) | Connection system for information processor | |
| JP2519298B2 (en) | Data transmission equipment | |
| JPH04304737A (en) | Fail safe method for multiplex transmission method | |
| JPS57150058A (en) | Information processing system | |
| JP2592676B2 (en) | System switching method | |
| JPS616755A (en) | Data transfer system | |
| JPH04137144A (en) | Data processor | |
| JPH0588926A (en) | Automatic switching circuit for monitor and control system | |
| JPS62182960A (en) | Detecting device for connection of input/output control device | |
| JPH0320780B2 (en) | ||
| JPH03220935A (en) | Duplicate switching control system | |
| JPH033043A (en) | Semiconductor device | |
| JPH0795282B2 (en) | Duplex microprocessor automatic switching device | |
| JPH0256662A (en) | Memory protecting system | |
| JPS63296428A (en) | Input/output bus control system | |
| JPH05298136A (en) | Method for starting redundant information system | |
| JPH02287836A (en) | Duplex alarm control system |