JPH0442959A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to reduce the coupling in an AC manner of elements through the parasitic capacity of each element to a substrate by a method wherein a substrate potential feeding impedance from the surface of a semiconductor chip is remarkedly reduced. CONSTITUTION:U-shaped grooves are cut in the peripheries of n-p-n transistors 108 and 109 and a diffusion resistance region 111, polysilicon 105 is buried in the grooves as an insulator and the sidewalls of element regions are respectively isolated from each other. A p<+> element region isolation layer 112, which encircles the periphery of each element region consisting of the transistors 108 and 109 and the region 111, reaches from the surface of a semiconductor chip to a p<-> silicon substrate 101 and in which an impurity of a conductivity type identical with that of the substrate 101 is introduced in a high concentration, is formed. It becomes possible to feed a substrate potential to the vicinities of the peripheries of the element regions 108, 109 and 11 in a low impedance and as a high impedance RH of the substrate 101 becomes that only of the part directly under an n<+> buried layer 102, an overall substrate potential feeding impedance is low.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a semiconductor integrated circuit device in which an insulator is used for sidewall isolation of an element, and an element region and a substrate are separated by a PN junction.

The purpose of this is to lower the impedance of substrate potential supply from the semiconductor chip surface, thereby reducing alternating current coupling between each element region and the substrate through parasitic capacitance.

In a semiconductor integrated circuit device in which an insulator is used to separate the side walls of elements constituting an integrated circuit, and each element region and a substrate are separated by a PN junction, each element region is surrounded by a
It reaches the substrate from the surface of the semiconductor chip. An element region isolation layer into which impurities of the same conductivity type as the substrate are introduced at a high concentration is provided, and at least one electrode for supplying a substrate potential is formed in the element region isolation layer.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device.

In semiconductor integrated circuit devices, various structures are used depending on required characteristics.

A structure in which an insulator is used to separate the sidewalls of elements that make up an integrated circuit, such as transistors, capacitors, and resistors, and a PN junction is used to separate the element region from the substrate can reduce the stray capacitance of each element with respect to the substrate. It is used in semiconductor integrated circuit devices that handle high-speed signals.

A semiconductor integrated circuit device according to the present invention is directed to a semiconductor integrated circuit device having a structure in which an insulator is used for sidewall separation of the elements constituting the integrated circuit described above, and the element region and the substrate are separated by a PN junction. .

[Conventional technology]

FIG. 5 is a diagram showing a conventional example of a semiconductor integrated circuit device having a structure in which an insulator is used to separate the side walls of elements constituting the integrated circuit, and the element region and the substrate are separated by a PN junction.

FIG. 3(a) is a plan view, and FIG. 2(b) is an X-Y sectional view.

In FIG. 5, 501 is a P-type silicon substrate.

502 is an n-type buried layer, 503 is an n-type epitaxial layer, 504 is a 5iO1 film, 505 is polysilicon, 50
6 is a p-type base layer 5507 is an n'' emitter layer, 508
is an npn) transistor, 509 is an npnl-transistor, 510 is a p-type diffused resistor, 511 is a diffused resistance region, 51
2, the P′ type part concentration impurity diffusion layer 513 is a SiO2 film,
514 is an aluminum electrode, and 515 is a substrate potential supply electrode.

In this conventional example, npn) transistors 508 and 509
．． Further, a U-groove is dug around the diffused resistance region 511, and polysilicon 505 is buried therein as an insulator to separate the sidewalls of each element region.

Furthermore, the isolation between each element region consisting of the npn) transistors 508 and 509 and the diffused resistance region 511 is
- type silicon substrate 501- (n' type buried layer 502.n-
This is done by reverse biasing the PN junction made of the type epitaxial layer 503). For this purpose, the n-type epitaxial layer 503 is reached from the semiconductor chip surface to the P-type silicon substrate 501. p ° type part concentration impurity diffusion layer 5 into which impurities of the same conductivity type as the substrate are introduced at a high concentration
No. 12 is provided at several locations within the semiconductor chip.

Then, by applying a negative potential to the substrate potential supply electrode 515 made of aluminum provided on the p-type part concentration impurity diffusion layer 512, the P-type silicon substrate 501-(n
"type buried layer 502.n-type epitaxial Ji503)
The PN junction consisting of the transistors 508 and 509 and the diffusion resistance region 511 are isolated from each other by reverse biasing the PN junction consisting of the transistors 508 and 509 .

[Problem to be solved by the invention]

Also shown in FIG. p type high concentration impurity diffusion layer 51
2 impedance Rt, and P-type silicon substrate 5
When the substrate potential supply impedance to the collectors of the npn transistors 508 and 509 is shown in a simple equivalent circuit using an impedance R of 0.01, it becomes as shown in FIG.

Impedance R8 of P type high concentration impurity diffusion N512
is low, but the impedance R□ of the P-type silicon substrate 501 is relatively high. however.

Since the substrate potential is originally a bias for separating the element regions, no direct current flows. Therefore, in the low frequency region, impedance to substrate potential supply does not pose much of a problem.

However, when amplifying a small signal with one high frequency,
When the impedance to the substrate potential supply is high, each element region is coupled in an alternating current manner through parasitic capacitance, which adversely affects the characteristics of the integrated circuit, such as unnecessary oscillation. There was a problem.

The present invention reduces alternating current coupling of each element region to the substrate through parasitic capacitance by lowering the substrate potential supply impedance from the semiconductor chip surface. An object of the present invention is to provide a semiconductor integrated circuit device, particularly a semiconductor integrated circuit device in which an insulator is used for sidewall isolation of elements, and each element region and a substrate are separated by a PN junction.

[Means to solve the problem]

In order to achieve the above objects, the semiconductor integrated circuit device according to the present invention uses an insulator for sidewall separation of elements constituting the integrated circuit, and a semiconductor integrated circuit device in which each element region and the substrate are separated by a PN junction. In a circuit device, it surrounds each element region and reaches the substrate from the surface of the semiconductor chip.

An element region isolation layer into which impurities of the same conductivity type as the substrate are introduced at a high concentration is provided, and at least one electrode for supplying a substrate potential is formed in the element region isolation layer.

[For production]

In the present invention, it surrounds each element region constituting an integrated circuit, such as a transistor, a capacitor, and a resistor, and reaches the substrate from the surface of the semiconductor chip.

An element region isolation layer is provided in which impurities of the same conductivity type as the substrate are introduced at a high concentration. Therefore, it is possible to supply the substrate potential at low impedance to the vicinity of the periphery of each element region, and the high impedance region of the substrate is only the portion immediately below the buried layer.

The overall substrate potential supply impedance decreases dramatically.

As a result, it becomes possible to suppress the influence of the high frequency current flowing from the element region to the substrate on the N region of other elements.

〔Example〕

(First example) FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 3(a) is a plan view, and FIG. 2(b) is an X-Y sectional view.

In FIG. 1, 101 is a p'' type silicon substrate.

102 is an n'' type buried layer, 1o3 is an n'' type epitaxial layer, 104 is a SiO□ film, 1o5 is polysilicon, 10
6 is a P-type base layer, 1o7 is an n-type emitter row L 108
is an npn) transistor, 1o9 is an npn l-transistor, 110 is a P-type diffused resistor, 111 is a diffused resistance region, 1
12 is a P° type element region isolation layer, 113 is a 5i02 film, 1
14 is an aluminum electrode, and 115 is a substrate potential supply electrode.

In this embodiment, npn)-transistors 10B and 10
9. Also, a tJ groove is dug around the diffused resistance region 111,
Polysilicon 105 is embedded therein as an insulator to separate the sidewalls of each element region.

npn transistors 108 and 109. It also surrounds each element region consisting of the diffused resistance region 111 and reaches the P-type silicon substrate 101 from the surface of the semiconductor chip. A p' type element region isolation layer 112 is formed into which impurities of the same conductivity type as the substrate 101 are introduced at a high concentration.

npn transistors 108 and 109. The isolation between each device region consisting of the diffused resistance region 111 and the P-type device region isolation layer 112-P-type silicon substrate 101-(n
This is done by reverse biasing the PN junction consisting of the ``type buried layer 102 and the n-type epitaxial layer 103''.

By applying a negative potential to the substrate potential supply electrode 115 made of aluminum provided on the p-type element region isolation layer 112, the p-type element region isolation layer 112-p-type silicon substrate 101-. (n0 type buried layer 102, n- type epitaxial layer 103) is reverse biased, and npn transistors 108 and 109. In addition, each element region consisting of the diffused resistance region 111 is separated.

It is illustrated in FIG. npn) transistor 108 using the impedance RL of the p-type element region isolation layer 112 and the impedance R of the p-type silicon N plate 10.1.
A simplified equivalent circuit of the substrate potential supply impedance up to the collector of 109 and 109 is as shown in FIG.

The impedance RL of the p-type element region isolation layer 112 is low, but the impedance RH of the p-type silicon substrate 101 is low.
is relatively high. However, in one embodiment, npn)
Transistors 108 and 109 and diffused resistance region 1
11, and reaches the P-type silicon substrate 101 from the surface of the semiconductor chip. Since the p-type element region isolation layer 112 is formed with impurities of the same conductivity type as the substrate 101 introduced at a high concentration, the substrate potential can be supplied to the vicinity of the periphery of each element region 108, 109, and 111 with low impedance. Since the high impedance RH of the P- type silicon substrate 101 is only in the portion directly under the n+ type buried layer 102, the overall substrate potential supply impedance is low.

(Second example) FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 3(a) is a plan view, and FIG. 2(b) is an X-Y sectional view.

In FIG. 3, 301 is a p-type silicon substrate.

302 is an n"-type buried layer, 303 is an n-type epitaxial layer, 304 is a 5i (h film), 305 is a polysilicon layer, 30
6 is a P-type base layer, 307 is an n-type emitter layer, 308
is an npn) transistor, 309 is an npn) transistor, 310 is a p-type diffused resistance, 311 is a diffused resistance region, 31
2 is a P° type element region isolation layer, 313 is a SiO2 film, 3I
4 is an aluminum electrode, and 315 is a substrate potential supply electrode.

In this embodiment, npn transistors 308 and 309
．． Further, a U-groove is dug around the diffused resistance region 311, and polysilicon 305 is buried therein as an insulator to separate the sidewalls of each element region.

npn! - transistors 308 and 309. and a diffusion resistance region 311 surrounding each element region.
- type epitaxial layer 303.

It reaches the p-type silicon substrate 301 from the surface of the semiconductor chip. A p' type element region isolation layer 312 is formed into which impurities of the same conductivity type as the substrate 301 are introduced at a high concentration.

npn) transistors 308 and 309. The isolation between each element region consisting of the diffused resistance region 311 and the p-type element region isolation layer 312 - the P- type silicon substrate 301 - (
n7 type buried layer 302. n-type epitaxial layer 303)
This is done by reverse biasing the PN junction consisting of.

Then, by applying a negative potential to the substrate potential supply electrode 315 made of aluminum provided on the p-type element region isolation layer 312, the p-type element region isolation layer 312-])-
The PN junction consisting of the type silicon substrate 301- (n-type buried layer 302, n- type epitaxial layer 303) is reverse biased to form npn transistors 308 and 309. In addition, each element region consisting of the diffused resistance region 311 is separated.

It is illustrated in FIG. The substrate potential supply impedance to the collectors of the npn transistors 308 and 309 is shown in a simplified equivalent circuit using the impedance RL of the P-type element region separation layer 312 and the impedance RH of the p-type silicon substrate 301, as shown in the first embodiment. Same as Otsuko, 2nd
It will look like the figure.

The impedance RL of the P-type element region isolation layer 312 is low, but the impedance R of the P-type silicon substrate 301 is low.
is relatively high. However, in one embodiment, npn)
Transistors 308 and 309 and diffused resistance region 3
It reaches the P-type silicon substrate 301 from the surface of the semiconductor chip in the n-type epitaxial H3O3 surrounding each element region consisting of 11 elements. A p-type element region isolation layer 3 into which impurities of the same conductivity type as the substrate 301 are introduced at a high concentration.
12 is formed, each element region 308.309
, 311 can be supplied with low impedance to the substrate potential.

High impedance R8ban of P-type silicon substrate 301
Since it is only the portion immediately below the ゛-type buried layer 302, the overall substrate potential supply impedance is low.

(Third example) FIG. 4 is a diagram showing still another embodiment of the present invention.

FIG. 3(a) is a plan view, and FIG. 2(b) is an X-Y sectional view.

In FIG. 4, 401 is a p-type silicon substrate.

402 is an n-type buried layer, 403 is an n-type epitaxial layer, 404 is a 5iOz film, 405 is polysilicon, 40
6 is a P-type base layer, 407 is an n-type emitter layer, 408
is an npn) transistor region, 409 is an npn) transistor, 410 is a p-type element region isolation layer, 411 is a Sin,
The film 412 is an aluminum electrode 2413 is a substrate potential supply electrode.

In this embodiment, trenches are dug around the three npn (npn) transistors, and polysilicon 405 is buried therein as an insulator to isolate the sidewalls of each element region.

It reaches the P-type silicon substrate 401 from the surface of the semiconductor chip into an n-type epitaxial layer 403 surrounding each device region consisting of an npn) transistor region 408 and an npn) transistor region 409. A P' type element region MN410 is formed by doping impurities of the same conductivity type as the substrate 401 at a high concentration.

The separation between each element region consisting of the npn transistor region 408 and the npn transistor 409 is as follows:
Mold embedding layer 402. This is done by reverse biasing the PN junction made of the n-type epitaxial layer 403).

Then, by applying a negative potential to the substrate potential supply electrode 413 made of aluminum provided on the P-type element region isolation layer 410-p-type silicon substrate 401-(n The PN junction consisting of the type buried layer 402 and the n" type epitaxial layer 4°3) is reverse biased to form the npn transistor region 408 and the npn transistor region 408 and the npn
Each element region made up of transistors 409 is isolated.

It is illustrated in FIG. If the substrate potential supply impedance up to the collector of the NPN transistor is shown in a simplified equivalent circuit using the impedance Rt of the P-type element region isolation layer 410 and the impedance R of the P-type silicon substrate 401, it will be the same as in the first embodiment. , as shown in Figure 2.

The impedance RL of the p-type element region isolation layer 410 is low, but the impedance R1 of the p-type silicon substrate 401 is low.
1 is relatively high. However, in the three embodiments, npn
Transistor region 408 and npn transistor 4
An impurity having the same conductivity type as the substrate 401, which reaches the P-type silicon substrate 401 from the surface of the semiconductor chip, is introduced at a high concentration into the n'' type epitaxial layer 403 surrounding each element region consisting of P. type element region isolation layer 4
10 is formed, each element region 408°409
It is possible to supply the substrate potential with low impedance to the vicinity of the periphery of the p-type silicon substrate 401, and the high impedance RM of the p-type silicon substrate 401 is only in the part directly under the n9-type buried layer 402, so the overall torsion plate potential supply impedance is low.

〔Effect of the invention〕

According to the present invention, it is possible to significantly reduce the substrate potential supply impedance from the semiconductor chip surface.
It becomes possible to reduce AC coupling through parasitic capacitance of each element to the substrate. As a result, even when amplifying small signals with two high frequencies, unnecessary oscillations of the integrated circuit and adverse effects on the characteristics can be eliminated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first embodiment. FIG. 2 is a diagram showing a simplified equivalent circuit of the present invention. FIG. 3 is a diagram showing a second embodiment. FIG. 4 is a diagram showing a third embodiment. FIG. 5 is a diagram showing a conventional example. FIG. 6 is a diagram showing a simple equivalent circuit of a conventional example. In Figure 1 101:p-type silicon substrate 102: n” type buried layer 103: n-type epitaxial layer 104: SiO, film 105: Polysilicon 106: P type base layer 107: n” type emitter layer 108: npn transistor 109: npn) transistor 110: p-type diffused resistance 111: Diffusion resistance region 112: P” type element region isolation layer 113: SiO□ film 114 aluminum electrode 115: Substrate potential supply electrode In Figure 3 301: P-type silicon substrate 302: n” type buried layer 303: n-type epitaxial layer 304: SiO□ film 305: Polysilicon 306: p-type base layer 307: n” type emitter layer 308: npn transistor 309: npn) Langimeta 310: p-type diffused resistance 311: Diffused resistance region 312: p” type element region isolation layer 313: SiO□ film 314 aluminum electrode 315: Substrate potential supply electrode In Figure 4 401: p-type silicon substrate 402: n” type buried layer 403: n-type epitaxial layer 404: 5iOz film 405: Polysilicon 406: p-type base layer 407: n' type emitter layer 408: npn transistor area :npn) transistor :p type element region isolation layer : 5i (h membrane aluminum electrode Two-substrate potential supply electrode

Claims (4)

[Claims] (1) In a semiconductor integrated circuit device in which an insulator is used to separate the side walls of the elements constituting the integrated circuit, and each element region and the substrate are separated by a PN junction, the periphery of each element region is surrounded and the surface of the semiconductor chip is The device is characterized by providing an element region isolation layer into which impurities of the same conductivity type as the substrate are introduced at a high concentration and reaching the substrate, and at least one electrode for supplying a substrate potential is formed in the element region isolation layer. Semiconductor integrated circuit device. (2) In a semiconductor integrated circuit device in which sidewall isolation of the elements constituting the integrated circuit is performed by burying an insulator in a U-groove formed around the element, and each element region and the substrate are separated by a PN junction. , an element region isolation layer is provided that surrounds each element region and is doped with impurities of the same conductivity type as the substrate at a high concentration that reaches the substrate from the surface of the semiconductor chip, and in the element region isolation layer,
A semiconductor integrated circuit device comprising at least one electrode for supplying a substrate potential. (3) In a semiconductor integrated circuit device in which sidewall isolation of the elements constituting the integrated circuit is performed by burying an insulator in a U-groove formed around the element, and each element region and the substrate are separated by a PN junction. , an element in which impurities of the same conductivity type as the substrate are introduced at a high concentration into an epitaxial layer grown on the substrate and of the opposite conductivity type to the substrate, surrounding each element region and reaching the substrate from the surface of the semiconductor chip. A semiconductor integrated circuit device, comprising: a region isolation layer; and at least one electrode for supplying a substrate potential formed on the element region isolation layer. (4) In a semiconductor integrated circuit device in which sidewall isolation of the elements constituting the integrated circuit is performed by burying an insulator in a V-groove formed around the element, and each element region and the substrate are separated by a PN junction. , an element in which impurities of the same conductivity type as the substrate are introduced at a high concentration into an epitaxial layer grown on the substrate and of the opposite conductivity type to the substrate, surrounding each element region and reaching the substrate from the surface of the semiconductor chip. A semiconductor integrated circuit device, comprising: a region isolation layer; and at least one electrode for supplying a substrate potential formed on the element region isolation layer.