JPH0442918A - Formation of semiconductor thin film - Google Patents

Abstract

PURPOSE:To control nucleation positions, determine grain boundary positions, and form single-crystal regions of few defects by forming a plurality of micro regions, which act as nucleation points with priority, at predetermined sections of an amorphous thin film and then heat-treating the regions. CONSTITUTION:Nucleated regions are coated with a mask, such as resist, formed on the surface of an amorphous Si laminated layer and Si ions are implanted only into regions not nucleated with energy selected to damage the amorphous Si layer and the section near a base interface. The amorphous Si layer having the Si-ion-implanted interface is heat-treated in N2 or H2. The heat treatment forms nuclei locally. Continuous heat treatment moves a crystal phase to the periphery and an amorphous phase interface outward. That is, the Si atoms in the amorphous material skip the interface and are incorporated in the crystal phase. The Si atoms are incorporated in the single crystal phase, which is produced from the undamaged interface regions before nuclei are formed in the damaged interface regions, by re-arrangement of the component atoms of the damaged interface regions, the crystals are grown in a solid phase, and adjacent crystals collide to form crystal grain boundaries.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a semiconductor i# film that can be applied to a component of a three-dimensional integrated circuit or a large area electronic device.

[Prior Art] One of the methods in the field of crystal formation technology for growing a crystal thin film on an amorphous substrate is a method in which an amorphous X thin film previously formed on a substrate is grown in solid phase by heat treatment at a low temperature below the melting point. is proposed.

For example, a 5ifiJ film formed on amorphous 5i02 and made amorphous by Si ion implantation to a thickness of about 1100 nm is heat-treated at 600°C for several tens of hours in an N2 atmosphere to crystallize the amorphous Si thin film. , the maximum particle size is 5
It has been reported that a polycrystalline thin film with a large dendritic grain size of up to μm is formed. (T, Noguchi,) 1. )I
ayashi & h.

Ohshima, 1987. Materials Re
5earch 5ocietySya+posium
Proceedings vol, 106. “Polys
iliconand Interfaces, p, p
, 293. EIsevier SciencePubl
(Ishing, New York, 1988) The polycrystalline thin film obtained by this method is several hundred times larger than the grain size of conventional thin films that become polycrystalline as they are deposited, making it possible to fabricate high-performance electronic devices. .

For example, the electron mobility of a field-effect transistor was fabricated using a chemical vapor deposition method in which the deposit remains polycrystalline? It operates about 10 times faster than [.

However, the following two problems exist in the thin film obtained by this crystal growth method.

(2) Although the maximum grain size of this solid-phase grown film is large, reaching μm size, its grain size distribution and the position of crystal grain boundaries are not controlled. This is because the crystallization of an amorphous Si thin film is based on the solid phase growth of crystal nuclei randomly generated in the amorphous layer by heat treatment, so the positions of grain boundaries formed by collisions between crystal grains are also disordered. As a result,
This is because the particle sizes are distributed over a wide range.

It is known that a large number of carrier traps are densely packed in grain boundaries, and that barriers are formed there against carrier movement, and the position of grain boundaries depends on the various characteristics of electronic devices fabricated there. have a significant impact on For example, a thin film made amorphous by Si ion implantation is heated to 600°C in N2 at 50°C.
When the particle size distribution of a thin film with a maximum particle size of 5 μm obtained by heat treatment for 0 hours was observed in detail using a transmission electron microscope, it was found to be 1 μm.
Most of them are crystal grains with the following grain sizes, and the grain size is 0.
．． It was found that the size was very widely distributed from 1 μm to 5 μm.

It has been observed that this distribution has a great influence on the various characteristics of the field effect transistors fabricated there, particularly the intra-wafer variations in mobility, threshold value, and subthreshold characteristics. In particular, when the channel length becomes equal to or less than the maximum particle size, this tendency becomes more obvious. This is because the disorder of grain size and grain boundaries deteriorates the uniformity of the number and amount of llmW in the channel. This is an extremely serious problem when building integrated circuits.

(2) The second problem is crystal defects within crystal grains. As mentioned above, solid-phase grown crystals are dendrites, which grow by introducing many twin grain boundaries inside and extending the side rods. Resolution observation revealed that the lattice stripes were fragmented.

Here, according to electron beam diffraction using a low magnification electron microscope, μm
The inside of the large-grain dendrite crystal is a single crystal with a uniform crystal direction as a whole.

It goes without saying that this group of defects within grains is a factor that inhibits carrier movement, and even if a short channel element with a channel length less than the maximum grain size is manufactured, it will never reach the performance of bulk Si.

The present invention solves the two problems of the conventional example, and the purpose of the present invention is to control the nucleation position in the solid phase, determine the grain boundary position, and form a low-defect single crystal region. The purpose of this invention is to provide a method for growing crystals.

[Means for Solving the Problems] The method for forming a semiconductor thin film of the present invention is a crystal growth method in which an amorphous thin film is crystallized by solid phase growth to form a thin film crystal. By forming a plurality of micro regions that will preferentially serve as nucleation points, and then performing a heat treatment, solid-phase growth will occur from the micro regions preferentially from Hayabusa's nuclei, and the position of the grain boundary will be changed. A specified crystalline semiconductor thin film is formed, and then the crystalline semiconductor thin film is heated to 110
It is characterized by reducing intragranular defects by heat treatment at 0°C or higher.

[Action Co. The operation of the present invention will be explained below along with the detailed configuration.

In the present invention, nucleation is generated at any position in an amorphous thin film by heat treatment in the solid phase, and dendrites are grown in the solid phase to determine the grain boundary body tube. 8. Setting of the nucleation region (1) For example, this can be achieved by the following method.

The degree of damage due to ion implantation is smaller in the amorphous thin film than in other regions. By implanting ions of
Nucleation is preferentially performed in the minute regions. Note that this heat treatment may be performed using a conventional heating means such as an electric furnace.

Cedar continues to grow in the solid phase, growing to a μm size while introducing twins, and the crystal end face is brought into contact with an adjacent large-grain dendrite crystal, which has been designed as a starting point for solid phase crystal growth, to form a grain boundary. form and stop growing.

In this way, in step 1), μm-sized crystal grains containing defects are formed at predetermined positions, and the amorphous region is completely crystallized. As a result, a polycrystalline thin film with grain orientation ff1711<determined is formed at a position approximately in the middle of adjacent nucleation regions.9 Also, in order to grow only a single crystal region without forming grain boundaries, The 'fii film may be divided in advance by a grain boundary forming region at a certain point 1]. For example, a Si layer of several microns square is formed, which is smaller than the maximum grain size.

■By the method of ■ above, a large number of defects (twins, micro-twins, dislocations, stacking faults, point defects) whose grain attachment positions or crystal positions are defined t'+ are removed without grain boundary movement and defects inside crystal grains. Heat at a temperature that decreases (above 1200℃)! Fill in A.

In this case, heating below the melting point by incoherent light remains. The reason for this is that it is easier to raise and lower the temperature at high temperatures in a short time compared to a normal electric furnace, and it is possible to use a thin film over a large area compared to beam scanning with coherent light such as a laser. It can be heated selectively.

Furthermore, since incoherent light is used, even if there is a slight distribution in film thickness, uneven heating due to light interference can be prevented, and the entire surface of the light incident surface can be heated uniformly.

In addition, the E-temperature rate is 100 to 500t:/SeC
(Preferably, the heating time is preferably 1 to 3 minutes.) In addition, heating with incoherent light can be performed in an inert atmosphere such as atmospheric pressure, reduced pressure, or pressurized nitrogen gas or inert gas atmosphere. preferable.

(1) Control of nucleation position (in solid phase) Further details of the present invention will be explained below along with the findings obtained in making the present invention.

The key point of the present invention is how to control the growing position of crystals in the solid phase. That is, in an amorphous thin film, nuclei are generated preferentially in a specific position, and nucleation in other areas is controlled.

The present inventor deposited polycrystalline 5ifi on a base material made of a material with a low nucleation density, such as SiO2, and then implanted, for example, Si ions to make the polycrystalline SiN amorphous. During heat treatment, the crystal nucleation temperature (
We discovered that the crystallization temperature strongly depends on the ion implantation energy.

Therefore, we investigated how the crystal nucleation temperature depends on the ion implantation energy and found the following. The details are described below.

When the implantation energy is changed, the Si after becoming amorphous becomes
In the layer (amorphous Si layer), the distribution of the implanted Si ions changes, and as a result, the distribution of the generated vacancies,
That is, the distribution of regions where implantation damage exists changes in the film thickness direction depending on the implantation energy.

In addition, in the amorphous trade, the embryo that is formed by overcoming the surface energy disadvantage roughly grows to produce one nucleus, and then,
A phase transition from an amorphous phase to a crystalline phase of Si atoms occurs.

By the way, there are two types of nucleation: uniform nucleation and heterogeneous nucleation. The former is nucleation in a homogeneous material (for example, inside an amorphous Si film), and whether such nucleation occurs is mainly determined by the surface It depends on whether or not the embryo can become a dog by overcoming the energy disadvantage. On the other hand, in the latter case of heterogeneous nucleation, nucleation is stimulated by contact with foreign matter, and the activation energy of the latter is lower than that of the former, meaning that heterogeneous nucleation occurs more than homogeneous nucleation. In fact, the rate of nucleation in an amorphous Si thin film is mainly determined by heterogeneous nucleation near the underlying interface.

The depth at which the ion implantation dose reaches its maximum (projected range) is
The present inventors have discovered that even under conditions where the injection amount is constant, it has a significant effect on the aforementioned heterogeneous nucleation at the interface.

FIG. 1 shows the correlation between implantation energy and crystallization temperature.

The conditions at this time are as follows. The injection layer is 5i02
This is a polycrystalline Si layer with a thickness of 1100 nm deposited on the substrate by low pressure CVD by decomposition of SiH4 at 620°C, and the implanted ions are SL''.The implanted amount is the critical implanted amount (approx.
” constant over m-2) (in this case 5 x 101
Sc m-2), the implantation energy was 40ke
V to 80keV.
When the layer is turned on) and the implantation amount exceeds the critical implantation dose, the degree of damage in the damaged region becomes continuous in the layer thickness direction and becomes amorphous. This amorphous Si layer was heat treated in a N2 atmosphere at various temperatures for 20 hours, and the recrystallization process in the solid phase was observed mainly using a transmission electron microscope, and the crystallization temperature under the above conditions was investigated.

For example, focus on implant energies of 40 keV and 70 keV. The implantation depths (projected ranges) of 40 keV and 70 key are 55.2 nm and 99.7 nm, respectively, and these correspond to the vicinity of the center of the film thickness and the vicinity of the interface with the underlying material within the 1100 nm layer. There is a difference of more than 50°C in their crystallization temperatures, indicating that the crystallization temperature is higher and it is more difficult to crystallize when implanted near the base interface.This indicates that the damaged area extends to the interface. It is considered that this is because the crystal growth was inhibited due to the large amount of nucleation and, as a result, heterogeneous nucleation. In addition, a layer made amorphous by implanting at 40 keV so that the projected range is near the center of the film thickness, or a layer deposited by CVD that crystallizes within 1 hour (i.e. 600 keV) When the amorphous layer was heat-treated at 70 keV at 70 keV with the implantation depth near the interface, it was confirmed by transmission electron microscopy that this layer did not crystallize even after over 100 hours. . That is, by changing the accelerating voltage of ion implantation, it was possible to form a crystallized region and a non-crystallized region. Figure 2 shows the relationship between the time from heat treatment to the start of crystallization (latent time) and implantation depth (projected range).As shown in Figure 2, the deeper the implantation depth toward the interface, the more The latent time is extended and crystallization is difficult; (projected range)/(film thickness) = 1, that is, the latent time is maximum (1, . . .) and has a maximum point near the interface where the most damage occurs.

From the above, it has been revealed that the crystallization temperature and the latent time differ by changing the implantation energy, and the cause is judged to be the inhibition of heterogeneous nucleation near the interface.

The thickness of the amorphous semiconductor layer is 1. Considering the implantation depth, the necessary implantation energy, and the capacitance of the semiconductor layer itself, it is preferably about 50 nm to 200 nm, more preferably 80 nm to 150 nm, and most preferably 80 nm to 120 nm.
It is m.

The nucleation position is controlled using the above phenomenon.

As shown in FIG. 3(A), a mask such as a resist is used on the surface of the amorphous Si deposited layer to cover the fII region where nucleation is to occur, and Si ions are applied to the amorphous S
The implantation energy is selected and implanted so that the vicinity of the interface between the first layer and the underlying layer is damaged.

Damage is caused mainly near the interface in areas not masked by the resist, and re-nucleation during subsequent heat treatment is inhibited.

Area with high degree of implantation damage (hereinafter referred to as interface damage area)
The temperature and time at which the silicon does not crystallize and the region with a low degree of implantation damage or no implantation damage (hereinafter referred to as non-interface damage region) crystallizes is determined from Figures 1 and 2, and Si The ion-implanted amorphous Si layer is heated with N2 or N
Heat treatment in 2. Nuclei are generated locally by such heat treatment. For amorphous Si [500°C to 700°C for 10 to 200 hours, more preferably 550°C to 65°C
50 hours to ioo hours at 0°C, optimally 580°C P62
Heat treatment at 0°C for about 70 to 100 hours is appropriate.

If the non-interface damage region is set to a microscopic surface f [(area of 5 pm or less in diameter, preferably 2 μm (diameter) or less, optimally 1 μm (diameter) or less), nuclei will be generated early from the micro region when heat treatment is started. However, this is preferable because a single crystal grows (FIG. 3(B)). As shown in FIG. 3(C), when this crystalline phase having a single domain is continued to undergo heat treatment, the interface between the crystalline phase and the amorphous phase moves outward. That is, Si atoms in the amorphous state jump across the interface and are incorporated into the crystalline phase. In this way, the mass of crystals continues to increase, but this phase transition from amorphous to crystalline phase is
Surface energy occurs at lower energies than those for unfavorable nucleation. Therefore, in the phase transition, before nucleation occurs in the interfacially damaged region, the falcon crystal phase generated from the non-interfacially damaged region is absorbed by the rearrangement of the atoms constituting the interfacially damaged region, and the solid phase transition occurs. Crystals grow, and most importantly, adjacent crystal masses collide, forming grain boundaries there.

At this time, the crystal grain size becomes approximately equal to the interval between non-interface damage groups (nucleation regions), and the desired crystal grain size can be determined, as well as the grain boundary position. The spacing between the nucleation regions is preferably 1. < is 11zm to 10μm, more preferably 2μm to 8μm, optimally 3μm to 5μm.

Note that the amorphous thin film in the present invention is not limited to one formed by amorphizing a polycrystalline thin film by ion implantation into the polycrystalline thin film, but may also be one that already has an amorphous structure at the time of deposition. .

When the starting material is a polycrystalline layer, in order to make it amorphous, the first ion implantation is performed without providing a mask so that the projected range is near the center of the polycrystalline thin film. By such ion implantation, the polycrystalline thin film can be made amorphous without causing implantation damage near the interface between the polycrystalline thin film and the underlying material. When forming a thin film with an amorphous structure during deposition, the first ion implantation described above may be omitted. Next, a second ion implantation is performed with a mask made of, for example, resist provided in a portion corresponding to the minute region so that the projected range is near the interface between the amorphous thin film and the underlying substrate.

Such ion implantation causes implantation damage near the interface between the amorphous thin film and the underlying substrate in areas other than the portion where the mask is provided, and can prevent heterogeneous nucleation near the interface. In a region where no implantation damage occurs (non-interface damage region), heterogeneous nucleation tends to occur near the interface, and this region becomes the nucleation region.

In the above method, ion implantation is performed twice, but by appropriately selecting the material and thickness of the mask, the projection range in the part corresponding to the minute area can be made to be near the center of the thin film, while the projection range in other parts can be The projected range is 1. Formation of a minute region with a small degree of implantation damage and making the polycrystalline thin film amorphous because the projection range is near the interface between the amorphous thin film or polycrystalline thin film and the underlying substrate. This can be done by multiple ion implantations.

It is desirable that such a mask be made of a material that transmits the ions to be implanted, and examples thereof include inorganic materials such as silicon oxide and silicon didide.

(2) Heat treatment for defect reduction The present inventor observed the crystal structure of a large number of samples using a transmission electron microscope when irradiating amorphous Si with incoherent light from a lamp. During my visit, I obtained the following important findings.

■ Directly irradiate amorphous Si with tungsten halogen lamp light (wavelength 0.5 = 3.5 μm), heat up time 10 seconds to 6
When heated for 1 to 3 minutes at temperatures above 1100°C and below the melting point for 0 seconds, crystallization occurs, forming a polycrystalline thin film with a grain size of submicron (<1 μm). It was found that there were so few defects that interference fringes (bend contours) observed using a transmission electron microscope were observed only when the bending was applied.

■Amorphous Si is heat-treated in an electric furnace at 600'e for 10 to 100 hours to grow solid-phase growth, to grow micron-sized (>1 μm) large-grain dendrites, and then It was confirmed that crystal defects (stacking faults, microtwins, dislocations) within grains were drastically reduced when irradiated with incoherent light from a lamp at a certain temperature, similar to the case (2).

Furthermore, this case was characterized in that no movement of grain boundaries was observed.

It was also found that as the temperature was increased to 1300° C. and 1400° C. (heating time 3 mln in each case) for both (1) and (2), the amount of defects decreased.

These phenomena can be understood as follows.

In the case of ■, the temperature of the amorphous t-layer suddenly reaches 1100℃ in 10 seconds.
As a result of the above heating, the nucleation temperature in the solid phase is higher than in case (2), and the grain size determined by the grain boundaries formed by collisions between growth-sized grains becomes minute, less than 1 μm, and defects It is determined that the defect moves and disappears using the reduction in free energy as the driving force. Incidentally, at this time, grain growth also occurs due to the driving force of grain boundary energy decrease.

In case (2), as mentioned above, the nucleation rate in the solid phase is limited to a low level due to low-temperature annealing (for example, below 700°C).
After heat treatment for 0 hours or more, large-grain dendritic polycrystals grow (with a grain size of 1 micron or more), and then irradiated with lamp light and heated to a temperature of 1100°C or more and below the melting point, which drives the defect energy reduction. As a result, the defect group moves and disappears.

However, since the grain size is as large as 1 μm or more, the grain boundary energy state is lower than in case (2), and grain growth accompanied by movement of grain boundaries does not occur.

The irradiation intensity of the incoherent light used in the present invention is an intensity that can raise the temperature of the semiconductor thin film at a heating rate within the above-mentioned range, preferably 0. 1 W/cm2 or more is desirable.

A transistor (P-channel field effect transistor) was fabricated on the Si thin film produced in this manner and changed to have a large area uniform crystal structure. FIG. 4 shows the relationship between hole carrier mobility and subthreshold characteristics with respect to lamp heating temperature.

First, the results of fabricating a MOS transistor in the sample (2), that is, amorphous Si subjected to high-temperature treatment by direct lamp heating, are plotted with black circles (.).

The hole carrier mobility hardly changes until heat treatment at 1100°C and remains below 10 cm"/V-sec, but 12
When heat treated at 00°C or higher, the mobility suddenly increases to exceed 10cm27V-see. The subthreshold coefficient is 1000 mV/decade or more, which is so poor that it is not even shown in this graph.

Sample (2), that is, amorphous isi, is grown in solid phase at a low temperature,
A field effect transistor (IIIO5FET) was fabricated using a lamp irradiated after increasing the grain size to 1 μm or more. The resulting changes in hole carrier mobility are shown in white circles (O).
, the change in the subthreshold coefficient is indicated by a triangle (Δ).

Even in a transistor grown in a low-temperature solid phase before lamp irradiation, the carrier mobility is already 40 cm2/V-s.
It exceeded ec, and there was a gradual improvement up to 1100°C, and it became 58cm2/■·sec.

Furthermore, its properties were rapidly improved by light irradiation heating above 1100℃, and at 1300℃ it was 140cm2/V-sec.
As a result, its characteristics are dramatically improved. This improvement is 1
It has also been found that this phenomenon is particularly significant at temperatures above 200°C. At the same time, the subthreshold characteristic is 700 m up to 1100°C.
V/decade or higher, and a decrease begins with heat treatment at 1100°C or higher, and a particularly remarkable improvement is observed at 1200°C or higher.

To summarize the above, heat treatment is performed in the solid phase at low temperature before lamp light irradiation, and after grain size expansion, heat treatment with a lamp at 1100°C or more, preferably 1200°C or more, is carried out in Dev.
It was found to be effective for improving ice characteristics.

Furthermore, in lamp heating, the rate of temperature increase is fast, so the temperature reaches 1100° C. or higher in a very short time (several seconds), and the temperature decreases extremely quickly. Furthermore, selective heating of only the Si layer is also possible by selecting the wavelength. When the absorption wavelength of Sl is changed from 300 nm to 11 tm, the absorption depth changes to 10 nm or 61007,+ m. 800nm to 900n to heat only the surface layer
It is recommended to use a Xe (xenon) lamp with an emission wavelength spectral peak between m. In these two respects, it is advantageous over commonly used electric furnaces. In particular, it is difficult to heat at a temperature increase rate of 1100° C. or more in a few seconds using a normal electric furnace. Furthermore, according to the present invention, it is possible to form a semiconductor thin film in which nuclei are generated at desired positions and the grain size and position of grain boundaries are controlled. Therefore, it is possible to obtain a device having characteristics equivalent to those of a device fabricated on a single crystal semiconductor substrate.

Below, the threshold values ( The dispersion of Vth) is shown in Table 1, and the IR below shows the carrier mobility (μ), which is an index of the operational performance of the transistor.

Sample B in Table 1 shows a transistor manufactured by performing lamp heating at 1350° C. after grain boundary position control, and sample C shows a transistor manufactured on a bulk Si wafer. Channel lengths (L) of 10 μm and 3 μm are appropriate. The grain boundary spacing was designed to be 5 μm (sample B).

In sample B, in which the grain boundary position is not controlled, the dispersion σ is larger in the short channel, and in sample B, in which the grain boundary position is controlled, the dispersion σ is smaller in the short channel, and the carrier mobility is increased.

As described above, high-temperature heat is applied to large-grain dendritic polycrystals with controlled grain boundary positions! By performing A filling to reduce defects, uniformity improves and high performance is achieved. This effect is extremely important when building integrated circuits.

[Example] (Example 1) 0 thermally oxidized s i 02 m on a 4-inch Si wafer
．． 1 μm thick and then deposited an amorphous S1 film with a thickness of 1100 nm on top of it using the normal low pressure CVD method.At this time, SiH4 was used as the source gas, and the temperature was 550°C and the pressure was 0.
．． It was formed at 3 Torr.

Thereafter, a resist was applied, and resist with a diameter of 1 μm was left in the form of lattice points at intervals of 5 μm using a normal lithography technique.

Using this resist as a mask, Si” ions were applied at 70 keV.
It was injected all over. The injection amount is 3 x 1015 cm"" and 1 no. At an implantation energy of 70 keV, its projected range comes close to the 3102 glass interface of the underlying material such as ionm Si. This caused damage to the interface (Si/5iO2) in all areas other than the 1 μm diameter resist.

1 Nozist! ! Terrorism in N2 atmosphere after releasing J 30
t: Heat treatment was performed using an electric furnace for 80 hours to grow crystals in a solid phase. After that, as a result of observation with a transmission electron microscope, the grain boundaries were found to be 5 μm, which corresponds to the initial pattern spacing.
The particles were arranged at m intervals, and the particle size distribution was within ±1 μm with respect to an average of 5 μm.

Further, the atmosphere was N2. Further, in order to prevent surface roughening during irradiation, a 50 nm thick 5iO2 layer was formed as a cap on the surface of the Si thin film by sputtering.

Furthermore, a tungsten halogen lamp was installed at 110°C from both sides.
Six samples were formed that were irradiated for 3 minutes at 0°C, 1350°C, and 1400°C. In addition, the heating rate is 200℃/s
It was set as ec. Thereafter, a polysilicon gate P-channel field effect transistor was fabricated on a 4-inch wafer using an IC process. Channel length is 10μm and 3μm
It was m.

As a result, an excellent transistor with high carrier mobility and low threshold dispersion was obtained.

Furthermore, similar effects were obtained even when the heat treatment in the N2 atmosphere was changed to the heat treatment in the N2 atmosphere.

(Example 2) A polycrystalline Si thin film with a density of 1100 nm was deposited on a base material made of plate-shaped glass by thermally decomposing SiH4 using a low pressure chemical vapor phase method.
n deposited. Formation temperature is 620℃, pressure 0.3Torr
The particle size was fine, about 50 nm.

Si injection was performed twice. First, we first implanted a 3×10”c film with an energy of 40 keV on the entire surface without a resist mask.
Si ions were implanted into the polycrystalline Si layer at an implantation dose of m-', and the vacancies caused by knock-on atoms caused by the ion implantation became continuous and became amorphous. However, the projected range of 40keV is located near the center of the film thickness of 1100n, and as a result, there is almost no damage near the Si/5in2 base interface.

Thereafter, as in Example 1, a resist mask was provided in the form of lattice points with a diameter of 1 μm and an interval of 5 μm, and a second St'' ion implantation was performed, this time at 70 keV, to introduce damage near the interface. After the resist was removed, it was heat-treated in N at 620°C for 100 hours. As a result, the grain size was 5 μm ± 1 μm as in Example 1, and the grain boundaries were aligned in a lattice pattern. Ta.

Furthermore, after coating the Si thin film with grain boundary position control with a sputtered 5ift film of 50 nm, a Si wafer was brought into contact with the top of the film as a light absorber, and tungsten halogen lamp light was irradiated at 1100°C, 1200°C, 1300°C.
Five samples were formed at 1350°C and 1400°C for 3 minutes. In addition, the temperature increase rate is 200℃/s
c I did it. In addition, the atmosphere was N.

After removing the cap Sin, a field effect transistor was manufactured in the same manner as in Example 1, and a transistor with good characteristics was obtained.

(Example 3) Amorphous Si was deposited to a thickness of 1100 nm on a quartz substrate as a base material by electron beam evaporation in an ultra-high vacuum under the conditions shown below.

Ultimate vacuum level lXl0-”Torr Vacuum level during deposition
5×10-”Torr Substrate temperature: 150°C Deposition rate: ~100 nm/hr On this amorphous Si thin film, resist was applied using a normal photolithography process so that 1 μm square areas remained in the form of lattice points with 5 μm intervals. I buttered it.

Furthermore, Si + ions accelerated to an energy of 70 keV were implanted into the entire substrate at an implantation dose of 1×101101 s. In this case, since the projected range of Si ions in Si is 99.7 nm, The largest number of Si ions are distributed near the interface between the amorphous Si thin film and the quartz substrate in a region not covered by the resist, and a large amount of damage is introduced at the interface.

After removing the resist, the substrate temperature was increased to 59°C in an N2 atmosphere.
Heat treatment was performed while maintaining the temperature at 0°C. Fifteen hours after the start of the heat treatment, crystal nuclei began to be generated in a 1 μm square area where the second Sf ions were not implanted. At this point, no nucleation has occurred in the region not covered with resist and implanted with Si ions, so if annealing is continued further, 1μ
The crystal nuclei that had already been formed in the m-square region grew laterally beyond that region, forming dendritic large-grain thin film crystals. After annealing for 120 hours, the growth end face came into contact with a crystal grain grown from an adjacent region about 5 μm apart to form a grain boundary, and the amorphous S1 thin film was crystallized over almost the entire area. As a result, the grain boundaries were reduced to approximately 5 μm.
A thin film-like crystal consisting of a group of crystal grains having an average grain size of 5 μm was obtained while being arranged in a lattice shape with intervals.

Lightly heated with a halogen lamp as in Examples 1 and 2,
Next, a field effect transistor was fabricated.

In all Examples, after the Si thin film whose grain boundary position was controlled by solid phase growth was heat treated at high temperature with light, the grain boundary position was reconfirmed using a transmission A electron microscope, and as a result, there was no grain boundary movement.

The Si thin film whose grain boundary position was controlled according to Example 1.2.3 was irradiated with light to improve its crystallinity, and then a transistor was fabricated. As shown in FIG. The property quality is improved, and as shown in Table 1 [Table 1 (B)], the variation is reduced, which is very advantageous when building integrated circuits.

[Effects of the Invention] According to the present invention, crystal defects within crystal grains can be reduced without grain boundary movement by incoherent light irradiation on a solid-phase grown large-grain dendritic crystal Si thin film with grain boundary position control. As a result, high performance and high uniformity of the device fabricated therein can be achieved at the same time.

[Brief explanation of the drawing]

Figure 1 is a graph showing the relationship between implantation energy and crystallization temperature, Figure 2 is a graph showing the relationship between projected range and latent time, and Figure 3 is a graph showing the relationship between an amorphous layer and a crystalline layer. FIG. 4, a process diagram showing the process, is a graph showing the relationship between heat treatment temperature and crystal defects. Fig. 1 Fig. 3 Si''' Ion-implanted crystal S1 Fig. 2

Claims (4)

[Claims] (1) In a crystal growth method in which an amorphous thin film is crystallized by solid-phase growth to form a thin film crystal, a plurality of micro regions that serve as preferential nucleation points are formed at predetermined positions in the amorphous thin film. is formed, and then heat treatment is performed to cause solid phase growth from a single nucleus preferentially from the micro region to form a crystalline semiconductor thin film in which the position of the grain boundary is specified, and then the crystalline semiconductor thin film is A method for forming a semiconductor thin film, characterized by reducing intragranular defects by heat treatment at 1100° C. or higher. (2) The amorphous thin film is a thin film that becomes an amorphous structure as it is deposited, or a thin film that becomes an amorphous structure by performing ion implantation into the deposited amorphous layer or polycrystalline thin film. The method for forming the semiconductor thin film described above. (3) The formation of the minute region is performed by ion implantation with an implantation energy that causes implantation damage to the vicinity of the base interface in a portion other than the region.
The method for forming the semiconductor thin film described above. (4) The method for forming a semiconductor thin film according to any one of claims 1 to 3, wherein the heat treatment at 1100° C. or higher uses incoherent light irradiation.