JPH0440918B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention connects a main operation panel and a plurality of terminal devices to each other via signal lines, and centrally controls the loads connected to each terminal device by the main operation panel. This invention relates to a remote monitoring and control system that allows the main operation panel to centrally monitor the outputs of sensors, switches, etc. connected to each terminal.

FIG. 1 is a block diagram showing a schematic configuration of a conventional remote monitoring and control system, in which a large number of terminal devices 3 are connected to a signal line 2 connected to a main operation panel 1.
Signals are sent and received between the main operation panel 1 and each terminal device 3 for remote monitoring and control. A unique address is set for each terminal device 3. Since the address identifies each terminal device 3..., originally, terminal devices 3... having the same address are not connected in one system. However, if the address setting switch of the terminal device 3... is operated incorrectly during construction, the same address may be assigned to two or more terminal devices 3..., and in such a case, the return signal from the terminal device 3... There was a problem in that the returned signals could not be correctly identified because the timing overlapped.

The present invention has been made to solve these problems of the conventional example, and is designed to prevent the same address from being assigned to multiple terminals monitored and controlled by the main operation panel. The purpose of this project is to provide a remote monitoring and control system that provides

The configuration of the present invention will be described below with reference to illustrated embodiments. FIG. 2 is a block diagram showing the overall configuration of an embodiment of the present invention. The main operation panel 1 is operated by power from a power line 5 branched by a distribution board ₄ , and the power from this power line 5 is temporarily used as power for driving the loads 6... _2. It is something that is drawn into... On the other hand, each terminal device 3 ₁ , 3 ₂ ... is
The signal power sent from the main operation panel 3 via the signal line 2 using a time division multiplex transmission method is full-wave rectified and used as its own operating power source, and this signal itself is read to control the loads 6... This is what we do. 7 is a monitored device such as a sensor or switch, and its output is sent to the main operation panel 1 via a terminal ₃ .
It is now being sent back as a monitoring signal.
Each of the terminals 3 ₁ , 3 ₂ . . . has the same configuration as shown in the block diagram of FIG. In FIG. 3, 8 is a diode bridge that full-wave rectifies the signal power sent from the main operation panel 1 via the signal line 2, and the output voltage of this diode bridge 8 is provided in the power supply circuit 9. The signal is smoothed by a large capacitor and input to the power input terminal V _DD and GND of the terminal logic IC 10 . 11 is a waveform shaping circuit that shapes the voltage waveform on the signal line 2 and inputs the waveform to the signal input terminal S _G of the terminal logic IC 10. On the signal line 2, time division multiplexed transmission signals as shown in FIG. 4 are transmitted from the main operation panel 1 to each terminal device 3. In this signal, a wide pulse represents a logical value "1" and a narrow pulse represents a logical value "0", and for each terminal device 3, a wide pulse as a start pulse and a logical value "1"
1-bit pulse of , 8-bit address data AD for selecting a predetermined terminal 3, 1-bit address parity AP, 1-bit pulse of logical value "1", control in the called terminal 3 5-bit control data CD for setting contents, 1
It is designed to send out a signal in which long pulses for 5 to 6 bits, which are the bit control data parity CP and the waiting period for the return signal, are sequentially arranged in series, and this is sent cyclically and repeatedly for each address one after another. It is. Therefore, the terminal logic in each terminal device 3
The IC 10 receives the signal on the signal line 2 as described above via the waveform shaping circuit 11, and receives the address data.
When the data content of the AD is compared with the output of the address setting switch 12 and it is determined that the AD is calling, the content of the control data CD is output to the control output terminal 13, and the signal input to the monitoring input terminal 14 is output to the control output terminal 13. The signal is parallel-serial converted and output to the return signal output terminal 15. Therefore, the control data CD output to the control output terminal 13 is transmitted to each terminal device 3.
The monitor input terminal 14 is used as control data for the load 6 installed in the monitor input terminal 14, and the output of a monitored device 7 consisting of a sensor or a switch is input to the monitor input terminal 14. Furthermore, the return signal output to the return signal output terminal 15 is input to the base of the transistor 16, and by turning on and off the transistor 16 from the main operation panel 1 during the long pulse sending period, the signal line 2 is connected through the resistor R. This short-circuits the terminals and sends a return signal back to the main operation panel 1 in current mode.

Figures 5a to 5c show examples of such return signals, where the 1st to 5th bits are monitoring data, and the 6th bit is odd parity. Figure 5a shows a return signal sent back in current mode from a terminal device _3o assigned a specific address.
_5b shows the return signal R _n returned in current mode from the terminal 3 _n to which the same address was incorrectly assigned. Figure 5c is the return signal R _o shown in Figures 5a and b.
This shows the return signal R _no when R _n is received redundantly at the same timing on the main operation panel 1 . As is clear from Figure 5 a to c, the return signal R _o "00001" is the return signal R _n
Since they overlap with "101001" and the odd parity is also the correct value, it is impossible to determine that the addresses of the terminals 3 overlap by looking only at the logical values. Therefore, in the present invention, the main operation panel 1 is configured as shown in FIG. 6, and by checking the current level of the return signal, it is possible to determine whether or not the addresses of the terminal devices 3 are duplicated. It is something.

In FIG. 6, reference numeral 17 denotes a signal line driver circuit, in which the signal line 2 is
The non-grounded end of the circuit is driven in the positive and negative directions with respect to the ground potential, and a bipolar signal of ±24V is output as shown in the waveform diagram of FIG. The ground side end of the signal line 2 is grounded via the resistor γ of the return current detection section 19. This resistor γ has a sufficiently low resistance value, so that the influence of the voltage drop on the signal line 2 is small. The output of the return current detection section 19 is converted into an absolute value signal in an absolute value amplifier 20, and further amplified to a required level and waveform shaped in an amplification and waveform shaping section 21. The waveform-shaped signals are compared with a predetermined reference level by the level determination units 22 ₁ to 22 _o , and the number of terminals 3 having the same address connected to the signal line 2 can be determined. Further, the waveform-shaped signal is converted to a logic level by a level converter 23, and is input to a received signal processor 24 where it is identified as return data. FIG. 7 shows the operating principle of the present invention. For example, when K terminal devices 3 with the same address are connected to the signal line 2 in duplicate, when sending a return signal, the resistance
R ₁ to R _k are connected in parallel to signal line 2, and therefore, assuming that the resistance values of resistors R ₁ to _{R k} are approximately equal, the magnitude of the return current is determined by the fact that the addresses overlap. This is approximately K times as much as when it is not used. Therefore, the return current is K times the normal value (K=1,...,
n), the outputs of the level determining units 22 ₁ to 22 _k of the main operation panel 1 will be at the H level, and the outputs of the other level determining units 22 _k+1 to 22 _o will be at the L level. For example, terminal device 3 with the same address
This allows you to easily know how many units are connected in duplicate. Note that if you only want to check whether or not there are duplicate addresses, the level determination unit 22 ₁
It is sufficient to provide only 22 and ₂ .

The present invention is configured as described above, in which a main operation panel and a plurality of terminal devices are connected to each other via a pair of signal lines, and address signals and control data are sent from the main operation panel to each terminal device. A signal in which a signal and a long pulse signal for waiting for return are arranged in series is cyclically transmitted for each address, and each terminal device has an address judgment means for comparing the address signal on the signal line with its own address, and an address signal. control output means for producing a control output according to the control data signal when the
A monitoring signal return means is provided which returns the monitoring signal as a return current to the main operation panel side by short-circuiting the signal lines through an appropriate impedance during the period of the long pulse signal for return standby, and The panel includes return current detection means for detecting return current from each terminal device, and address duplication determination means for determining that addresses are duplicated when the magnitude of the return current detected by the return current detection means is equal to or higher than a predetermined level. Therefore, even if the same address is assigned to two or more terminals by mistake, the level judgment section installed in the main operation panel will determine that the return current is lower than the return current for one terminal. By determining whether or not the address is larger, the existence of terminals with duplicate addresses can be easily known, and there is an advantage that installation of terminals with the same address can be prevented. Furthermore, the remote monitoring and control system of the present invention has a main operation panel and a plurality of terminal devices connected to each other via a pair of signal lines, and the monitoring signal is originally sent back to the main operation panel from the means for returning the monitoring signal. Since the current mode monitoring signal is used to detect when the same address is assigned twice, in order to detect when the same address is duplicated,
There is no need to install separate detection wiring,
What's more, there is no need for any kind of circuitry on the terminal side to detect duplication of the same address; furthermore, it is possible to detect whether or not the same address is duplicated by simply connecting the terminal to the signal line as usual. There are advantages to being able to do so. If the level determination unit determines how many terminals the return current corresponds to, it is possible to accurately determine the number of terminals with duplicate addresses.
It's convenient.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 3 is a block diagram showing the configuration of the same terminal device, and FIG. 4 is a block diagram showing the same as above. Waveform diagram showing the transmission waveform on the line, No. 5
Figures a to c are waveform diagrams showing the current waveforms of the return currents as above, Fig. 6 is a circuit diagram showing the configuration of the main operation panel as above, and Fig. 7 is an equivalent circuit diagram showing the operating principle of the present invention. 1 is the main operation panel, 2 is the signal line, 3 is the terminal device, 10
is the terminal IC, 12 is the address setting switch,
13 is a control output terminal, 14 is a monitoring input terminal, 15
is a return signal output terminal, 19 is a return current detection section, 2
2 ₁ to 22 _o are level determination units.

Claims (1)

[Claims] 1 Connect the main operation panel and a plurality of terminal devices to each other via a pair of signal lines, and send an address signal, a control data signal, and a long pulse signal for waiting for return from the main operation panel to each terminal device. Serially arranged signals are cyclically transmitted for each address, and each terminal has an address judgment means that compares the address signal on the signal line with its own address, and a control output according to the control data signal when the address signals match. A control output means that generates a return current and a monitoring signal return function that returns the monitoring signal as a return current to the main operation panel by short-circuiting the signal line through an appropriate impedance during the period of the long pulse signal for return standby. provide means,
A return current detection means for detecting the return current from each terminal device on the main operation panel, and an address duplication determination means for determining that an address is duplicated when the magnitude of the return current detected by the return current detection means is equal to or higher than a predetermined level. A remote monitoring and control system comprising: