JPH0440762B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplitude detection circuit for a read circuit of a high-speed, large-capacity magnetic disk device.

Conventionally, the amplitude detection circuit of this type of magnetic disk device has rectified the read signal and held the read signal with different charging and discharging time constants to generate a threshold voltage for detecting the amplitude of the read signal. was. This is done by making the charging time constant small so that the threshold voltage can follow the peak voltage of the read signal, and conversely to prevent the threshold voltage from dropping extremely even when there are erased parts of the signal and there is no peak in the recorded waveform. The discharge time constant was increased. In this case, when the address of the magnetic head or the cylinder of the recording medium was switched and the amplitude of the read signal suddenly decreased, the threshold voltage could not follow the large discharge time constant.

The present invention provides a circuit in which the threshold voltage can follow a sudden drop in read signal amplitude by switching the address of the magnetic head or cylinder of the medium.

According to the present invention, in an amplitude detection circuit that rectifies a read signal to generate a threshold voltage and detects a signal by comparing the threshold voltage and the amplitude of the read signal, the rectified threshold voltage is An amplitude detection circuit for a magnetic recording device is obtained, which is characterized in that the discharge time constant is reduced for a certain period of time from an address switching signal of a magnetic head or a cylinder of a recording medium.

In this invention, since the read signal at the time of switching the address of the magnetic head or the cylinder of the recording medium is normally disturbed and cannot be used as information, the discharge voltage specified number of the threshold voltage generation circuit is made small in this area to follow the sudden drop in signal amplitude. I made a circuit that can do it.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of an amplitude detection circuit according to the present invention. Referring to FIG. 1, the differential amplifier is connected so that the read signals a ₁ and a ₂ are input, and further,
Its output is connected to the bases of transistors 10 and 11 through capacitors 2 and 3. Resistors 4 and 5 are connected in series between both capacitors 2 and 3, and these resistors 4 and 5 are connected to transistor 1.
0 and 11 and the anode of the constant voltage diode 8. The cathode of the voltage regulator diode 8 is grounded, and the anode side is connected through a resistor 9 so that a DC voltage of -V is applied thereto. The bases of transistors 12 and 13 are connected to the anode of a constant voltage diode through resistors 6 and 7, respectively. Transistors 10, 11,
Collectors 12 and 13 are each grounded.
Further, the emitters of transistors 10 and 11 are connected together, and similarly the emitters of transistors 12 and 13 are also connected together. The emitters of transistors 10 and 11 are connected to ground through a capacitor 15 and are connected through a resistor 14 to the emitters of transistors 12 and 13. Further, a DC voltage -V is applied to the emitter of the transistor 12 through a resistor 27. FET transistor 17 has its drain connected to the emitter of transistor 12 and its source connected to the emitter of transistor 10 through resistor 16.
The buffer circuits 18 and 19 are composed of, for example, a FET source follower or an operational amplifier whose main purpose is to convert impedance.
The emitter of transistor 0 and the emitter of transistor 12 are respectively connected to the input terminal side. The output terminal of the buffer circuit 18 is connected to the input terminals of the comparators 24 and 25, and the output terminal of the buffer circuit 19 is connected to the input terminals of the comparators 24 and 25 respectively through resistors 22 and 23.
is connected to the input terminal of Comparators 24, 25
The output terminals of are connected to the input terminals of the OR circuit 26, respectively. Read signals a1 and a2 are connected to be supplied to comparators 24 and 25 through capacitors 20 and 21, respectively.

FIG. 2 shows waveforms at each point in FIG. The read signals a1 and a2 are differential mode read signals, and the signal a1 has the same waveform as the signal a3.
However, the signals a1 and a3 have different DC bias voltages. A waveform l shown in FIG. 2, which is not shown in FIG. 1, represents a signal for switching the address of a magnetic head or a cylinder of a recording medium.

Next, the operation of one embodiment of the present invention will be explained with reference to FIG. Read signals a1, a2
is amplified by differential amplifier 1 and transistors 10, 1
1, and smoothed by a circuit consisting of a capacitor 15 and a resistor 14. Normally, the FET transistor 17 is "OFF" and the value of the resistor 14 is set large, so the discharge time constant is large. Also, the charging resistor is the transistor 10,
There are only 11 emitter resistors, so the charging time constant is small. Therefore, this smoothing circuit operates with a slight peak hold. This rectified voltage C is impedance-converted and level-shifted by the buffer circuit 18 to become a threshold voltage waveform f. transistor 1
The transistors 2 and 13 are the same as the transistors 10 and 11 and have similar characteristics, and are thermally coupled and mounted. Therefore, the voltage d is the temperature of the voltage c,
This is similar to the characteristic of change over time, and compensates for fluctuations in the potential difference between c and d. Similarly to the rectified voltage c, the rectified voltage d also has a waveform g due to the buffer circuit 19. A constant voltage circuit consisting of a resistor 9 and a constant voltage diode 8 is a circuit that determines the input bias voltage of the buffer circuits 18 and 19.

As a result, the read signal is rectified and its amplitude value is converted into a potential difference between f and g. The initial adjustment of the potential difference between f and g is performed by changing the gain of the differential amplifier 1.

As shown in FIG. 2, the read signal waveform a1 is biased with a voltage g to become a3, and a level pulse is generated by the comparator 24 using the waveform f as a threshold. In the case of the read signal waveform a2, a level pulse is generated by the comparator 25 in the same manner. These level pulses are converted into a level pulse train j by an OR circuit 26.

When the address of the magnetic head or the cylinder of the recording medium is switched, the read waveform a3 becomes excessively small as shown in FIG. When the address switching is completed and the amplitude of the read waveform there is much smaller than before the switching, the threshold voltage f cannot follow the change in amplitude as shown by the broken line. In the circuit of FIG. 1 constructed according to the present invention, the discharge time constant in this section is reduced by applying a signal k to the gate 17 that turns the FET transistor 17 "ON" for a certain period of time in synchronization with the address switching timing. This improves the follow-up characteristics of the threshold voltage f.

As explained above, the present invention reduces the discharge time constant of the threshold generation circuit to improve followability during address switching where a sudden change in the read signal amplitude occurs, so that amplitude detection is less likely to be hindered and the reliability is high. It has the effect of amplitude detection.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a partial block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms of various parts shown in FIG. 1... Differential amplifier, 2, 3... Capacitor, 4
~7... Resistor, 8... Constant voltage diode, 9...
...Resistor, 10-13...Transistor, 14...
...Resistor, 15...Capacitor, 16...Resistor, 17...FET transistor, 18,9...
Buffer circuit, 20, 21... Capacitor, 2
2, 23...Resistor, 24, 25...Comparator, 2
6...OR circuit, 27...Resistor.

Claims (1)

[Claims] 1. In the amplitude detection circuit that rectifies and smoothes the read signal to generate a threshold voltage, and detects the signal by comparing the threshold voltage and the amplitude of the read signal, An amplitude detection circuit for a magnetic recording device, characterized in that a discharge time constant of the rectified and smoothed threshold voltage is made small for a predetermined period of time.