JPH0440529A - Real time processor - Google Patents

Abstract

PURPOSE:To eliminate the ROM access waiting even at the time of executing a condition branching instruction and at the time of executing an interruption, and to obtain this real time processor having high speed responsiveness by incorporating a ROM which has plural address inputs and plural data output ports, and can access simultaneously plural different ROM data. CONSTITUTION:The real time processor is constituted with plural address inputs and plural data output ports. In this case, when a dual port ROM provided with two ports is used as a ROM 1, a queue A4, a ROM (port A side) 1 and a ROM pointer A2, a queue B4', a ROM (port B side) 1 and a ROM pointer B2' are independent, and an access can be executed simultaneously from the A side and the B side to the ROM 1. In such a manner, at the time of executing a condition branching instruction, at the time of interruption, etc., ROM access waiting is eliminated, and a real time system is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a real-time processing device incorporating a ROM that provides two or more address inputs and two or more data output ports.

Conventional technology In the past, when a conditional branch instruction was executed in a semiconductor integrated circuit device such as a microprocessor or microcontroller, the instruction pointer was calculated and the ROM data was accessed after the condition was met, so there was a difference between when the condition was met and when the condition was not met. There was a difference in the time it took to execute the next instruction after a conditional branch instruction. To solve this problem, we created two caches (one for when the condition is met and one for when the condition is not met).
A method of accessing preliminary ROM data using a low-capacity, high-speed storage device provided between a main memory and a processor has been considered. In this case, the ROM data when the condition is met and the ROM data when the condition is not met are sequentially read from the main memory, which has one output, and stored in the respective caches. The idea is to read data from one of the caches when determining a condition, and to make the processing speed the same between when the condition is met and when the condition is not met.

Invention or problem to be solved However, when the condition is not satisfied and an attempt is made to read the branch destination instruction, the condition judgment is shorter than the transfer of the instruction from 1, 0 to the cache, so the condition judgment is shorter. This method has not always been effective because time is lost if the necessary data cannot be prepared in advance, and a cache is required either within the semiconductor integrated circuit or externally.

Further, in the case of an interrupt, since the interrupt processing program is accessed after the interrupt is activated, the time required for accessing the ROM is required, which is an obstacle to real-time processing that requires high-speed response.

Furthermore, if there are multiple queues in the real-time processing device, since the ROM data output is one port,
Since the output of ROM data to the queue is performed only to one of the multiple queues, the transfer of ROM data to the queue is not performed efficiently, and it is necessary to use multiple queues to run multiple programs in parallel. If you run ', ROM
There was a waiting time for access, so-called queue waiting. Furthermore, when reading ROM data as operand data, it is necessary to temporarily stop accessing the ROM data on the instruction data side, making it impossible to access the ROM data efficiently.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a real-time processing device that eliminates the need to wait for ROM access and has high-speed responsiveness even when executing conditional branch instructions and interrupts.

Means for Solving the Problems To achieve this object, the real-time processing device of the present invention is comprised of a ROM having multiple address inputs and multiple output ports.

Effect: With this configuration, there is no need to wait for ROM access when executing a conditional branch instruction, when interrupting, etc., and a real-time system can be realized.

Example Examples of the present invention will be described below.

FIG. 1 is a block diagram of a real-time processing device that is an embodiment of the present invention. The ROM pointer for ROM data fetch calculated by the instruction pointer calculation unit 3 is transferred to the ROM pointer A2 or ROM via the dedicated bus 7.7'.
It is transferred to M pointer B2'. ROM pointer A2
and ROM pointer B2' are input to ROMI via ROM address bus 66'. In this embodiment, a dual port ROM having two ports is assumed as the ROMI. ROM indicated by ROM pointer 6 or 6'
The data are each queue A4. It is stored in queue B4'.

Cue A4. ROM (port A side)1. ROM pointer A2 and queue 84' ROM (port B side)1. ROM
Pointer B2' is independent and can access ROM1 from side A and side B at the same time. ROM pointer A2. ROM pointer B2' is also connected to initial address generator 8 and RAM address 10.

The pointer for ROM data access calculated by the instruction pointer calculation unit 3 is the ROM pointer A2 or R.
It is transferred to OM pointer B2'. Here, the values of ROM pointer A2 and ROM pointer B2' may take different values or the same value, depending on the contents of the program.

The value of ROM pointer A2 or ROM pointer B2' is input to ROMI, and the ROM data stored in ROMI of the pointer value is read out to queue A4 and queue B4'. The above A-side and B-side operations are independent,
Operation during A and B surveys is possible only on the A side and only on the B side. The A side and B side can be stored in ROM independently and continuously if necessary.
There is no queue waiting because the data can be accessed.

Next, the case where ROM data is accessed as address data will be explained using FIG. First, address bus 1
Address data is stored in ROM pointer A2 or ROM pointer B2' via 0. For example, when side A is used for executing instructions, side B is assigned to the address data side.

ROMI is accessed by address data stored in ROM pointer A2 or ROM pointer B2',
The read data is output to the address data bus 11. In this case as well, since the A side and the B side operate independently, there is no need to stop ROM access and no queue waiting occurs.

Next, the case where it is used for interrupt processing will be explained using FIG. 1 as well. Assume that the A side is assigned to normal processing and the B side is assigned to interrupt-only processing. Since interrupt operations occur asynchronously with respect to normal operations, it is necessary to prepare by accessing the ROM. Therefore, the interrupt ROM data is simultaneously accessed using the normal operation processing sequence when the initial address is generated at the initial start. Normally, at the time of initial start, a start address is generated under the control of the micro ROM, the ROM is accessed based on that address, and execution is started. At the start, the device is initialized, so interrupts are normally prohibited. Interrupts are prohibited only at this point, and this prohibited section is used to access the interrupt processing program. The normal program and the interrupt processing program are efficiently executed at the same time to reduce the micro ROM sequence, and the initial address generator determines whether the address is for the normal program or the interrupt program. Each address is transferred to ROM pointer A2 or ROM pointer B2'. By setting and accessing the interrupt program in its initial state, you can check whether the interrupt wait time or RO
The time required for M access can be shortened, and micro R
Since the normal processing sequence of OM can be performed without stopping, the normal processing does not stop, and a real-time processing system can be easily provided.

The ROM access timing of the present invention will be explained using the sequence diagrams of FIGS. 2, 3, 4, and 5. Here, execution refers to instruction ROM access and actual instruction execution, indicating that ROM access and instruction execution are performed simultaneously, and fetch refers to access to ROM data.

A and B indicate the A side and B side of ROM access, and correspond to FIG. 1. The horizontal axis represents time.

FIG. 2 is a diagram showing a sequence in which a conditional branch instruction is executed. On the A side, a conditional branch instruction is executed in sequence A21, and in sequences A21 and A2-2, an instruction for a conditional branch or failure is fetched. Sequence B
In step 2-2, in response to the execution of the conditional branch instruction in step A2-1, the branch address when the condition is satisfied is calculated, and the instruction is fetched based on the address. That is, in sequences A2-2 and B2-2, ROM data is read simultaneously. The branch instruction executed in sequence A2-1 is determined at the end of sequence A2-2 (at the same timing as the end of sequence B2-2), and if the condition is met, the branch destination instruction is executed in sequence B23. . Since the branch destination instruction has already been fetched in sequence B2-2, no ROM access wait occurs. At this time, in sequence A2-3, the queue is at its capacity, so RO
M access is not performed. Also, since there may be a return from execution of a conditional branch destination instruction, the contents of the queue are held. If there is a return instruction at the end of sequence B2-3 and it returns to the main program,
Executed on A side. At this time, the value of the ROM data can be used as is, and no waiting time occurs due to ROM access. The above is the sequence when executing a conditional branch instruction.

FIG. 3 is a diagram showing a sequence for quickly executing an interrupt program during interrupt processing.

Simultaneously with the reset start, on the A side, the normal main program Phenotin-Kens A3-1 is started. On the B side, interrupt flowgram fetch sequence B5-1
or is started. These program fetches are performed simultaneously under the control of the micro ROM. Furthermore, since this is performed in the initialization section, no matter where an interrupt occurs during normal execution, the ROM data has already been fetched, and it can be adequately handled no matter where an interrupt occurs. Sequence A32
Now the main program sequence is executed. If an interrupt occurs during execution of sequence A3-3, interrupt processing is executed in sequence B5-4 on the B side. At this time, since the interrupt program has already been fetched in sequence B5-1, the interrupt program can be executed without waiting for ROM access. In sequence A3-4, the program after the interrupt return is fetched, and in the execution of sequence A3-5 after the interrupt return, there is no waiting time for ROM data fetch.

FIG. 4 is a diagram showing a sequence when ROM data is required as address data. On the A side, a normal program is executed in the sequence A4-1, A'1-2, A4-3. At this time, the ROM is used as address data.
Data is accessed in sequence B4-2. At this time, there is no need for the program at A4-2 to stop fetching data.

FIG. 5 is an example in which a plurality of programs are executed in a multi-register file system. Independent programs are being executed on the A side and the B side. Sequence A3
In sequence B5-1, instruction execution and program fetch are performed, and in sequence B5-1, only fetch is performed. Conversely, in sequence A3-2, only a plurality of instructions are executed, and in sequence B5-2, instruction execution and fetching are executed.

These sequences continue as described above, but since the fetch has finished in the previous sequence before execution, RO
Waiting for M access does not occur.

Effects of the Invention As described above, according to the present invention, a real-time device can be realized by efficiently accessing ROM data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a real-time processing device that is an embodiment of the present invention, FIG. 2 is a diagram showing a sequence when executing a conditional branch instruction according to the present invention, and FIG. 3 is a diagram showing a sequence when executing an interrupt according to the present invention. FIG. 4 is a diagram showing a sequence when ROM data is accessed as address data according to the present invention, and FIG. 5 is a diagram showing a sequence in a multi-register file system according to the present invention. 1...ROM, 2.2'...ROM
Pointers A, B, 3... Instruction pointer calculation unit, 44'... Queue A, B, 5.5',
7.7'9.9'...Exclusive lotus, 6.6'...
...ROM address bus, 8...Initial address generator, 10, RAM address bus, 11...
...RAM data bus. Name of agent: Patent attorney Shigetaka Awano (N)

Claims (3)

[Claims] (1) A real-time processing device that has a built-in ROM that has multiple address inputs and multiple data output ports and can access multiple different ROM data at the same time. (2) A built-in ROM having multiple address inputs and data output ports, an instruction pointer for accessing multiple ROM data, and an instruction pointer calculation unit for accessing one or more ROM data; Consisting of two or more sets of queues that temporarily store ROM data read by an instruction pointer,
2. The real-time processing device according to claim 1, wherein a plurality of ROM data can be read simultaneously. (3) The real-time processing device according to claim 1, wherein a plurality of independent ROM data can be automatically read simultaneously by hardware in an initial state.