JPH0440163A - Picture processor - Google Patents

Abstract

PURPOSE:To arbitrarily change the size of a filter and a coefficient in a spatial filter processing by separating a picture data into a color expressing component and a strength expressing component, changing the order of the picture data and executing a filter processing after weighting the picture data. CONSTITUTION:In a block circuit 105, the order of a picture element data is changed different from that of input time under the control of a control part 112, and the data is simultaneously outputted as data signals 30 and 40 to weighting circuits 106 and 107. The data signal 30 is inputted to the weighting circuit 106, weighted for each group according to a weighting coefficient transmitted from the control part 112 and becomes a data signal 50. The data signal 40 simultaneously transmitted to the weighting circuit 107 becomes a data signal 60 after being weighted for each group according to the coefficient transmitted from the control part 112.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to the application of an input image from an input unit such as an image scanner or a CCD to a printer, facsimile, etc. [Prior art] There is a -21379 spatial filter device. An image processing device using this filter sequentially reads out image data from a 3-row by 3-column image memory row by row or column by column, and performs digital spatial filter processing using the upper, lower, left, and right image data.

[Problems and Objectives to be Solved by the Invention] However, conventional image processing apparatuses have had the problem that the coefficients and sizes of filters cannot be easily changed by processing techniques.

Furthermore, there is a problem in that input/output address control using the image memory becomes complicated.

The present invention has been made to solve this problem, and its purpose is to make it possible to arbitrarily change the filter size and coefficients without complicating address control in spatial filter processing. Our goal is to provide an image processing device that can.

[Means to solve the problem]

In order to solve the above problems, the image processing device of the present invention includes a separation means for separating image data into a color expression component and an intensity expression component, a blocking means for converting the order of the image data, and a method for weighting the image data. The present invention is characterized in that multivalue processing is performed by a filter processing means having a plurality of means for performing filter processing.

[Effect]

According to the above configuration of the present invention, the size and coefficient of the filter can be arbitrarily changed in the spatial filter processing.

Furthermore, spatial filter processing can be performed by specifying the filter size and coefficient without specifying the address of the image memory for each pixel.

〔Example〕

The present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram showing an image processing procedure according to an embodiment of the present invention. The image processing device of the present invention includes an input unit 101
, A/D conversion section 102 , correction circuit 103 , H3I conversion circuit 104 , blocking circuit 105 , and weighting circuit 106
, 107, logic operation circuit 108, and RGB conversion circuit 109
, output buffer 110 , output device 111 , and control section 11
It is composed of 2.

Below, a procedure for performing image processing and providing a multivalued image by this apparatus will be explained.

A KGB signal, which is an image signal inputted by an input unit 101 such as an image scanner or a CCD, is sent to an A/D converter 10.
2 into a digital RGB signal. The digital RGB signal is input to a correction circuit 103. The digital RGB signal is corrected by gamma correction, echo canceller, etc. in the correction circuit 103 and sent to the input section 10.
Correct the input distortion in 1. The digital RGB signal 10 output from the correction circuit 103 is input to the H3I conversion circuit 104. The digital KGB signal 10 input to the H3I conversion circuit 104 is converted into a digital H3I signal.

Here, the H3I signal refers to hue, saturation,
It is a signal that expresses a color by each component of intensity (1 ntensity). The H signal represents the hue component, the S signal represents the saturation component, and the ① signal represents the intensity component. As the hue changes, the color changes continuously in a circular pattern from red to orange to yellow to green to blue to purple to red. Saturation indicates the vividness of the color, and intensity indicates the brightness of the color. H3
The I color space is equivalent to the expression called the HLS color space in boat fishing.

The H3I conversion circuit 104 outputs the H3I signal to the blocking circuit 105. Said H3I conversion circuit 1
Of the 04 to H3I signals, the H signal and S signal are sent to the RGB conversion circuit.

The digital signal 20 input to the blocking circuit 105 is stored in the RAM as pixel data. In the blocking circuit 105, the pixel data is not changed in order from the input order under the control of the control unit 112, and is simultaneously outputted to a weighting circuit 106 and a weighting circuit 107 as a data signal 3o and a data signal 4o. . The data signal 30 is inputted into the weighting circuit 106, and the weighting sent from the control section 112 is weighted for each group by a coefficient, resulting in a data signal 50.

At the same time, the data signal 40 sent to the weighting circuit 107 is weighted for each group by the coefficient sent from the control section 112 to become a data signal 60.

The control unit 112 controls the size of the pixel data group, the weighting coefficient, and the value of the LUT table of the logic operation circuit 108.

The data signal 50 outputted from the weighting circuit 106 and the data signal 60 outputted from the weighting circuit 107 are both input to the logic operation circuit 108. In the logic operation circuit 108, the data signal 5o is
A logical operation is performed on the data signal 6° to form a multivalued digital signal 70, which is input to the RGB conversion circuit 109. In the KGB conversion circuit 109, the H signal and S signal sent from the H3I conversion circuit are converted into a data signal 7.
Delayed until 0 is sent. Data at the same address is synchronized. The H signal, S signal and data signal 70 are R
It is converted into a GB signal 80 and output to an output buffer 110.

The RGB signal 8 input to the output buffer 110
0 is sent to an output device 111 such as a printer or LCD and output.

FIG. 2 is a diagram showing details of the blocking circuit of FIG. 1. The blocking circuit includes an input latch 201 and an RA
M202, controller 203, and output latch 204
It consists of The controller 203 is controlled by the control section 112.

The digital signal 20 output from the H3I conversion circuit 104 in FIG. 1 is divided into data for each pixel by the input latch 201 and input to the RAM 202. The RAM 202 is a two-port memory, and has a structure that allows internal data to be output while inputting data.

The data input to the RAM 202 is controlled by the controller 203, and the order of the data is changed from when it was input, and is sent to the output latch 204, where it is output as a data signal 30 and a data signal 40 at the same time.

FIG. 3 is a diagram showing input addresses of pixel data in the RAM 202 of FIG. 2. The following describes a procedure in which the output order of the pixel data in the RAM 202 inside the blocking circuit is changed into the data signal 30 and the data signal 40 under the control of the controller 203 using FIG.

To the RAM202! i, up to n+1 scans are stored for each scan of the input unit 101(7).

In Figure 3, 1.1→1.2→1.3→...→1.
i-+1. i+1→... 1 scan completed, 2.1→
2.2→2.3→...→2. i→2, i+1→・
・・2 scans completed, 3.1→3.2→3,3→・・
・→３． i→3. i+1→... Pixel data for n+1 scans are input in the address order at the end of 3 scans.

The stored pixel data is 1.1-2.1-...
→n, 1→1.2→2.2→...→n, 2→1.3→
2.3→...→n, 3→...→1. i→2. i→・
...→n, i→1. The order is converted as i+1→... and output as data signal 2o. The output pixel data area of the RAM 202, that is, 1, 1 → 1.2 → 1.3 →
...→1. i→1. In the pixel data area of i+1→..., n+2 of the n+2th scan, 1→n+2.2→
One piece of data having addresses n+2, 3→n+2, 4, etc. is stored in synchronization with the output of n pieces of pixel data.

By storing data in the output free area as described above, if there is an area in the RAM 202 to store input pixel data for n+1 scans, the blocking circuit converts the order of all input pixel data. Can be output.

The time delay in the blocking circuit is n of the input section 1o1.
It's just a scan time delay. After the time delay, n pixel data is output for each input pixel.

In the conversion of the output order by the blocking circuit, n and i, that is, the size of the block, can be specified by the control unit 112.

FIG. 4 is a diagram showing details of the weighting circuit 106 of FIG. The weighting circuit is a weighting memory 401.
This is a transparsal filter circuit configured by a multiplier 402, a delay circuit 403, an adder 404, etc. and weights nXi group data. The number of nXi stages and weighting are stored in the memory 401 from the control unit 112.
nXi pieces of data are sent, and the weighting is controlled by the circuit.

In the weighting, the coefficients of the memory 401 weight nXi groups of pixel data. The procedure for weighting the pixel data to become the data signal 50 by the circuit will be described below.

Data signal 3 output from the blocking circuit 105
0 means that the weighting is applied to the circuit 106 and the pixel data is 1.1.
→2.1→...→n, 1→1.2→2.2→...→
n, 2→1.3→2,3→...→nJ→...→1.
i→2. The addresses are input in the order of i→...→n, i→1, i+1→.... After the pixel data is weighted and multiplied by the coefficient of the memory by the coefficient multiplier 402, the next pixel data is delayed by the delay time T by the delay time T input into the circuit. An adder 404 adds the result of multiplying the pixel data by a weighted coefficient and the weighted data of the pixel data.

Similarly, the weighting is multiplied by the coefficient and the result is added to the nXi groups of pixel data.The weighting is multiplied by the reciprocal of the sum of the coefficients by the coefficient multiplier 405, and the data signal 50 is obtained.

The weighting coefficient 402 in the memory 401 can be rewritten by the control unit 112.

The weighting circuit 107 and the weighting circuit 106 in FIG. 1 have the same configuration.

Similarly, data signal 40 is weighted in circuit 107 and becomes data signal 60.

FIGS. 5(a) and 5(b) are diagrams showing examples of weighting coefficients for 5×5 pixel groups of the weighting circuit 106 and the weighting circuit 107, respectively.

The weighting shown in Fig. 5(a) is based on a coefficient, and the weighting of surrounding 5x5 pixel data is applied to a central pixel using a coefficient.The result of spatial filtering is the generation of a single dot in the output image relative to the input image. This has the effect of suppressing vertical lines and emphasizing vertical lines.

The weighting shown in Fig. 5(b) is based on a coefficient, and the weighting of surrounding 5x5 pixel data is applied to a central pixel using a coefficient.The result of spatial filtering is the generation of a single dot in the output image relative to the input image. It has the effect of suppressing the lines and emphasizing the horizontal lines.

FIG. 6 is a diagram showing details of the logic operation circuit of FIG. 1. The logic operation circuit includes an adder 601 and a logic operation circuit 6.
02 and an LUT table 603.

The weighting circuit 106 and the weighting circuit 107 are
As shown in FIG. 4, since they have the same configuration, the pixel data input at the same time will receive the data signal 5 after the same delay time.
0 and the data signal 60 are simultaneously input to the adder 601. The data signal 5 input to the adder 6o1
0 and the data signal 60 are added for every n pixels and input to the arithmetic circuit 602. In the arithmetic circuit 602, LU
According to the T table 603, it becomes a multi-value engineering signal 70 and RG
It is output to the B conversion circuit. The values of the LUT table 603 are specified by the control unit 112.

〔Effect of the invention〕

According to the image processing device of the present invention, by simply specifying the size and coefficient of the spatial filter to the control unit, weighting can be performed by a blocking circuit that transforms input image data before calculation, and multiple weighting can be performed by a circuit. , image processing can be performed by arbitrarily changing the size and coefficients of the spatial filter.

Furthermore, after a certain time delay between the blocking circuit and the calculation time, one pixel is output for each input pixel, resulting in high-speed processing.

Further, by performing spatial filter processing after converting the RGB color space to the H3I color space, an image whose saturation and hue are faithfully reproduced can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an image processing procedure according to an embodiment of the present invention. FIG. 2 is a diagram showing details of the blocking circuit of FIG. 1. FIG. 3 is a diagram showing pixel data in the RAM of FIG. 2. FIG. 4 is a diagram showing details of the weighting circuit of FIG. 1. FIGS. 5(a) and 5(b) are diagrams showing examples of weighting coefficients for 5×5 pixel groups in the weighting circuit of FIG. 4. FIG. 6 is a diagram showing details of the logic operation circuit of FIG. 1. 106°...Input section...A/D conversion section...Correction circuit...H3I conversion circuit...Blocking circuit 107...Weighting circuit 201°403° 405°...RGB conversion circuit...Logic operation circuit...Output buffer...Output device...Control unit 204...Latch...RAM...Controller ... Weighting is memory ... Weighting is coefficient 406 ... Multiplier ... Delay circuit 601 ... Adder ... Arithmetic circuit ... Application for LUT table and above Person: Seiko Epson Co., Ltd. Agent Patent Attorney Tsuchi Suzuki Ura 3 Department (1 other person) Figure 1 Figure 5 (a) Figure 5 (b)

Claims (1)

[Claims] In an image processing device that converts an image signal inputted by an optical image input means into digital data and performs multi-value processing, the multi-value processing includes separation of the digital data into a color expression component and an intensity expression component. 1. An image processing apparatus comprising a filter processing means having a plurality of means, a blocking means for converting the order of the digital data, and a means for weighting and filtering the digital data.