JP2005173926A - Image processing apparatus, method, program, and storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the versatility of an image processing circuit by reducing the constitution memory capacity of each image processing part constituted in an apparatus. <P>SOLUTION: The apparatus comprises a 1st storage means of storing image data; a 1st control means of storing the image data stored in the 1st storage means in a 2nd storage means by 1st rectangular areas; an area decision means of deciding which of character data and achromatic data data are image data in a 1st rectangular area; a magnification varying means of varying magnification of input image data with a specified magnification; an expanding means of expanding the decision result of the area decision means by the number of pixels of the magnification-varied image data; an achromatic coloring processing means of performing achromatic coloring processing for the magnification-varied image data; an image data selecting means of inputting the magnification-varied image data and image data after achromatic coloring processing and selecting and outputting either of the inputted image data according to the expanded decision result; a table selecting means of selecting an image formation table according to the expanded decision result; and an output image data generating means of generating output image data with the selected image formation table. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is compatible with both image reading devices (CCD (Charged Coupled Device) and CIS (Contact Image Sensor)), and stores image data read by each device in a memory and reads out the stored data. The present invention relates to an image processing technique for controlling a rectangular area unit.

  FIG. 20 is a block diagram showing the configuration of the scanner image processing circuit in the conventional image processing apparatus. As an image reading device, an optical element such as a CCD 2010 or CIS 2110 is used, and data according to a predetermined output format for each line unit in the main scanning direction is respectively converted into a CCD interface (I / F) circuit 2000 and a CIS interface (I / F). ) A / D converted by the circuit 2100 and stored in the main memory 2200. In this case, the CCD 2010 outputs data corresponding to R, G, and B in parallel, whereas the signal output from the CIS 2110 outputs R, G, and B data serially according to the lighting order of the LEDs. Due to the difference in output data characteristics, dedicated interface circuits are provided, and the read image data is stored in the main memory 2200 through a predetermined A / D conversion process (for example, , See Patent Document 1).

  Therefore, in order to develop the read image data on the main memory 2200, it depends on which device (for example, CCD or CIS) is used, and dedicated image data input processing is indispensable. It was. In other words, the image processing circuit is customized depending on which image reading device is used, which is a factor that hinders generalization and cost reduction of the image processing circuit.

  Also, in FIG. 20, each image processing block (shading correction processing unit 2300, character determination processing unit 2320, filter processing unit 2340, scaling processing unit 2350, achromatic color determination processing unit 2360, block attribute determination processing unit 2370, etc.). Are provided with dedicated line buffers 2400a to 2400f. In such a circuit configuration, data stored in the main memory 2200 is read for a plurality of lines in the main scanning direction, stored in dedicated line buffers (2400a to 2400f), and subjected to individual image processing. It was done.

  However, in a circuit configuration in which dedicated line buffers 2400a to 2400f are provided for each processing unit, the maximum number of pixels in the main scanning direction that can be processed depends on the memory capacity of the dedicated line buffer provided in each processing unit. As a result, the processing throughput is limited.

Further, in order to improve the processing capability, in the hardware configuration of the image processing circuit, an increase in the capacity of the line buffer increases the cost burden, and hinders cost reduction of the entire image processing apparatus.
JP-A-7-170372

  As described above, in the conventional image processing apparatus, the throughput of processing in each image processing unit configured in the apparatus depends on the capacity of the line buffer, which prevents cost reduction of the entire image processing apparatus and lacks versatility. It was a thing.

  Accordingly, an object of the present invention is to increase the versatility of an image processing circuit by reducing the configuration memory amount of each image processing unit configured in the apparatus.

  In order to solve the above problems, the present invention provides image data input means, first storage means for storing the input image data, and image data stored in the first storage means. First control means for storing in the second storage means for each rectangular area, and area determination means for determining whether the image data in the first rectangular area is at least character data or achromatic data An image processing apparatus comprising: a scaling unit that scales the input image data according to a predetermined scaling factor; and a determination result in the region determination unit that is equal to the number of pixels of the image data after scaling. Only the unfolding means for unfolding, the achromatic processing means for achromatic processing of the scaled image data, the scaled image data, and the achromatic processing image data are input. Acceptance, the exhibition An image data selection unit that selects and outputs one of the received image data based on the determined determination result, a table selection unit that selects an image formation table based on the developed determination result, and the selected Output image data generating means for generating output image data using the image forming table and the selected image data.

  According to the above-described present invention, the versatility of the image processing circuit can be increased by reducing the configuration memory amount of each image processing unit configured in the apparatus.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a schematic configuration of an image processing apparatus 200 according to an embodiment of the present invention. A scanner interface (hereinafter referred to as “scanner I / F”) unit 10 is connected to a CCD 17 and a CIS 18 via an analog front end (AFE) 15, and the read data without interposing a dedicated circuit. Can be taken into the image processing apparatus 200. Reference numeral 20 denotes a scanner image processing unit. The image data developed in the main memory 100 by the processing of the scanner I / F unit 10 is set in an image processing operation mode (color copy, monochrome copy, color scan, monochrome scan, etc.). It is a processing unit that executes corresponding image processing.

  The printer image processing unit 30 is a processing unit that performs image forming processing for outputting data obtained as a result of image processing by the scanner image processing unit 20 to a printer, and performs, for example, N-value processing. The processing contents of the scanner image processing unit 20 and the printer image processing unit 30 will be described in detail later. Reference numeral 40 denotes an LBP interface unit (hereinafter referred to as an LBPI / F unit) when a laser beam printer (hereinafter referred to as LBP) is connected as a recording unit of the present invention device, and reference numeral 45 denotes an LBPI / F unit 40. LBP.

  Reference numerals 50 and 60 denote JPEG and JBIG modules, which are processing units for executing image data compression / decompression processing conforming to a predetermined standard. Reference numeral 65 denotes a DMA control unit (hereinafter referred to as an LDMAC) connected to the scanner I / F unit 10, the scanner image processing unit 20, the printer image processing unit 30, the LBPI / F unit 40, JPEG 50, and JBIG 60. Each channel of the LDMAC is connected to the processing unit.

  For example, the scanner image processing unit 20 is connected to channel 1 of the LDMAC 65 (hereinafter referred to as DMAC / 1ch). Each channel of the LDMAC, in cooperation with the memory control unit 70, generates predetermined address information for DMA control regarding data exchange between each image processing unit (10, 20, 30) and the main memory 100. Set. For example, according to the type of image reading device, CCD 17 and CIS 18, address information for DMA transfer of image data read by the scanner I / F unit 10 to the main memory 100 is generated for each DMA channel. Alternatively, the address information for reading the image data developed on the main memory 100 is generated according to the DMA channel, and DMA-transferred to the scanner image processing unit 20. 40), and functions as a unit that manages DMA control between the image processing units (20, 30) together with the memory control means 70.

  Reference numeral 70 denotes a memory control unit, which connects the first BUS 80 of the image processing system and the second BUS 85 of the computer system, and performs control for writing and reading data to and from the main memory 100. Reference numeral 80 denotes a first BUS capable of transferring data between the processing units (10 to 60) of the image processing system. Reference numeral 85 denotes a CPU 180, a communication and user interface control unit 170, a mechatronics system control unit 125, and the like. It is the second BUS of the computer system to be connected.

  A control unit 90 performs DMA control between the second BUS 85 and each control unit connected to the second BUS 85. The control unit 90 is connected to the ROM 95 via the ROMISA 97 and is controlled according to the image reading device (CCD 17 or CIS 18). A control program is set. Since various control parameters and the like can be set according to the image reading device, image data input processing according to the individual data output formats of the CCD 17 and the CIS 18 can be performed, and it is not necessary to provide a dedicated interface circuit. .

  The mechatronics system control unit 125 includes a motor control unit 110 and an interrupt timer control unit 120 that controls timing for controlling motor drive timing and image processing system processing.

  The LCD control unit 130 is a unit that controls display for displaying various settings, processing statuses, and the like of the image processing apparatus on the LCD 135.

  Reference numerals 140 and 150 denote USB interface units that allow connection with peripheral devices. FIG. 1 shows a state in which the ink jet printer 175 is connected.

  Reference numeral 160 denotes a media access control (MAC) unit that controls at what timing (access) data should be sent to a connected device. A CPU 180 controls the overall operation of the image processing apparatus 200.

  Next, the flow of data read by the CCD 17 or CIS 18 as a reading device will be described. The scanner I / F unit 10 can correspond to the CCD 17 and the CIS 18 as image reading devices, and inputs signals of both image reading devices. The image data input here is DMA-transferred by the LDMAC 65 / 0ch and the memory control unit 70 and developed on the main memory 100.

  FIG. 3 shows the relationship between the schematic configuration of the LDMAC 65 and the main memory 100 that stores image data read by the image reading device (CCD 17, CIS 18). The process of transferring the image data to the main memory 100 by DMA transfer includes the I / O control unit 651 of the LDMAC 65 and the I / P control unit that controls the exchange of data between the main memory 100 and the scanner image processing unit 20. In addition, when the main memory 100 is used as a ring buffer, a buffer controller 655 for arbitrating data writing and reading is included.

<Configuration of I / O control unit 651>
Here, the I / O control unit 651 includes a data arbitration unit 651a, a first write data interface (I / F) unit 651b, and an I / O interface unit 651c. The I / O interface unit 651c sets predetermined address information generated for storing data in the main memory 100 in the first write data I / F unit 651b. Further, the image data output from the scanner I / F unit 10 is received, and the data is stored in each buffer channel (hereinafter referred to as “channel”) (ch0 to ch2) in the I / O control unit 651.

  The first write data I / F unit 651b is connected to the first BUS 80 for transferring data to the memory control unit 70, and is stored in each channel (ch0 to ch2) according to the generated predetermined address information. Data is DMA transferred to the memory control unit 70.

  The data arbitration unit 651a reads the data stored in each channel, and delivers the data of each channel in accordance with the writing process of the first write data I / F unit 651b. The first write data I / F unit 651b is connected to the buffer controller 655 and is controlled so that data read or write by the I / P control unit 652 described later does not conflict with access.

  Even when the main memory 100 to which the memory control unit 70 is connected is used as a ring buffer by this access control, the data is stored at the same memory address before the data stored in the main memory 100 is read. Can be prevented, and memory resources can be used effectively. Further, as described above, the transfer of the image data read by the reading device is developed in the main memory 100 by the dedicated DMA channel. Therefore, by switching the address control during the DMA transfer according to the image reading device, Image data can be captured without a dedicated interface circuit.

  In FIG. 1, the I / O control unit 651 and the I / P control unit 652 are described as DMAC / ch0 and DMAC / ch1, respectively. In FIG. 1, the DMAC / 2ch to 5ch, which is the internal configuration of the LDMAC 65, also has the configuration described in FIG. 3, and the I / O control unit 651 and the channel for writing to and reading from the main memory 100 The I / P control unit 652 is configured.

  The image data developed in the main memory 100 is input to the scanner image processing unit 20 as corresponding image data, that is, R, G, B data, or monochrome image data, for each predetermined rectangular area, and for each rectangular area. Image processing is executed. In order to perform image processing for each rectangular area, the CPU 180 stores in the main memory 100 shading (SHD) correction data for correcting variations in sensitivity of the light receiving elements of the image reading device (CCD 17 / CIS 18), variations in the amount of light of the LEDs 19, and the like. The shading data of the rectangular area and the image data of the rectangular area are DMA-transferred to the scanner image processing unit 20 by the I / P control unit 72 described later.

  FIG. 4 is a diagram for explaining reading of data when image data in a rectangular area is transferred from the main memory 100 to the block buffer RAM 210 (FIG. 2) of the scanner image processing unit 20.

  A specific method of image data processed by the scanner image processing unit 20 will be described with reference to an area (0, 0) in FIG. First, when processing the effective pixel area abcd of the area (0, 0), an image data area (AB1CD1) greater than or equal to the effective area must be set. Here, the effective pixel area means an area where there is a pixel that can be a target pixel when processing is performed in the scanner image processing unit 20, and particularly when the shape of the area where the pixel exists is a rectangle. This is called an effective rectangular area. In addition, as described above, the image data larger than the effective image area is set because the surrounding pixels must be referred to in order to perform processing such as filtering on the target pixel existing near the boundary of the effective area. Because it must. In the following description, particularly when an area is designated without being referred to as an effective pixel area or an effective rectangular area, the effective pixel area is an area including peripheral pixels necessary for processing, that is, an area (0, 0). If there is, the image data area AB1CD1 is referred to.

  FIG. 4C is a diagram for explaining surrounding pixels used in the processing of the effective pixel region abcd. Here, Nm represents the number of pixels in the main scanning direction of the rectangular image area input by the LDMAC 65 to the scanner image processing unit 20, and Ns represents the number of pixels in the sub scanning direction. Na represents the necessary number of pixels on the left end side required for the effective pixel region abcd, Nb represents the necessary number of pixels on the right end side, Nc represents the number of upper end pixels, and Nd represents the number of lower end pixels.

  For example, when a 5 × 5 filtering process is performed on an arbitrary target pixel in the effective pixel region, five pixels in the main scanning direction and five pixels in the sub-scanning direction are required around the target pixel, so that the boundary of the region Na, Nb, Nc, and Nd are all two pixels when the target pixel located at is considered.

  That is, the number of effective pixels in this case is (Nm-2-2) * (Ns-2-2) pixels. Furthermore, when performing color copying, the largest reference area in the image processing mode is required to determine the character. In order to detect black characters, it is necessary to reliably determine halftone dots and characters. For this reason, it is required to determine the period of halftone dots. In this case, Na, Nb, Nc, and Nd are set according to the determination algorithm, but generally exceed 10 pixels in many cases. Thus, the pixel data required around the effective pixel region is determined by the image processing algorithm performed by the scanner image processing unit 20, and the present invention describes an embodiment corresponding to a specific number of pixels. In this embodiment, the number of pixels is not particularly limited.

  Next, an operation when the LDMAC 65 transfers image data from the main memory 100 to the scanner image processing unit 20 will be described. The image data of the LDMAC 65 is transferred in units obtained by dividing the image data in the main memory 100 into rectangular areas. The operation when processing a rectangular image whose effective image area is abcd is as shown in FIGS. 4 (a) and 4 (b).

  The LDMAC 65 reads the corresponding data up to the B1 address in the main scanning direction using A in the main memory as a start address. When the reading of data in the main scanning direction is completed, the address of the next data to be read is moved to the A2 address in the figure shifted by one line in the sub-scanning direction, and the data is read up to the pixel at the B3 address in the main scanning direction. . In the same manner, data is read out, and data in the main scanning direction from the C address to the D1 address corresponding to the last line of the surrounding pixel area including the effective pixel area is read out, and the area (0, 0) Data reading is completed.

  Regarding the area (0, 1), B2ED2F is set as a rectangular area surrounding the effective area for the effective pixel area bedf (FIG. 4B), and reading of image data uses B2 as a start address. Corresponding data is read up to the E address in the main scanning direction. When the reading of the data in the main scanning direction is completed, the address of the next data to be read is moved to the B4 address in the figure shifted by one line in the sub-scanning direction, and the data is read up to the pixel at the B5 address in the main scanning direction.

  Then, the image data in the main scanning direction from the D2 address to the F address corresponding to the last line of the surrounding rectangular area is read, and the reading of the data in the second area is completed. Through the above processing, the data of the effective rectangular area including the surrounding rectangular area is read out. Thereafter, the same processing is performed for each rectangular area.

<Configuration of I / P control unit 652>
Reading of data stored in the main memory 100 is controlled by the I / P control unit 652 in the LDMAC 65 in FIG. The read data I / F unit 652a is connected to the main memory 100 via the second BUS 80 and the memory control unit 70, and the read data I / F unit 652a refers to the address information generated by the LDMAC 65 and refers to the main memory 100. Predetermined image data can be read out from.

  The read data is set to a plurality of predetermined channels (ch3 to ch6) by the data setting unit 652b. For example, image data for shading correction is channel 3 (ch3), frame sequential R data is channel 4 (ch4), frame sequential G data is channel 5 (ch5), and frame sequential B data is channel 6 (ch6). Each data is set.

  Data set in each channel (ch3 to ch6) is sequentially DMA-transferred through the I / P interface 652c under the control of the I / P control unit 652, and the block buffer RAM 210 (in the scanner image processing unit 20). 2).

  Channel 7 (ch7) is a channel for storing dot-sequential image data output from the scanner image processing unit 20 in order to store data subjected to predetermined image processing in the main memory 100. The scanner image processing unit 20 sends address information and control signals (a block end signal indicating the end of the rectangular area, a line end signal indicating the end of the line in the rectangular area) in accordance with the output of the dot sequential image data. Based on these information, the second write data I / F 652d stores the image data stored in the channel 7 in the main memory 100 via the memory control unit 70.

  FIG. 2 is a block diagram illustrating a schematic configuration of the scanner image processing unit 20, and processing corresponding to each image processing mode is executed on data loaded in the block buffer RAM 210. The scanner image processing unit 20 executes processing by switching a rectangular pixel region to be referenced with respect to the rectangular region in accordance with the set image processing mode. The contents of the scanner image processing unit 20 will be described below with reference to FIG.

  In FIG. 2, a shading correction block (SHD) 22 is a processing block for correcting variations in the light amount distribution of the light source (LED 19) in the main scanning direction, variations in light receiving elements of the image reading device, and dark output offset. The shading data stores correction data for one pixel in the order of bright R, bright G, bright B, dark R, dark G, and dark B in the main memory 100 in the order of the number of pixels corresponding to the rectangular area. (Number of pixels Nm in the main scanning direction) is input to the scanner image processing unit 20. The input line-sequential correction data is converted into dot-sequential data by the input data processing unit 21 and stored in the block buffer RMA 210 of the scanner image processing unit 20. Then, when the shading data capturing of the rectangular area is completed, the process proceeds to image data transfer.

  The input data processing unit 21 is a processing unit that executes processing for reconstructing frame sequential data separated into R, G, and B into dot sequential data. One-pixel data is stored in the main memory 100 as frame-sequential data for each color of R, G, and B, and when these data are loaded into the block buffer RAM 210, the input data processing unit 21 One pixel data is taken out every time and reconstructed as R, G, B data of one pixel. Reconstruction processing is performed for each pixel, and frame sequential image data is converted to dot sequential data.

  The pixel data corrected by the shading correction processing 22 is further subjected to image processing in the processing block 23. In the processing block 23, the averaging processing unit is a processing block that performs sub-sampling (simple decimation) for reducing the reading resolution in the main scanning direction, or averaging processing, and the input masking processing unit receives the input R, This is a processing block for calculating color correction of G and B data. The γ correction processing unit is a processing block that gives predetermined gradation characteristics to input data.

  The character determination processing 24 determines character attributes for input image data, that is, performs character determination and pixel determination of a line drawing outline, and determines whether or not a character and a line drawing are formed for each pixel constituting the input image data. It is a processing block for doing. Since the character discrimination process needs to refer to an area wider than the halftone dot period as described above, it is common to refer to an area that is about 10 pixels wider than the effective pixel area in both the main scanning direction and the sub-scanning direction. is there.

  The character determination signal 245 generated by the character determination process 24 is output for the number of pixels in the effective rectangular area, and is used in a filter correction processing block and a block attribute determination processing block described later. In the following description, the logic of the character determination signal 245 is assumed to be non-character determination when the value is “0” and character determination when the value is “1”.

  The processing block 25 includes an MTF correction processing unit, a color conversion processing unit, and a background density adjustment processing unit, and the following image processing is performed on the pixel data processed by the processing block 23. First, the MTF correction processing unit is a processing unit that performs filter processing in the main scanning direction for MTF difference correction and moire reduction at the time of zooming when changing the image reading device. This is a block for multiplying and adding each coefficient for a predetermined pixel in the main scanning direction. The color conversion processing unit performs conversion processing of multi-value image data of each color of R, G, and B when performing filtering (lightness enhancement, saturation enhancement, color determination) performed in the subsequent filter processing block 26. The background density adjustment processing unit automatically performs processing for obtaining binarized data suitable for facsimile communication or the like by automatically recognizing the background density of the document and correcting the background density value to the white side.

  The filter processing block 26 performs edge determination processing and saturation (Ca, Cb) of the lightness component (L) of the image as processing for performing color determination and filtering on the obtained data in the previous color conversion processing. Perform emphasis processing. At this time, the parameter of the enhancement amount can be changed based on the character generated in the character determination processing block 24, the determination signal of the line drawing outline portion, and the like. The filtered data is converted from the luminance signal (L) and color difference signals (Ca, Cb), which are internal signals, into R, G, B data and output. This processing block functions as an edge enhancement filter of 5 pixels × 5 pixels when processing monochrome image data.

  A block 27 is a processing block that performs linear interpolation scaling in the main scanning and sub-scanning directions, and performs input pixel data enlargement or reduction processing in the main scanning and sub-scanning directions according to the set magnification.

  A block 28 is an achromatic color determination processing block, and it is determined with reference to the output data from the processing block 25 whether an input pixel has an achromatic color attribute, that is, a pixel constituting an achromatic image. Achromatic color determination is performed. Since the determination result is used by the block attribute determination processing unit 29 in the subsequent stage, it is output as an achromatic color determination signal 285. The achromatic color determination signal 285 is also output for the number of pixels corresponding to the effective rectangular area, similarly to the character determination signal 245. In the following description, the logic of the achromatic color determination signal 285 is assumed to be chromatic color determination when the value is “0” and achromatic color determination when the value is “1”.

  A block 29 is a block attribute determination processing block, and an effective rectangle input with reference to a character determination signal 245 that is an output of the character determination processing block 24 and an achromatic color determination signal 285 that is an output of the achromatic color determination processing block 28. The block attribute of the image area is determined. Since the character determination signal 245 and the achromatic color determination signal 285 are output by being limited to the number of pixels in the effective rectangular area, the LDMAC 65 performs determination processing for each effective area in the rectangular area input to the scanner image processing 20.

  In the present embodiment, the above image processing is performed on image data in units of rectangular areas in accordance with the set image processing mode (copy mode, scanner mode, etc.). In addition, by setting a rectangular area corresponding to the image processing mode on the main memory 100 and switching the unit of the rectangular area, it is possible to realize resolution and high-definition processing corresponding to each image processing mode.

Next, block attribute determination processing that is a characteristic part of the apparatus of the present invention will be described in detail.
FIG. 21 is a flowchart showing the flow of block attribute determination processing. First, as described above, image data in a rectangular area is transferred from the main memory 100 to the block buffer RAM 210 (step S2101).

  The character determination process 24 performs character attribute determination on the image data transferred to the block buffer RAM 210, and outputs a character determination signal 245 to the block attribute determination processing unit 29 (step S2102). Similarly, the achromatic color determination processing unit 28 performs achromatic color attribute determination on the image data, and outputs an achromatic color determination signal 285 to the block attribute determination processing unit 29 (step S2103).

  FIG. 5 is a diagram illustrating an example of the configuration of the block attribute determination processing unit 29. Since FIG. 5 is described in the order of processing executed in each block, each step of the block attribute determination processing is also represented by processing executed in each block. In FIG. 5A, a determination signal generation unit 291 generates a determination signal for determining a block attribute based on an input character determination signal 245 and an achromatic color determination signal 285, and 292 is generated by a determination signal generation unit 291. Block attribute determination signal 293 is a main scanning direction determination unit for determining the main scanning direction, 294 is a sub scanning direction determination unit for determining the sub scanning direction, 295 and 296 are a main scanning direction determination unit 293, This is a determination signal output by the scanning direction determination unit 294, and count values counted inside are output.

  A block attribute determination unit 297 determines block attributes by referring to values of the main scanning direction determination signal 295 and the sub-scanning direction determination signal 296, and a determination signal 298 indicates a block attribute of a predetermined rectangular area unit in the input rectangular image data. A determination result holding unit 299 stores a plurality of rectangular areas in the main scanning direction to which the block attribute determination result signal 298 is input.

  Hereinafter, each processing unit constituting the block attribute determination processing unit 29 will be described. FIG. 8 is a diagram illustrating a configuration of the determination signal generation unit 291. Since FIG. 8 is described in the order of processing executed in each block, each step of the determination signal generation processing is also represented by processing executed in each block. The block attribute determination signal 292 is generated with reference to the character determination signal 245 and the achromatic color determination signal 285 input from the outside of the block attribute determination processing block 29 (step S2104). As the character determination signal 245, a signal obtained by inverting logic is generated by the inverting circuit 2911 and is input to the selector 2912. Similarly, the achromatic color determination signal 285 is also generated as a signal whose logic is inverted by the inverting circuit 2913 and is input to the selector 2914. The selector 2912 and the selector 2914 are configured such that the selection signal is switched by a register value configured in the block attribute determination processing unit 29, for example (switching signal 2917, switching signal 2918).

  The determination signal generation unit 291 is configured to pass the character determination signal 245 through the selector 2912 and the selector 2916. Accordingly, when the character determination signal is to be passed, “0” is input as the switching signal 2917 and the switching signal 2919, and the input character determination signal 245 is output as it is from the selector 2916 via the selector 2912. Therefore, in this case, a signal output from the selector 2916 as a basic signal for determining the attribute of the block (this is the block attribute determination signal 292) represents a non-character with “0”, and a character with “1”. Represent.

  On the other hand, when reflecting the result of the achromatic color determination signal 285 in the character determination signal 245, the selector 2914 selects the achromatic color determination signal 285 and outputs it to the AND circuit 2915. As a result, “1” is input from the selector 2912 to the AND circuit 2915 in both case of character determination and non-character determination. Therefore, the output from the AND circuit 2915 is the result of the achromatic color determination signal 285. In other words, “1” is output when the achromatic color determination signal 285 is achromatic color determination, and “0” is output when the chromatic color determination is performed. .

  The switching signal of the selector 2916 is switched by a register value configured in the block attribute determination processing unit 29, similarly to the switching signal of the selector 2912 or the selector 2914 described above. This register value is set to “0” when the character determination signal 245 is passed through, and is set to “1” when the achromatic color determination signal 285 is reflected in the character determination signal 245 for output.

  As described above, a function capable of inverting the determination signals output from the character determination processing block 24 and the achromatic color determination processing block 28 is provided, and a signal calculated by the AND circuit 2916 can be selected as the block attribute determination signal 292. Thus, various block determination signals 292 (character, non-character, achromatic character, chromatic character, achromatic non-character, chromatic non-character) can be generated.

  FIG. 8 shows an example of the determination signal generation unit 291 having a configuration in which it is possible to select whether the character determination signal 245 is to be passed or the achromatic color determination signal 285 is reflected. It is also possible to select whether to pass the achromatic color determination signal 285 or to reflect the character determination signal 245. Specifically, a signal input to the selector 2912 is an achromatic color determination signal 285, and a signal input to the selector 2914 is a character determination signal 245. In this case, when the achromatic color determination signal 285 is passed, the block attribute determination signal 292 represents an achromatic color at “1” and a chromatic color at “0”.

  When the contents of the character determination signal 245 are reflected, the output from the selector 2912 is input with a switching signal 2917 so that the achromatic color determination signal 285 is passed, and the output from the selector 2914 is “1”. The switching signal 2918 is input so that Accordingly, the achromatic color determination signal 285 is input from the selector 2912 to the AND circuit 2915, and “1” is always input from the selector 2914. Therefore, the output from the AND circuit 2915 represents an achromatic character or an achromatic non-character at “1”, and represents a chromatic character or a chromatic non-character at “0”. In this way, in the determination signal generation unit 291 having a configuration in which it is possible to select whether the character determination signal 245 is to be passed or the achromatic color determination signal 285 is reflected, the block attribute determination signal 292 is an achromatic color or a chromatic color. An achromatic character, an achromatic non-character, a chromatic character, and a chromatic non-character can be represented.

  Next, processing contents for performing main scanning direction determination with reference to the block determination signal 292 in the main scanning direction determination unit 293 and outputting the determination signal 295 will be described. FIG. 5B is a diagram illustrating an internal configuration of the main scanning direction determination unit 293. As illustrated in FIG. 5B, the main scanning direction determination unit 293 includes a main scanning continuity recognition unit 2931, an achromatic character group recognition unit 2932, and a main scanning count unit 2933.

  The operation of each processing unit will be described in more detail with reference to another drawing. FIG. 6A is a diagram for explaining the processing contents of the main scanning continuity recognition unit 2931. In the figure, blocks indicated as “0” and “1” indicate pixels, and the numbers described therein indicate the logic of the block attribute determination signal 292. In the following description of the main scanning continuity recognition unit 2931, the number of lines of the effective rectangular area input to the block attribute determination processing unit 29 will be described as four lines for simplification of the description.

  The main scanning continuity recognition unit 2931 is a processing unit that detects continuity in the main scanning direction of the block attribute determination signal 292. Hereinafter, the case where the continuity “5” is set by a register configured in the block attribute determination processing unit 29 (not shown) will be described. Looking at the arrangement of the block attribute determination signal 292 on the 0th line in FIG. 6A, “1” is continued five times from the second pixel to the sixth pixel.

  In such a case, the main scanning continuity recognition unit 2931 detects that the block attribute determination signal 292 satisfies the set continuity (the block attribute signal 292 in the thick frame line in FIG. 6 is a detected location). . When the block attribute determination signal 292 becomes “0” in the state where the continuity is less than the set value during counting, the count value is initialized and counting is started again.

  Further, the main scanning continuity recognition unit 2931 detects how many times the detection signal has been generated up to the end pixel of the line. That is, in the case of FIG. 6A, the number of detections is 0th line: 3 times, 1st line: 2 times, 2nd line: 1 time, 3rd line: 3 times.

  The achromatic color character group recognizing unit 2932 detects a line in which the number of times of detection for each line detected by the main scanning continuity recognizing unit 2931 is a predetermined value or more. For example, in the case where the continuity is “5” and the setting is made to detect lines where the continuity is 3 or more times per line, the 0th and 3rd lines are the detection target lines (FIG. 6B). ).

  The main scanning count unit 2933 performs processing for counting the number of lines detected by the achromatic character group recognition unit 2932. In the case of the set value used in the above description, the value output by the main scanning count unit 2933 is “2” (determination signal 295) (FIG. 6C).

  As described above, the main scanning direction determination unit 293 performs main scanning direction determination with reference to the block determination signal 292, and outputs the determination signal 295 (step S2105).

  Thus, the reason for paying attention to the continuity of the block attribute signal in each line is to improve the accuracy of the block attribute determination result. For example, in the case of recognizing a character, it is highly likely that pixels constituting the character are continuously arranged, and a pixel having a signal value “1” simply by paying attention to the amount (histogram) of the block attribute signal in the line. Are not arranged continuously, but even when many are arranged, it may be determined as a character, and the accuracy of the determination result will be reduced.

  Next, processing contents of the sub-scanning direction determination unit 294 will be described. The configuration of the sub-scanning direction determination unit 294 is shown in FIG. As shown in FIG. 5C, the sub-scanning direction determination unit 294 includes a main-scan continuity recognition unit 2941, an achromatic character group recognition unit 2942, a sub-scan continuity recognition unit 2943, and a sub-scan count unit 2944. . The block attribute determination signal referred to by the sub-scanning direction determination unit 294 is the same as the block attribute determination signal referred to by the main scanning direction determination unit 293.

  Hereinafter, each processing unit constituting the sub-scanning direction determination unit 294 will be described, but the operations of the main scanning continuity recognition unit 2941 and the achromatic character group recognition unit 2942 are the main scanning continuity described in the main scanning direction determination unit 293. Since the operations are the same as those of the recognition unit 2931 and the achromatic character group recognition unit 2932, description thereof is omitted here. However, it is assumed that different values can be set for the comparison values such as the continuity and the number of detected continuity occurrences in the line only by the same operation.

  The sub-scanning continuity recognition unit 2943 is a processing unit that detects that the lines detected by the achromatic character group recognition unit 2942 are continuous in the sub-scanning direction. For example, assuming that the block attribute determination signal 292 has the arrangement shown in FIG. 7A and the comparison value used in the description of the main scanning direction determination unit 293 is set (continuity: 5, detection count: 3 or more). Lines in which “1” continues for 5 pixels and is 3 or more times in the line are the 0th, 1st, 4th, 5th, and 6th lines.

  When the sub-scanning continuity detected by the sub-scanning continuity recognition unit 2943 is set to “2”, the 0th line, the 1st line, the 4th line, and the 5th line are detected line groups in FIG. It becomes. The fifth line and the sixth line are also continuous as detection lines, but since the continuity of the fifth line is detected at the fourth line, the sub-scanning continuity recognition unit 2943 does not detect it. The sub-scanning counting unit 2944 counts the number of line groups detected by the sub-scanning continuity recognition unit 2943. That is, in the above example, the count value is “2” (determination signal 296).

  As described above, the sub-scanning direction determination unit 294 performs sub-scanning direction determination with reference to the block determination signal 292, and outputs the determination signal 296 (step S2106).

  Next, processing contents of the block attribute determination unit 297 will be described. FIG. 13 is a diagram illustrating a configuration of the block attribute determination unit 297. Since FIG. 13 is described in the order of processing executed in each block, each step of processing in the block attribute determination unit 297 is represented by processing executed in each block. In the figure, reference numerals 2971 and 2993 are registers for setting comparison values with the input determination signals 295 and 296, reference numerals 2972 and 2974 are comparisons for comparing the register 2971 and the determination signal 295, and the comparison between the register 2971 and the determination signal 296. 2975 is an AND circuit.

  The comparator 2972 compares the determination signal 295 from the main scanning direction determination unit 293 with the value set in the register 2971. If the determination signal 295 is larger than the set value of the register 2971, a signal that satisfies the condition ("1") Is output to the AND circuit 2975. Similarly, the comparator 2974 compares the determination signal 296 from the sub-scanning direction determination unit 294 with the value set in the register 2972. If the determination signal 296 is larger than the set value in the register 2972, a signal that satisfies the condition ("1 ") Is output to the AND circuit 2975.

  When both the outputs of the comparator 2972 and the comparator 2974 are “1”, the AND circuit 2975 outputs the block attribute determination result signal 298 as an active state (“1”). For example, when the block attribute determination signal 292 is set as an achromatic character determination and “2” is set in the register 2971 and the register 2773 in the examples of FIGS. 6 and 7, the comparator 2972 and the comparator 2974, respectively. Outputs a signal satisfying the condition to the AND circuit 2975, and outputs a signal indicating that the attribute of the effective rectangular area input at this time is an achromatic color (outputs "1"). On the other hand, when “1” is not input from either of the comparators 2972 and 2974, a signal indicating that the attribute of the effective rectangular area is a chromatic color is output (“0” is output).

  As described above, the block attribute determination unit 297 generates and outputs the block attribute determination result signal 298 for each effective rectangular area using the determination signals 295 and 296 (step S2107).

  The block attribute determination result signal 298 determined by the block attribute determination unit 297 is held by the subsequent determination result holding unit 299 (step S2108). The configuration of the determination result holding unit 299 is shown in FIG. Since FIG. 14 is described in the order of processing executed in each block, each step of processing in the determination result holding unit is also represented by processing executed in each block. In FIG. 14, 2991 is a timing signal that becomes active every time the final pixel processing of the effective rectangular area is input. That is, taking the case of FIG. 4C as an example, when the pixel d is processed, the timing signal 2991 becomes “1”. Reference numeral 2992 denotes a timing signal that becomes active in units of areas determined by the block attribute determination unit 297. In the case of FIG. 4C, the timing signal is “1” while the pixels belonging to the range of the effective rectangular area abcd are processed.

  2993 is a register that holds a comparison value for detecting how many blocks the effective rectangular area is configured in the main scanning direction, and 2994 is an active state (signal value is “1”) and an inactive state (signals) of the timing signal 2992 A counter 2995 counts the number of times of switching to “0”), and a comparison circuit 2995 generates a timing signal 2997 by comparing the set value of the register 2993 with the count value of the counter 2994. The timing signal 2997 is a signal that becomes active only when the final effective rectangular area determination process in the main scanning direction is completed, and is used as a synchronization signal for processing in the main scanning direction. That is, a value corresponding to the number of blocks existing in the main scanning direction is set in the register 2993. Reference numeral 2996 denotes a shift register that holds the block attribute determination result signal 298, and 2999 denotes a determination result holding register that holds the output signal of the shift register 2996 in synchronization with the timing signal 2997.

  The input block attribute determination result signal 298 is sequentially input to the shift register 2996 in synchronization with the timing signal 2991, and the block attribute determination result is held for each effective rectangular area. At this time, the shift register 2996 shifts and holds the block attribute determination result signal previously held for each input effective rectangular area. When the processing of the final effective rectangular area in the main scanning direction is completed, the value counted by the counter 2994 coincides with the set value of the register 2993, for example, and a timing signal 2997 is output and synchronized with the timing signal 2997. Then, the value of the shift register 2996 is transferred to the determination result holding register 2999. As a result, the block attribute determination results of a plurality of effective rectangular areas adjacent to each other in the main scanning direction are held in the determination result holding register 2999. At this time, the shift register 2996 is cleared to hold the block attribute determination result of the next effective rectangular area.

  Subsequently, when the effective rectangular area adjacent to the effective rectangular area processed in the sub scanning direction is sequentially processed in the main scanning direction and the block attribute determination result signal 298 is input to the shift register 2996, the shift register 2996 A value is held as a block attribute determination result signal of the effective rectangular area. At this time, the block attribute determination result held in the shift register 2996 is not transferred to the determination result holding register 2999 until the block attribute determination results of all the effective rectangular areas are held in the main scanning direction. The value of the determination result holding register 2999 is held until the processing of the direction final effective rectangular area is completed. Therefore, during this time, the CPU 180 can read the value of the determination result holding register 2999 and use the block attribute determination result of the effective rectangular area processed so far.

  In the above description, the case where the block attribute determination is performed in units of the effective rectangular area input to the scanner image processing unit 20 by the LDMAC 65 has been described. However, the present invention is not limited to the rectangular area unit. . That is, the input effective rectangular area may be further subdivided inside, and the block attribute determination may be performed in units of the subdivided area. FIG. 9 shows a block configuration in this case.

  In FIG. 9, the effective rectangular area processed by the entire scanner image processing unit 20 is abcd, and the rectangular image area that the LDMAC 65 inputs to the scanner image processing unit 20 in order to obtain the processing result of the effective rectangular area is the area ABCD. . FIG. 9 shows that the block attribute is determined by dividing the effective rectangular area abcd into four rectangular areas ab0cd0, a0b1c0d1, a1b2c1d2, and a2bc2d each having a pixel number Ne in the main scanning direction. In this example, the timing signal 2991 in FIG. 14 becomes active when the pixels d0, d1, d2, and d are input and processed, and the timing signal 2992 becomes active when the pixel d is input and processed.

  In FIG. 9, the effective rectangular area is subdivided equally by the main scanning direction pixels Ne. However, the number of main scanning direction pixels in each area may be different, or the effective rectangular area may be subdivided from the effective rectangular area. The block attribute may be determined by providing a separate determination processing unit for each of the converted areas.

  The value of Ne for further subdividing the effective rectangular area is preferably a power of 2 in consideration of the hardware scale, but the block attribute determination process in the device of the present invention is not limited to the above unit. Further, although subdivision in only the main scanning direction is shown in FIG. 9, it may be further subdivided in the sub scanning direction. FIG. 11 shows a configuration diagram in this case. In FIG. 11, the effective rectangular area abcd is divided into Nf lines and Ng lines in the sub-scanning direction, and divided into eight areas of inner areas ab0e0f0, a0b1e1f1, a1b2e2f2, a2be3f3, g0h0cd0, g1h1c0d1, g2h2c1d2, and g3h3c2d. In this example, the timing signal 2991 in FIG. 14 becomes active at the timing when the pixels f0, f1, f2, f3, d0, d1, d2, and d are inputted and processed, and the timing signal 2992 is inputted and processed by the pixel d. It becomes active at the timing.

When scaling processing is to be performed and the processing result of the effective rectangular area is to be raised to a power of 2, it is required to refer to surrounding line data. That is, there are cases where it is necessary not only to use pixels around the effective rectangular area as reference pixels, but also to perform processing using the pixels around that pixel as the target pixel. In this case, the effective rectangular area that is finally processed and output is an area that can be subdivided by setting the number of pixels in the main scanning direction or the number of sub-scanning lines to a power of 2, but from the line memory 100 to the scanner image processing unit. In the input image data, the surrounding line data is also input as an effective rectangular area. Therefore, in the block attribute determination process, it may be difficult to subdivide the number of pixels in the main scanning direction or the number of sub-scanning lines as a power of two. The block attribute determination unit 29 of the image processing apparatus 200 has a function of masking the input character determination signal 245 and achromatic color determination signal 285 in the main scanning direction and the sub-scanning direction. 10 and 12 are diagrams showing regions in this case. In FIG. 10, for example, when ab3cd3 is required as an intermediate effective rectangular area for obtaining the processing result of the effective rectangular area abcd by the main scanning scaling process, the character determination signal for the reference pixel Nf necessary for the scaling process and An achromatic color determination signal is input to the scanner processing unit 20 as an effective pixel.

  Even if extra Nf pixels are input, the rectangular region result finally output by the scaling process is abcd, so the block attribute determination processing unit receives the character determination signal 245 and the achromatic color determination signal 285 input as Nf. Are masked by the determination signal generation unit 291 and the count at the time of the block attribute determination process is not performed, and only signals for the rectangular area abcd are counted.

  Further, in FIG. 12, when the area ab3kl is required as the intermediate effective rectangular area for obtaining the processing result of the effective rectangular area abcd by the main scanning scaling process and the sub-scanning scaling process, the main necessary for the scaling process is required. The character determination signal and the achromatic color determination signal for the scanning direction reference pixel Nh and the sub-scanning direction reference line Ni are additionally input as effective pixels.

  Even if Nh pixels and Ni lines are input, the result of the rectangular area finally output by the scaling process is abcd, so the block attribute determination processing unit outputs the character determination signal 245 and achromatic color input as Nh and Ni. The input of the determination signal 285 is masked by the determination signal generation unit 291 and is not counted during the block attribute determination process.

  As described above, in the present invention corresponding to the present embodiment, image data read by a reading device is temporarily stored in a common main memory, and then image data is cut out in units of rectangular areas to perform image processing. The cost of the entire apparatus can be reduced and the versatility of the image processing circuit can be increased by significantly reducing and deleting the memory configured in the processing unit. In particular, since the input image data is a rectangular area, there is an effect that the block attribute discrimination processing unit can discriminate without configuring a memory.

  Further, for each rectangular area obtained by further subdividing the input rectangular area unit image data and the input rectangular area unit image data, the attribute of the area is determined, and a parameter corresponding to the determination result is used. By performing the recording process, the image quality of the output image can be improved.

  In addition, if the reference rectangular area of each processing unit operating simultaneously with the block attribute determination processing unit is larger than the area required by the block attribute determination processing unit, the unnecessary attribute is masked to improve the block attribute determination accuracy. It is possible to improve and eliminate the influence on the linked other processing units.

  In the present embodiment, image processing using the block attribute determination result signal obtained in the first embodiment will be described.

  First, the processing result of the scanner image processing unit 20 is developed in the main memory 100 in units of rectangular areas via the DMAC / 1ch of the LDMAC 65 and the memory control unit 70. When the apparatus of the present invention is operated in the scanner mode, the image data expanded in the main memory 100 is DMA-transferred to the USB 2.0 Device 140 by the DMAC 90, for example.

  When the apparatus of the present invention is operated in the copy mode, the image data developed in the main memory 100 is subjected to image processing of the recording system by the printer image processing 30. Recording image processing includes output masking processing, N-value conversion processing, smoothing processing, and the like. In the following description, N-value conversion processing using a block attribute determination result signal will be described.

  FIG. 15 is a diagram showing a processing block configuration for performing N-value conversion processing in the printer image processing unit 30. Since FIG. 15 is described in the order of processing executed in each block, each step of the N-value conversion processing in the printer image processing unit 30 is also represented by processing executed in each block. The image data processed in each processing unit shown in FIG. 2 of the scanner image processing unit 20 is developed in the main memory 100 in units of rectangular areas, and when the processing of a predetermined effective rectangular area is completed, the data output in units of lines is output. It becomes possible. When the CPU 180 sets an address or the like required for line-by-line image data transfer as a DMAC / 2ch control parameter of the LDMAC 65, the LDMAC 65 is connected from the main memory 100 to the printer image processing unit 30 via the memory control unit 70. Transfer image data to. Image data input to the printer image processing unit 30 is input as an input signal 301 in FIG.

  In the following description, it is assumed that the number of bits of each component in the input format R, G, B is 8 bits (0 to 255). In FIG. 15, 302 is a γ table that performs nonlinear tone correction and luminance density conversion on the input signal 301, 303 is an adder, 304 is a clamp processing unit that keeps the output of the adder 303 within a predetermined range, 305 Is an achromatic color processing unit that achromatically outputs the output signal of the clamp processing unit 304, 308 is a block attribute determination result signal determined by the block attribute determination processing unit 29 configured in the scanner image processing unit 20, and the CPU 180 Is read at a predetermined timing and notified to the printer image processing unit 30.

  309 is a determination signal pixel expansion unit that expands the pixel of the block attribute result determination signal 308, 307 is a signal output from the determination signal pixel expansion unit 309, a signal output from the achromatic processing 305 and a signal output from the clamp processing unit 304. A selector 310 for selecting and outputting the signal corresponding thereto outputs an output code (print data) corresponding to a signal output from the determination signal pixel developing unit 309 and a signal output from the selector 307, and a signal input to the selector 307. Is an output table that outputs multi-value data corresponding to, and 312 is a subtractor that calculates the difference between the signal output from the selector 307 and the multi-value data output from the output table 310, and 313 is the difference calculated by the subtractor 312. An error diffusion processing unit that performs diffusion processing on adjacent pixels, and 314 holds a value to be added to the data processing position of the next line Error buffer, 315 denotes an adder for adding the value error data and error diffusion processing unit 313 of the corresponding line of the error buffer 314 is outputted to the output.

  Hereinafter, the operation of the printer image processing unit 30 will be described in more detail. Input data of the printer image processing unit 30 is image data processed by the scanner image processing unit 20, and is input from the main memory 100 in units of lines via the memory control unit 70 and the LDMAC 65. The input data is R, G, and B 8-bit luminance data. A γ table 302 configured in the printer image processing unit 30 performs a non-linear gradation interpolation process on the input image data 301 and a density signal that is processing data of a recording system, that is, cyan (hereinafter referred to as C), magenta ( Hereinafter, conversion processing to M) and yellow (hereinafter, Y) is performed.

  The image data converted by the γ table 302 is added by the adder 315 and the adder 303 with the error data of the previous pixel generated by the error diffusion processing unit 313 described later and the target error data of the previous line stored in the error buffer 314. And input to the clamp processing unit 304. The clamp processing unit 304 corrects the portion exceeding the predetermined range by the adder 303, that is, clamps the value to “0” when the value is a negative value and to “255” when the value exceeds “255”.

  The clamped C, M, Y 8-bit image data is output to the selector 307 and also to the achromatic color processing unit 305. The achromatic color processing unit 305 performs a process in which all image components are at the same level for the input C, M, and Y image data having different values. Specifically, the process of setting the minimum or maximum value of input C, M, and Y as new C, M, and Y image data, or calculating the average value of C, M, and Y, A process for making M, Y image data and a function for adding an offset to the average value are provided, and any one of the processes for making the calculated value a new C, M, Y image data is performed. The C, M, and Y image data neutralized by the above-described processing is input to the selector 307.

  A block attribute determination result signal 298 generated by the block attribute determination unit 29 in the scanner image processing unit 20 is used as a switching signal for the selector 307. Specifically, the block attribute determination result signal 298 read out from the determination result holding unit 299 of the block attribute determination unit 29 by the CPU 180 is similarly sent to the printer image processing unit 30 as a determination signal 308 by the CPU 180 as a determination signal pixel developing unit. 309 is written.

  Further, the CPU 180 notifies the printer image processing unit 30 of the block area unit (number of main scanning pixels) determined by the block attribute determination processing unit 29. Since the determination by the block attribute determination processing unit 29 is not performed in units of pixels but in units of rectangular areas designated by the CPU 180, the determination signal pixel expansion unit 309 performs pixel expansion.

  The concept of pixel expansion in the determination signal pixel expansion unit 309 will be described with reference to FIG. However, in order to simplify the description, FIG. 18 shows a case where the determination rectangular area by the block attribute determination processing unit 29 is in units of 2 pixels in the main scanning direction and 2 lines in the sub scanning direction. In FIG. 18, the block attribute determination result of the rectangular area located on the left side is zero. The determination signal pixel developing unit 309 expands the pixels in the main scanning direction with reference to the fact that the determination rectangular area has two pixels in the main scanning direction.

  That is, the block attribute determination result “0” is expanded to “00” as a pixel. Thereafter, the block attribute determination result of the rectangular area located in the center of the figure and the block attribute determination result of the rectangular area located on the right side of the figure are developed as pixels, and “001111” is generated as the pixel development result of the three rectangular areas. . Even when the effective rectangular area is subdivided inside the block attribute determination processing unit 29, pixel expansion may be performed for each rectangular area in the main scanning direction using the concept described above.

  The selector 307 switches input C, M, and Y image data based on the determination result expanded by the determination signal pixel expansion unit 309. In other words, when the pixel expanded determination signal output from the determination signal pixel expansion unit 309 is “0”, the C, M, Y image data output from the clamp processing unit 304 is output to the subsequent processing unit, and the determination is performed. When the pixel-developed determination signal output from the signal pixel expansion unit 309 is “1”, the image data after the achromatic processing that has the same C, M, and Y levels output from the achromatic processing 305 is obtained. Output to the post-processing unit.

  In the output table 310, a table corresponding to the pixel-developed determination signal level output from the determination signal pixel developing unit 309 is set. The determination signal from the determination signal pixel developing unit 309 is not only the selector 307 but also the output table. Also input to 310. That is, an output table for the determination signal level “0” and an output table for the determination signal level “1” are configured. However, it is known that the number of tables required for achromatic color determination (achromatic color character determination) may be smaller than that required for chromatic color determination (chromatic color character determination). However, the total capacity of the table does not double.

  The output table 310 refers to the table according to the determination signal of the determination signal pixel expansion unit 309 based on the upper 3 bits of each of the C, M, and Y output signals of the selector 307 and inputs the output image data code 311a. C, M, and Y image data 311b based on the data is output. FIG. 16 is a diagram for explaining this operation. FIG. 16 represents an output table selected by the output signal of the determination signal pixel development unit 309.

  For example, when the combination of the upper 3 bits of C, M, and Y by the selector 307 is “101110101” indicated by a thick frame 1601, the output image data code 311a output from the output table 310 is “1”, M Becomes “0”, Y becomes “1”, and K becomes “0”. In this case, the C, M, and Y image data 311b based on the input data has C of “230”, M of “240”, and Y of “230”.

  In the description of the output table 310, the output image data code 311a is 1-bit data for each color. However, the bit number configuration of the output table in the present invention is not limited to 1 bit. That is, a table of levels that can be output by the final image data output unit (LBP printer, inkjet printer, etc.) may be set.

  Image data 311 b that is an output signal of the output table 310 is input to the subtractor 312 together with the output image data of the selector 307. The subtractor 312 calculates the difference between the image data 312 based on the upper 3 bits of each color of the output image data of the selector 307 and the actual image data at the processing position. The density of the input data and the output data is preserved by inputting and processing this calculation result in the error diffusion process in the subsequent stage.

  The processing performed by the error diffusion processing unit 313 is an already known image processing method, and the input difference data is distributed to adjacent pixels by a weighting operation configured by a predetermined matrix. As for the distributed error data, data for which the target is a pixel of the next line is written in the error buffer 314. In addition, the pixel to be processed next is output to the adder 315. The adder 315 performs an addition operation on the error data output from the error diffusion processing unit 313 and the target error data generated by the error diffusion process on the previous line, and outputs the result to the adder 303.

  As described above, based on the block attribute determination result signal of the block attribute determination unit 29 configured in the scanner image processing unit 20, the image data processed by the printer image processing unit 30 is subjected to achromatic color processing, and a dedicated output table. Can be used to perform printer image processing according to pixel attributes.

  In the above-described embodiment, the printer image processing unit 30 is configured such that the achromatic color processing unit 305 is disposed after the clamp processing unit 304. This is because the block attribute determination results are adjacent to each other. This is an effective configuration for preventing image degradation when the areas differ. With reference to FIG. 17, the concept regarding image degradation prevention will be described. In the figure, the attribute determination results of the blocks adjacent to the boundary A, boundary B, boundary C, and boundary D are different from each other such that one is a chromatic color determination and the other is an achromatic color determination.

  In such a case, when the achromatic processing unit 305 is disposed immediately after the γ table 302 or immediately after the adder 303, the achromatic data is input to the selector 307 without performing the clamping process. At the above four boundary positions, error data generated by the error diffusion process performed based on the chromatic color determination result and error data generated by the error diffusion process performed based on the achromatic color determination result are output all at once at the boundary. This will greatly affect the output data of the boundary portion beyond the range. In other words, the image data at the boundary portion is not smooth and adversely affects human eyes.

  As described above, in the present invention corresponding to the present embodiment, the recording system processing unit develops the pixel in a form corresponding to the rectangular area, and the optimum image processing parameter based on the developed determination signal. Can be used to perform image processing.

  In this embodiment, pixel development of a block attribute determination result when the image processing apparatus 200 of the present invention is operated in the copy mode and the scaling process is performed by the scanner image processing unit 20 will be described.

  In the image processing apparatus 200 corresponding to the present embodiment, the block attribute determination process in the block attribute determination processing unit 29 illustrated in FIG. 2 is performed as a pre-stage process of the scaling process in the scaling process unit 27. The reason why the processing in the block attribute determination processing unit 29 is preprocessing is to increase the accuracy of block attribute determination.

  If the block attribute determination process is executed after the scaling process, the processes in the character determination processing unit 24 and the achromatic color determination processing unit 28 are also automatically executed after the scaling process. As a result, the scaling process by the scaling process unit 27 is executed first, so that the character determination process and the achromatic color determination process are affected by the result of the scaling process.

  Considering a more specific case, for example, when image data is enlarged by scaling, character determination and achromatic color determination are naturally performed based on the image data after the enlargement processing. Character detection is often based on the detection of line drawing edge amount and halftone dot detection, so if linear interpolation processing is performed by enlargement processing, the determination accuracy is high due to factors such as the reduction of edge components. There is a risk of falling. That is, there is a case where what is determined based on the same-size image data becomes character determination, but determination based on the image data after enlargement processing is not character determination.

  The same applies to the achromatic color determination process, and the enlargement process extends the luminance component and the color component of the determination pixel, increasing the possibility of erroneous determination. The erroneous determination of the character determination result and the achromatic color determination result directly leads to the erroneous determination of the block attribute determination and causes image degradation. Therefore, in the image processing apparatus 200 corresponding to the present embodiment, the block attribute determination processing unit 29 is positioned in front of the scaling processing unit 27.

  However, if the block attribute determination processing unit 29 is preceded by the scaling processing unit 27, pixel development of the block attribute determination result signal at the time of the copying operation in which scaling is performed becomes complicated. This is because the image data output from the scanner image processing unit 20 has been subjected to scaling processing by the scaling processing unit 27, but the block attribute determination processing is performed on a rectangular region of equal magnification. is there.

  Therefore, in this embodiment, a configuration is adopted in which pixel expansion of the block attribute determination signal at the time of scaling processing is performed in a shared manner between the CPU 180 and the printer image processing unit 30.

  FIG. 19 shows a pixel development view during 150% scaling (enlargement) processing. However, in order to simplify the description, FIG. 19 shows a case where the determination rectangular area by the block attribute determination processing unit 29 is set to 2 pixels in the main scanning direction and 2 lines in the sub-scanning direction as in FIG. . In FIG. 19, the block attribute determination results of the rectangular areas located on the left side, the center, and the right side are 0, 1, and 1, respectively. In the configuration of the image processing apparatus 200 corresponding to the present embodiment, since the CPU 180 sets the magnification for the scaling processing unit 27, the block attribute determination result by the block attribute determination processing unit 29 is equal. The CPU 180 performs a process of developing pixels (lines) on the sub-scanning side.

  Note that the pixel development of the block attribute determination result signal on the main scanning side is performed by a determination signal pixel expansion unit 309 configured in the printer image processing unit 30. Referring to the example of FIG. 19, the CPU 180 first reads “011” as the block attribute determination result signal from the determination result holding unit 299 of the block attribute determination processing unit 29. Next, the read block attribute determination result signal is expanded based on the magnification specified for the scaling processing unit 27 (in this case, the number of pixels is 1.5 times in the sub-scanning direction, that is, 2 pixels are expanded to 3 pixels). Therefore, “011”, “011”, and “011” are obtained).

  The CPU 180 synchronizes with the input of the image data after the image processing by the scanner image processing unit 20 that is input to the printer image processing unit 30, and performs the printer image processing on the target determination result and the scaling factor of the block attribute determination result signal developed on the line. Input to the unit 30. A determination signal pixel developing unit 309 inside the printer image processing unit 30 expands the input block attribute determination result signal in the main scanning direction based on the magnification. In this case, since the number of pixels in the main scanning direction is 1.5 times, that is, 2 pixels are expanded to 3 pixels, each element of “011” is expanded so as to be 3 in succession, and becomes “000111111”. . The image processing of the recording system described above is performed using the block attribute determination result signal expanded in this way.

  In FIG. 19, the scaling factor is set to 150% for ease of explanation, but the actual setting magnification is usually in increments of 1%. Scale increases. However, in the configuration of the image processing apparatus 200 corresponding to the present embodiment, the control is simplified because the CPU 180 that knows the variable magnification including the processing synchronization relationship is interposed. In the description of FIG. 19, the enlargement process has been described. Even when the reduction process is performed, the CPU 180 and the printer image processing unit 30 perform the process.

  Further, the pixel development error of the block attribute determination result caused by the magnification is corrected to the logic of the block attribute determination result that has less influence in the printer image processing unit 30 and the image processing of the recording system is performed. For example, in order to avoid the influence on the output image, the recording system processing for pixels where the chromatic color determination result is used or the achromatic color determination result is used, the subsequent recording system image processing is performed using the chromatic color determination result. You may go.

  As described above, in the present invention corresponding to the present embodiment, even when the scaling process is performed in the reading system process, the CPU that controls the entire apparatus and the recording system image processing unit respectively suit the block attribute determination results. Since it is expanded in the direction, the overall control is simplified and the hardware scale is reduced by sharing the processing of the region attribute result during scaling processing in units of directions such as the main scanning direction and the sub-scanning direction. Can do.

[Other Embodiments]
Note that the present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, and a printer), and a device (for example, a copying machine and a facsimile device) including a single device. You may apply to.

  Another object of the present invention is to supply a storage medium (or recording medium) in which a program code of software that realizes the functions of the above-described embodiments is recorded to a system or apparatus, and the computer (or CPU or CPU) of the system or apparatus. Needless to say, this can also be achieved by the MPU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention. Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Furthermore, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function is determined based on the instruction of the program code. It goes without saying that the CPU or the like provided in the expansion card or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

1 is a diagram illustrating an example of an overall configuration of an image processing apparatus 100 corresponding to an embodiment of the present invention. It is a figure showing an example of the structure of the scanner image process part 20 corresponding to the Example of this invention. It is a figure showing an example of a structure of DMAC65 which performs the image data transfer of the rectangular area corresponding to the Example of this invention. It is a figure for demonstrating the image data reading control of the rectangular area corresponding to the Example of this invention. It is a figure which functionally represents an example of a structure of the block attribute determination process part 29 corresponding to the Example of this invention. It is a figure for demonstrating the content of the determination signal production | generation process corresponding to the Example of this invention. It is a figure for demonstrating the content of the determination signal production | generation process corresponding to the Example of this invention. It is a figure which represents functionally an example of a structure of the determination signal production | generation part 291 corresponding to the Example of this invention. It is a figure for demonstrating the subdivision of the effective rectangular area corresponding to the Example of this invention. It is a figure for demonstrating the subdivision of the effective rectangular area corresponding to the Example of this invention. It is a figure for demonstrating the subdivision of the effective rectangular area corresponding to the Example of this invention. It is a figure for demonstrating the subdivision of the effective rectangular area corresponding to the Example of this invention. It is a figure which functionally represents an example of a structure of the block attribute determination part 297 corresponding to the Example of this invention. It is a figure which functionally represents an example of a structure of the determination result holding | maintenance part 299 corresponding to the Example of this invention. It is a figure functionally showing an example of the structure of the printer image process part 30 corresponding to Example 2 of this invention. It is a figure showing the example of a table structure which produces | generates the printing data corresponding to Example 2 of this invention. It is a figure for demonstrating the case where the block attribute determination result corresponding to Example 2 of this invention differs in the mutually adjacent rectangular area. It is a figure for demonstrating the case where the block attribute determination result corresponding to Example 2 of this invention expands a pixel and a line. It is a figure for demonstrating the case where a block attribute determination result corresponding to Example 3 of this invention carries out pixel expansion and line expansion. It is a figure showing the example of a structure of the conventional apparatus. It is an example of the flowchart which shows the flow of the block attribute determination process corresponding to the Example of this invention.

Claims (6)

Image data input means, first storage means for storing the input image data, and image data stored in the first storage means are stored in the second storage means for each first rectangular area. An image processing apparatus comprising: first control means for storing; and area determination means for determining whether image data in the first rectangular area is at least one of character data and achromatic data,
Scaling means for scaling the input image data in accordance with a predetermined scaling ratio;
Expanding means for expanding the determination result in the area determining means by the number of pixels of the image data after the scaling;
Achromatic processing means for performing achromatic processing on the scaled image data;
Image data selection that accepts input of the scaled image data and the achromatic image data, and selects and outputs one of the accepted image data based on the developed determination result Means,
Table selection means for selecting an image forming table based on the developed determination result;
An image processing apparatus, comprising: output image data generation means for generating output image data using the selected image formation table and the selected image data. The expansion means is
First expansion means for expanding the scaled image data by the number of pixels in the main scanning direction;
The image processing apparatus according to claim 1, further comprising: a second expansion unit that expands the scaled image data by the number of pixels in the sub-scanning direction. An image data input unit, a first storage unit for storing the input image data, and image data stored in the first storage unit are stored in a second storage unit for each first rectangular area. A control method of an image processing apparatus comprising: a control unit for storing; and an area determination unit that determines whether image data in the first rectangular area is at least one of character data and achromatic data,
A scaling process for scaling the input image data according to a predetermined scaling ratio;
An unfolding step of unfolding the determination result in the region determining unit by the number of pixels of the image data after the scaling,
An achromatic process for achromatic processing the scaled image data;
Image data selection that accepts input of the scaled image data and the achromatic image data, and selects and outputs one of the accepted image data based on the developed determination result Process,
A table selection step of selecting an image forming table based on the developed determination result;
An image processing apparatus control method comprising: an output image data generation step of generating output image data using the selected image formation table and the selected image data. The unfolding step is
A first developing step of developing the scaled image data by the number of pixels in the main scanning direction;
The image processing apparatus control method according to claim 3, further comprising a second expansion step of expanding the scaled image data by the number of pixels in the sub-scanning direction.   A program for causing a computer to execute the control method of the image processing apparatus according to claim 3 or 4.   A computer-readable storage medium storing the program according to claim 5.

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