JPH0439804B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge coupled device (Charge Coupled Device).
The present invention relates to a circuit for generating input sampling pulses (hereinafter referred to as input pulses) for injecting input signal charges into a device (hereinafter referred to as CCD).

CCDs are widely used as compact, high-performance analog delay lines because they can delay signals by a desired amount of time and can be integrated into MOS. CCD
delays the input signal in the form of charges, so in addition to one or more charge transfer pulses to transfer and store these charges, it also requires a charge proportional to the amount of the input signal.
An input pulse is required to be injected into the CCD. Therefore, forming these drive pulse generation circuits on the same chip as the CCD is advantageous in terms of small size, low power consumption, and
This is a condition for providing an easy-to-use CCD delay line.

The potential balance method and the diode cutoff method are well known as methods for injecting input signal charges into a CCD. The potential balance method has excellent signal charge linearity and noise characteristics, but has the disadvantage that the shape of the input pulse for this purpose is complex. On the other hand, in the diode cutoff method, the input pulse generation circuit is simple, but the signal charge includes nonlinear distortion due to depletion layer capacitance. Hereinafter, regarding the potential balancing method that provides excellent signal charge linearity, the CCD input method will be explained with reference to the drawings, and the input pulse generation circuit required for the potential balancing method will be explained.

Figure 1 shows a CCD using an n-channel CCD as an example.
This figure shows a cross-sectional view of the input part of. 1 is p
This is a semiconductor substrate with a ground potential. 2 is the substrate 1
The n-type regions 3 and 4 formed on the surface are gate electrodes provided on the surface of the substrate 1 with an insulating film interposed therebetween.
2, 3, and 4 constitute the input section of the CCD. 5 is
A plurality of them constitute one delay stage, and one transfer pulse is generally applied to the leftmost electrode of a group of transfer electrodes that are repeatedly provided. In the case of the potential balance method, an input signal is applied to one of the gate electrodes 3 or 4, and a DC voltage is applied to the other gate electrode. 1
For example, a DC voltage V _G1 is applied to the gate 3, and an input signal V _G2 superimposed on a DC bias is applied to the gate 4. At this time, V _G1 and V _G2 are made to satisfy the condition V _G1 < V _G2 . The input pulse is applied to the n-type region 2. The voltage value of the input pulse during the period when the input signal is not sampled is set to a voltage value higher than the value of V _G1 (hereinafter referred to as high voltage value). Next, when sampling the input signal, the voltage value of the input pulse is set to a value lower than V _G1 (hereinafter referred to as a low voltage value), the charge is filled directly under the gate electrodes 3 and 4, and the input pulse is again Return the voltage value to the high voltage value. At this time, the surplus charge directly under the gate electrodes 3 and 4 returns to the n-type region 2 again, and finally only the charge proportional to the voltage difference (V _G2 -V _G1 ) is accumulated directly under the gate electrode 4. This charge is sent as a signal charge directly below the adjacent transfer electrode 5, and thereafter is sequentially transferred to the right directly below the transfer electrode group not shown in the figure. an n-type region 2 to which an input pulse is applied;
Between the substrate 1 directly under the gate electrodes 3 and 4, there is a pn
A junction is formed. Therefore, the potential of the n-type region 2 is the built-in potential of the p-n junction φ _B (
0.6V), this pn junction becomes forward biased, and the charge flows from region 2 to substrate 1, interfering with normal operation of the CCD. From the above, the low voltage value of the input pulse is lower than V _G1 ,
It is necessary to make it higher than φ _B.

In order for the low voltage value of the input pulse to satisfy the above conditions, conventional integrated input pulse generation circuits require the driver MOSFET channel, resistance, and load that make up the output stage inverter circuit and push-pull circuit to satisfy the above conditions.
This was achieved by reducing the MOSFET channel resistance ratio.

FIG. 2 shows an inverter circuit as an example for explaining a conventional input pulse generation circuit. 1
1 is a depletion type used as a load
MOSFET 12 is an enhancement type MOSFET used as a driver. 16 is a power supply terminal to which a high voltage value of an input pulse, for example, V _D is applied. Reference numeral 17 denotes an input terminal to which an inverted pulse of the timing of the input pulse obtained in the logic circuit section is supplied, and 19 denotes an output terminal of the input pulse, which is supplied to the input diode indicated by drawing number 2 in FIG. . In this inverter circuit, input terminal 1
Consider the case where voltage 7 is a high potential in the logic circuit section.
Since both MOSFETs 11 and 12 are conductive, the output voltage is determined by the ratio of the channel resistances of both MOSFETs. In a general inverter circuit, the channel resistance _R1 of MOSFET11 and
Ratio R ₁ /R ₂ of channel resistance R ₂ of MOSFET 12 is 10
or more, the low voltage value of output terminal 19 is almost
Make it so that it becomes 0V. However, in the case of a CCD input pulse generation circuit, R ₁ /R ₂ is made small so that the low voltage value becomes a desired value. Specifically, load MOSFET, driver
The MOSFET channel length is L _l , L _d , and the channel width is
Assuming W _l and W _d , (W _d /L _l ) is compared to (W _l /L l ).
There is a way to reduce the value of L _d ). However, in this method, because the channel resistance of the driver MOSFET is large, when the input pulse transitions from a high voltage value to a low voltage value, the driver MOSFET is
The disadvantage is that the time it takes for charges to be discharged through the input pulse is long, and the fall time of the input pulse is long.

Furthermore, since the low voltage value of the input pulse is fixed at the time of designing the peripheral circuit, the range of the input gate voltage values V _G1 and V _G2 of the manufactured CCD integrated circuit is limited, and the range of applications is narrowed. Further, due to variations in manufacturing conditions, the low voltage value of the input pulse fluctuates, resulting in problems such as the fact that optimal operating conditions for the CCD may not be obtained.

The purpose of the present invention is to eliminate the drawbacks of the conventional CCD input pulse generation circuit as described above, and to be able to control the low voltage value of the input pulse externally at high speed.
The purpose of the present invention is to provide a CCD input pulse generation circuit.

According to the invention, the load MOSFET and driver
Inverter circuit or push-pull circuit driver obtained by cascading MOSFETs
A third connection between the source of the MOSFET and ground
MOSFETs are connected in cascade, and the third MOSFET
A DC voltage value higher than the threshold voltage of the third MOSFET and whose value can be set externally is applied to the gate of the third MOSFET, and the drain and source are connected to the output terminal and ground of the inverter circuit or push-pull circuit, respectively. The fourth MOSFET
There is obtained an input sampling pulse generation circuit for a charge transfer element, characterized in that the gate of the driver MOSFET is connected to the gate of a fourth MOSFET via a differential circuit.

Hereinafter, the present invention will be explained in detail while showing examples. FIG. 3 is an embodiment of the present invention. A MOSFET 23 is cascade-connected to the ground side of an inverter circuit using an n-channel depletion type MOSFET 21 and an n-channel enhancement type MOSFET 22 as a load and a driver, respectively, and is further connected to the output terminal 29 of the inverter circuit and the ground.
Connect the drain and source of MOSFET24.
The gate terminal 30 of MOSFET 24 has
The gate terminal 27 of the MOSFET 22 is used as an input terminal, and the output terminal of a differentiating circuit including a capacitor 31 and a resistive element 32 is connected to the gate terminal 27 of the MOSFET 22. 26 is a power supply terminal to which a power supply voltage V _D is applied. 27
is an input terminal to which an inverted pulse of the CCD input pulse obtained in the logic circuit section is applied. 28
is the gate terminal of MOSFET23, and
A DC voltage value higher than the threshold voltage of 23, for example V _B , is applied. First, consider the case where the voltage at the input terminal 27 is 0V. Since the voltage at terminal 30 is also 0V
Both MOSFETs 22 and 24 are in a cut-off state. Therefore, the output terminal 29 is at V _D , that is, the high voltage value of the input pulse. Next, input terminal 27
voltage is the high level of the logic circuit section, e.g.
Think about the time of V _D. Since the voltage value of the terminal 30 has a value other than 0V only when the voltage value of the input terminal 27 changes, it is also 0V in this case. Therefore,
MOSFET 24 is in a cut-off state. On the other hand, terminal 2
Since the voltage value V _B of 8 is higher than the threshold voltage of MOSFET 23, MOSFETs 22 and 23 are in a conductive state. Now, MOSFET21,2 in this state
Letting the channel resistances of 2 and 23 be R ₁ , R ₂ , and R ₃ ,
The voltage V _O at the output terminal 29 is (R ₂ + R ₃ )/(R ₁ +
R ₂ + R ₃ ). Here, MOSFET22
If the channel resistance of MOSFETs 21 and 23 is sufficiently smaller than that of MOSFETs 21 and 23, V _O is approximately R ₃ /(R ₁
+R ₃ ). The value of R ₃ depends on V _B ; if V _B is increased, R ₃ is decreased, ie, V _O is decreased, and if V _B is decreased, R ₃ is increased, ie, V _O is increased. Therefore, by changing the value of V _B , it is possible to control the low voltage value of the CCD input pulse generated at the output terminal 29. Next, consider a transition state in which the voltage value at the terminal 27 changes from 0V to a high level, that is, _VD . At this time, current gradually begins to flow through the MOSFETs 22 and 23, discharging the charges accumulated in the load capacitance and wiring capacitance associated with the output terminal 29. On the other hand, the voltage at terminal 30 is
Since the voltage value is temporarily changed to such that the MOSFET 24 becomes conductive by the differentiating circuit composed of the resistor element 32 and the resistor element 32, the charges accumulated in the load capacitance and wiring capacitance associated with the output terminal 29 are as follows.
Not only MOSFET22 and 23 but also MOSFET24
It is also discharged through. Therefore, the discharge time of the charges is shortened, and the falling time of the input pulse of the CCD obtained at the output terminal 29 is shortened.
In particular, when it is desired to set the low voltage value of the CCD input pulse to a high value, the voltage value V _B of the terminal 28 is lowered and the channel resistance of the MOSFET 23 is increased, so the effect of the MOSFET 24 provided for bypass increases. .

As explained above, the present invention makes it possible to externally control the low voltage value of the CCD input pulse, which was previously impossible. It is possible to provide an input pulse generation circuit that can eliminate fluctuations in low voltage values and can set input operating conditions for these low voltage values to values suitable for CCD applications. Furthermore, since the present invention can shorten the falling time of the input pulse of a CCD, it is possible to provide an input pulse generation circuit for a high-speed operation CCD.

In the above explanation, the resistive element 31 used may be any element as long as it functions as a resistor, and for example, it may be one in which the drain terminal of a depletion type MOSFET is connected to the terminal 30, and the gate terminal and source terminal are grounded. I don't mind. In this way, it becomes easy to integrate the CCD input pulse generation circuit with the CCD main body on-chip. Furthermore, the differentiating circuit is not limited to, for example, a circuit using a capacitor and a resistor. The inverter circuit composed of the MOSFETs 21 and 22 is not limited to the circuit shown in FIG. 3, and the present invention is also applicable to circuits that operate on the same principle, such as push-pull circuits.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of the input portion of an n-channel CCD. 1 is a p-type semiconductor substrate, which is grounded. 2 is an n-type region formed on the surface of 1;
3 and 4 are input gate electrodes provided on 1 through an insulating film, and 5 is the leftmost transfer electrode. Second
The figure is an inverter circuit diagram shown to explain a conventional example of an input pulse generation circuit for a CCD that operates using the potential balance method. 11 is a depletion type MOSFET for loading, 12 is an enhancement type MOSFET for driver, 16 is a power supply terminal, 17 is an input terminal for pulses obtained in the logic circuit section, and 19 is an input pulse output terminal. FIG. 3 is a circuit diagram of an embodiment of the present invention. 21 and 22 are depletion type used as load and driver respectively
MOSFET, enhancement type MOSFET, 2
4 is an enhancement type MOSFET, 31,3
2 are a capacitor and a resistor, respectively, which constitute a differentiating circuit. 26 is a power supply terminal; 27 is a terminal into which an inverted pulse of the timing of the CCD input pulse is input; 29 is an output terminal for the CCD input pulse;
28 is a DC voltage application terminal for controlling the low voltage value of the input pulse of the CCD, and 30 is an output terminal of the differentiating circuit.

Claims (1)

[Claims] 1. A third MOSFET is connected in cascade between the source of the driver MOSFET of an inverter circuit or a push-pull circuit obtained by cascading a load MOSFET and a driver MOSFET, and the ground.
The gate of the third MOSFET is connected to the third MOSFET.
A fourth MOSFET is provided, to which a DC voltage value higher than the threshold voltage of the MOSFET and whose value can be set externally is applied, and whose drain and source are respectively connected to the output terminal of the inverter circuit or push-pull circuit and the ground. , from the gate of the driver MOSFET to the fourth
An input sampling pulse generation circuit for a charge transfer element, characterized in that the circuit is connected to the gate of a MOSFET.