JPH043977A - Read only semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce an area necessary to form a column gate of a transmission MIS transistor and to make the parasitic capacity of a selecting line uniform by selecting (n) pieces of data lines by the same selecting line, and employing the transistor for transmitting data to (m) pieces of common data lines. CONSTITUTION:When selecting line Y1 of selecting lines Y1 and Y2 becomes an 'H' level, data of a data line BL1 or BL2 is transmitted to a common data line DB1 or DB2 through a transmission N-channel MIS transistor Q1 or Q2 connected at a gate to the line Y1. Since two common data lines of a column gate of a transmitting MIS transistor are employed, the gates of the transistors Q1 and Q2, Q3 and Q4 can be connected to the same selecting line, and the number of contact holes can be reduced by half.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a transmission MIS for a read-only semiconductor memory device.
Regarding transistors.

[Summary of the Invention 1 The present invention provides a read-only semiconductor memory device in which a transmission MIS transistor selects n data lines using the same selection line and transmits data to m common data lines. This is intended to reduce the area required to form the MIS transistor.

[Prior Art] A circuit diagram of a column gate, which is a transmission MIS transistor used in a conventional read-only semiconductor memory device, is shown in FIG. 3, and a plan view thereof is shown in FIG. 4.

Ql is an N-channel MIS transistor for transmission, and its drain, source, source, or drain and gate are connected to an N-type region 1N-type region 2 a polycrystalline silicon layer 1
It is 0. Q2 is an N-channel MIS transistor for transmission, and its drain, source, drain, and gate are an N° type region 4N′ type region 5 and a polycrystalline silicon layer 11. Q3 is a transmission channel MIS transistor whose drain, source, drain, and gate are connected to an N''' type region 6N' type region 5,
This is a polycrystalline silicon layer 12. Q4 is an N-channel MIS transistor for transmission, and its drain or source/source or drain/gate is in the N° type region 3N9.
The mold region 2 is a polycrystalline silicon layer 13. BLI・BL2
・BL3 and BL4 are aluminum wiring layers 20 and 21.
22 and 23, and are connected to the N-type regions 14, 6, and 3 via contact holes 30, 31, 33, and 32, respectively.

DB is a common data line formed by the aluminum wiring layer 24, and is connected to the contact holes 34 and 3.
5 to the N-type region 25, respectively. Yl・¥2・Y3¥4 is aluminum wiring layer 25
- Selection lines formed by 26, 27, and 28, and are connected to polycrystalline silicon layers 10, 11, 12, and 13 via contact holes 40, 41, 42, and 43, respectively.

When the selection line Yl of the selection lines Yl-Y2, Y3, and Y4 goes to the ``H°'' level, the gate becomes the selection line Y1.
The data on the data line BLI is transferred to the common data line D via the transmission N-channel MIS transistor Ql connected to the common data line D.
It is transmitted to B.

[Problem to be solved by the invention] However, in the above-mentioned conventional technology, the transmission N-channel MIS
Polycrystalline silicon layers 7 and 10, which are the gates of the transmission N-channel MIS transistors Q1 and Q4, must be formed and wired on the sides of the transistors Q2 and Q3, respectively, which is necessary to form the column gate. In addition to increasing the area, the polycrystalline silicon layer 7.
Since the wiring lengths of the wiring 10 and the polycrystalline silicon layers 8 and 9 are different, there is a problem that the parasitic capacitance of the selection lines cannot be made the same.

The present invention is intended to solve these problems, and its purpose is to provide a column for a read-only semiconductor memory device that can reduce the area required for forming the column and make the parasitic capacitance of the selection line uniform. It's there to provide the gate.

[Means for Solving the Problems] In the read-only semiconductor memory device of the present invention, the drains or sources of the n transmission MIS transistors are each connected to 0 data lines, and the n transmission MIS transistors are connected to each other. The wiring layer is characterized in that the sources or drains are respectively connected to m common data lines, and the gates of the n transmission MIS transistors are connected to the same selection line.

[Embodiment] As an embodiment of the present invention, FIG. 1 shows a circuit diagram used in a column gate, which is a transmission MISI transistor of a read-only semiconductor storage device, and its plan view is shown in FIG. 2.
As shown in the figure.

Ql is an N-channel MIS transistor for transmission, and its drain, source, drain, and gate are N4 type region 1, N4 type region 2, and polycrystalline silicon layer 1.
It is 0. Q2 is an N-channel MIS transistor for transmission, and its drain, source, drain, and gate are an N'-type region 4, an N'-type region 5, and a polycrystalline silicon layer 10. Q3 is an N-channel MIS transistor for transmission, and its drain or source is an N''' type region 6, N' type head 5, and polycrystalline silicon layer 11. Q4 is an N channel MIS transistor for transmission. It is a channel MIS transistor, and its drain or source/source or drain/gate is an N9 type region 3.
N′″ type region 2/polycrystalline silicon layer 11. BLI
・BL2, BL3, BL4 are aluminum wiring layers 20
・This is a data line formed by 21, 22, and 23, and is connected to the N''' type region head 4, 6, and 3 through contact holes 30, 31, 33, and 32, respectively.DBI are common data lines formed of aluminum wiring layer 24, and are connected to N9 type region 2 through contact holes 34, respectively.

DB2 is a common data line formed of an aluminum wiring layer 25, and is connected to each N'' type region 5 through a contact hole 35.Yl
-Y2 is a selection line formed by aluminum wiring layers 26 and 27, and contact hole 40 and
41 to the polycrystalline silicon layers 10 and 11, respectively.

When the selection line Yl of the selection lines Y1 and Y2 becomes the °°H°° level, the transmission N-channel MIS transistor Q1 or Q whose gate is connected to the selection line Yl
The data 118BLL or BL2 is transmitted to the common data line DBI or DB2 via the common data line DBI or DB2, respectively. As means for selecting data on the common data line DB1 or DB2, although it is not nationally authorized, it may be selected using a separately formed N-channel MIS transistor for transmission, or select sense amplifiers connected to the common data lines DBI and DB2, respectively. can be selected by various means.

By reducing the number of common data lines for the column gate, which is a transmission MIS transistor, to two, N-channel MIS transmission
The gates of S transistors Q1 and Q2 and Q3 and Q4 were connected to the same selection line, and the number of contact holes could be halved. Furthermore, transmission MI
The number of selection lines for the column gates of the S transistors can be reduced to two, which is 1/2 compared to the conventional circuit. For example, when there are 64 data lines, 64 selection lines are required in the conventional circuit, but by reducing the number of common data lines to two according to the present invention, the number can be reduced to half, 32.

In the explanation of the present invention, the case where the common data line is two is used, but it is sufficient that the common data line is an exponential multiple of 2, and the transmission MIS
As a transistor, a P-channel MIS transistor or an N-channel MIS transistor and a P-channel MIS transistor may be used instead of the N-channel MISh transistor.

Furthermore, it goes without saying that the same effect can be obtained even if column decoders are provided for each column decoder without wiring the selection lines using an aluminum wiring layer.

[Effects of the Invention] As described above, the transmission MI selects n data lines using the same selection line and transmits data to m common data lines.
By using the S'l-transistor, it was possible to reduce the area required to form a column gate, which is a transmission MIS transistor, and to make the parasitic capacitance of one selection line uniform.

Furthermore, since the number of selection lines can be made equal to the number of data lines/the number of common data lines, the area required for forming the selection lines can also be reduced.

Furthermore, we were able to halve the number of contact holes, contributing to improved quality and manufacturing yield6.

[Brief explanation of drawings]

1 and 2 are a circuit diagram and a plan view of an embodiment of the present invention. 3 and 4 are a circuit diagram and a plan view according to the prior art. Ql-Q2, Q3, Q4...Transmission MIS transistor BLI, BL2, BL3, BL4...Data line Yl-Y2, DBI, DB2, selection line, common data line or higher

Claims (1)

[Claims] 1) The drains or sources of the n transmission MIS transistors are connected to the n data lines, and the sources or drains of the n transmission MIS transistors are connected to the m common data lines. A read-only semiconductor memory device characterized in that the gates of the n transmission MIS transistors are connected to the same selection line. 2) A read-only semiconductor memory device, wherein the gates of the n transmission MIS transistors according to claim 1 are formed in parallel to the n data lines. 3) A read-only semiconductor memory device according to claim 1, characterized in that m common data lines are formed orthogonally to n data lines. 4) A read-only semiconductor memory device according to claim 1, wherein the n transmission MIS transistors, the n data lines, the m common data lines, and the selection line are each an exponent of 2. 5) The drains or sources of the n transmission MIS transistors are connected to n data lines, the sources or drains of the n transmission MIS transistors are connected to two common data lines, and the n A read-only semiconductor memory device characterized in that every two transmission MIS transistors have gates connected to the same selection line.