JPH043934A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To bury a conductor layer at an approximately the same packing rate by relatively changing the ratio of the exposed area of a foundation conductive base body on a bottom to the opening area of a contact hole and controlling the speed of burying of the conductor layer. CONSTITUTION:When a contact hole is formed in an insulating film 2, the ratio of the opening area of a shallow contact hole 3B to the exposed area of a foundation conductive base body on a bottom is set previously at a value smaller than that of the opening diameter of a deep contact hole 3A to the exposed diameter of the founda tion conductive base body. When a conductor layer is selectively vapor-grown, the number of the growth nuclei 104 of the deep contact hole 3A is made larger than that of the shallow contact hole 3B because the density of nucleation is kept constant, growth also progresses in the lateral direction when deposition progresses and deposi tion thickness exceeds the tapered section 5, and the upward deposition rate of the conductor layer 4 is made largely smaller than that of the conductor layer 4 in the deep contact hole 3A, but the deposition rates are equalized when growth progresses and the whole bottom region is covered with the conductor layer 4 deposited. Accord ingly, the contact holes can be formed at approximately the same fine stepped sections.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example 1 Process sectional view of the example (Figure 3) etc. Process sectional view of the embodiment (FIG. 4) Effects of the invention [Summary] Regarding the improvement of a method for manufacturing a semiconductor device, especially a method for flattening a wiring formation surface by embedding a conductive layer in a contact hole, We provide a method that allows conductor layers to be buried in contact holes of different depths with a filling rate that is not significantly different, and after embedding, all the steps at the top of contact holes of different depths can be completely filled with a good wiring metal layer. For the purpose of burying a conductive layer in contact with the underlying conductive substrate at the bottom of the contact hole using selective vapor growth only within the contact hole, the underlying layer at the bottom of the contact hole is buried. By changing the relative ratio between the exposed area of the conductive substrate and the opening area of the contact hole, or by changing the material of the underlying conductive substrate exposed at the bottom of the contact hole, The structure includes a step of controlling the embedding speed of the conductor layer into the conductor layer.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to an improvement in a method of burying a conductor layer into a contact hole to planarize a surface on which wiring is formed.

In recent years, with the miniaturization and higher integration of semiconductor devices, the aspect ratio of contact holes for wiring connections has been increasing, and it is important to obtain wiring metal coverage that ensures reliability when forming wiring. Therefore, it has become essential to bury a conductor layer in the contact hole using selective vapor deposition technology to reduce the step formed above the contact hole.

On the other hand, in the current situation where wiring is becoming more multi-layered along with higher integration, the depth of the contact hole differs depending on where the wiring is drawn out, and as devices become smaller and the aspect ratio becomes higher. Therefore, the difference in aspect ratio of contact holes with different depths tends to become even larger. embedding technology is desired.

[Conventional technology]

In a conventional semiconductor device, a plurality of contact holes formed on the same substrate all have the same shape, and the relative ratio between the opening area at the top and the exposed area of the underlying conductive substrate at the bottom is as follows: All were formed identically.

Therefore, when filling multiple contact holes with a conductive layer by selective vapor phase growth of tungsten (W), etc., the filling speed for all contact holes on the same substrate (for straight contact holes, the vapor phase growth rate Responses) were all the same.

[Problem to be solved by the invention]

Therefore, as mentioned above, when the depth of the contact hole becomes uneven due to multi-layered wiring, etc., the filling rate of the conductor layer (filling thickness/contact hole depth) becomes irregular. For example, if an appropriate embedding thickness is selected for the shallowest contact hole, the filling rate will decrease in the deepest contact hole and the embedding thickness will not be sufficient.
A large step remains in the upper part of the contact hole, which causes a problem in that the coverage of the wiring metal film formed over the contact hole by sputtering or the like deteriorates, resulting in a decrease in the reliability of the wiring.

Therefore, the present invention provides a method capable of embedding a conductive layer in contact holes of different depths with a filling rate that is not significantly different, and completely eliminates the level difference at the top of the contact holes of different depths after embedding. The purpose is to keep the height difference within a low level so that good coverage of the wiring metal film can be obtained.

[Means to solve the problem]

The above-mentioned problem is that when a conductor layer that is in contact with the underlying conductive substrate at the bottom of the contact hole is buried by selective vapor growth means only in the contact hole, the exposed area of the underlying conductive substrate at the bottom of the contact hole and the By relatively changing the ratio of the opening area of the contact hole, or
A method for manufacturing a semiconductor device according to the present invention, comprising the step of controlling the filling speed of the conductive layer into the contact hole by changing the material of the underlying conductive substrate exposed at the bottom of the contact hole, or In multiple contact holes with different depths formed in the insulating film on the same substrate,
A method for manufacturing a semiconductor device comprising the step of simultaneously embedding a conductive layer in contact with the underlying conductive substrate at the bottom of the contact hole by selective vapor growth means to reduce a step difference between the contact hole portion and the upper surface of the insulating film, When forming the plurality of contact holes having different depths, the ratio of the exposed area of the bottom conductive substrate to the top opening area in the shallow contact hole is smaller than the ratio in the deep contact hole, or At least the region of the underlying conductive substrate disposed below the shallow contact hole that is exposed at the bottom of the contact hole is grown by selective vapor phase epitaxy over the surface of the underlying conductive substrate that is exposed at the bottom of the deep contact hole. This problem is solved by the method of manufacturing a semiconductor device according to the present invention, which includes a step of forming the semiconductor device using a conductive material with a slow nucleation rate.

[For production]

FIGS. 1(a) to 1(d) are process sectional views for explaining the principle of the present invention, in which (a) shows a deep contact hole portion and (b) shows a shallow contact hole portion.

In one method according to the present invention, as shown in FIG. 1(a), when forming a contact hole in the insulating film 2 on the underlying conductive substrate l, the opening area of the shallow contact hole 3B is diameter (Dss) and the exposed area of the underlying conductive substrate at the bottom, i.e. the exposed diameter of the underlying conductive substrate (DIB
) by providing a tapered portion 5 at the bottom of the contact hole 3B, the opening diameter (D!A) in the deep contact hole 3A and the exposed diameter of the underlying conductive substrate (D+A) relative ratio (D, A/D
! A) Make it smaller.

When the conductor layer is selectively grown in vapor phase in this way, the first
In the nucleation process shown in Figure (a), the number of growth nuclei 104 in the deep contact hole 3A is smaller than that in the shallow contact hole 3B because the nucleation in the selective vapor phase epitaxy is rate-determined by the surface reaction and the density of nucleation is constant. The number of growth nuclei 104 is greater than the number of growth nuclei 104.

As shown in FIG. 1(b), while the conductive layer 4 is grown in the tapered portion 5 corresponding to the exposed diameter (DIB) of the underlying conductive substrate in the shallow contact hole 3B, The deposition thickness (ta+) is approximately equal to the deposition thickness (tA+) in the deep contact hole 3B.

Then, as shown in FIG.
Growth also progresses in the lateral direction at the point when the growth exceeds 1, and in this process, the deposition rate of the conductor layer 4 in the upward direction in the shallow contact hole 3B is lower than that of the conductor layer 4 in the deep contact hole 3A.
It lags significantly behind the upward deposition rate.

Then, as shown in FIG. 1 (dl), when the growth progresses further and the deposited conductor layer 4 covers the entire bottom of the contact hole 3B, the conductor layer 4 is deposited upward in the shallow contact hole 3B. The speed is deep contact hole 3A
is equal to that of

As a result, by appropriately selecting the relative ratio between the opening diameter of the shallow contact hole and the exposed diameter of the conductive substrate at the bottom,
For example, the apparent deposition rate in a deep straight contact hole 3A and a shallow contact hole 3B is changed, and the top surface of the conductor layer 4 buried in each contact hole 3A, 3B and the top surface of the surrounding insulating film 2 are changed. It becomes possible to form minute steps d+ and d2 with no large difference.

The apparent deposition rate can also be changed by changing the material of the underlying conductive substrate exposed at the bottom of the contact hole.

Figure 2 shows the case where the underlying conductive substrate is silicon (Si) (
W layer growth time and embedding thickness (curve A) and tungsten silicide (WSiz) case (curve B)
As can be seen in this figure, when WSi2, which has a slow formation rate of growth nuclei, is used as the growth substrate, the growth rate increases during the nucleation process at the beginning of growth. The difference in thickness caused by the delay is maintained until the growth for a predetermined period of time is completed. Therefore, by using a substance with a slow nucleation rate in the underlying conductive substrate under the shallow contact hole and a substance with a fast nucleation rate in the underlying conductive substrate under the deep contact hole, it is possible to achieve the above-mentioned aspect of the present invention. Similarly to the method, the steps at the top of the shallow contact hole and deep contact hole after embedding the conductor layer are
It becomes possible to form minute steps with no significant difference.

As described above, the steps above the contact holes having different depths formed on the same substrate are made uniform to minute steps, so that the coverage of the wiring metal film is improved and step breaks in the wiring are prevented.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

3(a) to 3(e) are process sectional views of one embodiment of the method of the present invention, and FIGS. 4(a) to 4(b) are process sectional views of another embodiment of the method of the present invention. It is a diagram.

Identical objects are indicated by the same reference numerals throughout the figures.

Refer to FIG. 3(a) By applying the method of the present invention, for example, a semiconductor device having a multilayer wiring structure having a second layer wiring connected to the semiconductor substrate surface and a second layer wiring connected to the first layer wiring is manufactured. When forming, for example, the first and second impurity diffusion regions 12A, 12
On the Si substrate 11 on which B is formed, chemical vapor deposition (CV
D) Silicon dioxide (S) with a thickness of about 5000
An iO□) lower layer insulating film 13 is formed, and then a contact hole 14 exposing, for example, the second impurity diffusion region 12B is formed in this SiO□ lower layer insulating film 13 by ordinary photolithography, and the thickness is about 3000 mm. By performing vapor phase growth of a poly-Si layer, introducing impurities into this poly-Si layer, and patterning, the poly-Si lower layer is led out from above the first impurity diffusion region 12B to the SiO2 lower layer insulating film 13 through the contact hole 14. Wiring 15 is formed, and then thermal oxidation is applied to the surface of poly-Si lower layer wiring 15 to a thickness of 500 mm.
After forming a thermally oxidized Si0□ film 16 with a thickness of 0, a thickness of 500
The interlayer insulating film 17 is formed by about 02VD-3iO□.

Refer to FIG. 3(b) Next, on the substrate, a portion where a shallow contact hole for the poly-Si lower layer wiring 15 is to be formed is etched to a diameter of about 1/2 of the upper opening diameter of the contact hole, for example, about 0.5 μm. A first resist film 18 having a window 19 is formed, and a CVD-3iO□ interlayer insulating film 17 and thermally oxidized Si are etched in alignment with the etching window 19 by reactive ion etching (RIE) using fluorine gas.
A tapered opening 20 having a diameter of about 0.5 μm is formed to penetrate the O 2 film 16 and expose the surface of the poly-Si lower layer wiring 15 .

Refer to FIG. 3fc) Next, using the resist film 18 as a mask, the side surface of the tapered hole 20 is etched again by wet etching with dilute hydrofluoric acid to a predetermined depth having an opening diameter of about 1 μm. A shallow contact hole 21B of about 5500λ is formed. At this time, the thermally oxidized SiO□ film 16, which has a slow etching rate, is hardly etched.
The opening 20 for the tapered portion is only formed into a tapered shape as shown in the figure, and the opening diameter at the bottom remains unchanged.

Refer to FIG. 3(d) Next, after removing the first resist film 18, a second resist film 2 is formed on the substrate, which has an etching opening 23 with a diameter of about 1 μm at a location where a deep contact hole is to be formed.
2 and RIE using this resist film 22 as a mask.
The CVD-3i02 interlayer insulating film 17 and the thermally oxidized SiO□ film 16 below it are removed to expose the first impurity diffusion region 12A with a diameter of about 1 μm and a depth of 100001 μm.
A contact hole 21A with a certain depth is formed.

Refer to FIG. 3(e) Next, a conventional selective vapor phase growth method of W by reduction of silane is used, for example, tungsten hexafluoride (WFa):monosilane (SiHa):hydrogen (H2)=7:4.9
: 0 of the growth gas with a composition of 1000[SCCM]
．． In an atmosphere with a pressure of about 2 Torr, 250~
Selective vapor phase growth of W was performed at about 300° C. for 2 minutes. Through this vapor phase growth, a 0W buried layer 24A with a thickness of about 3,600 layers is buried in the deep contact hole 21A with a depth of about 100 layers, and a 0W layer 24A with a thickness of about 2,000 layers is buried in the shallow contact hole 21B with a depth of about 5,500 layers. The layer 24B is deposited, and the step from the top surface of the buried layers 24A and 24B to the top surface of the CVD-3iO□ interlayer insulating film 17 around the contact hole is a deep contact hole 17.
Approximately 6,400 people attended the A section, and approximately 3,500 people attended the shallow contact hole 17B section. As a result, in order to avoid overflow of the buried layer in the shallow contact hole portion due to variations in the growth rate, the conventional method was used to fill the shallow contact hole 2IB with a 2,000-layer thick W layer as in the above embodiment.
8 formed above the buried layer in the deep contact hole 21B in which a W layer of similar thickness is buried when the layer is buried.
Compared to the step difference of 000 people, the step difference is 1600 people, or 20
%, and the difference in the step between the shallow contact hole and the deep contact hole was reduced by about 35% compared to the conventional method.

In addition, in the method of the above embodiment, the opening diameter of the tapered portion formed at the bottom of the shallow contact hole 21B is further reduced, so that the apparent deposition rate of the upper buried layer in the shallow contact hole and the deep contact hole is reduced. By increasing the difference, the effect of reducing the step difference in the deep contact hole 21A portion can be further enhanced.

Refer to FIG. 4(a) Furthermore, in another method according to the present invention, for example, the first
S having second impurity diffusion regions 12A and 12B
A 0WS12 lower layer wiring 25 having a thickness of, for example, about 2000 layers is formed on the contact hole 14 that exposes, for example, the second impurity diffusion region 12B formed in the SiO□ lower layer insulating film 13 on the i-substrate ll, and this lower layer wiring is formed. Thickness 50 on the surface
A CVD-3iO□ interlayer insulating film 17 is formed, and then the CVD-3i02 interlayer insulating film 17 is penetrated to expose the WSi and lower wiring 25 to a depth of about 5000.
A contact hole 26B having a depth of about 10,000 mm and a deep contact hole 26A penetrating the CVD-3iO□ interlayer insulating film 17 and the 5in2 lower layer insulating film 13 to expose the first impurity diffusion region 12A are simultaneously formed.

Refer to FIG. 4(b). Then, similar to the above example, for example, WFs:SiH
4: H2= 7: 4.9: 1000 [S
Selective vapor phase growth of W was carried out for 3 minutes at a temperature of about 250 to 300° C. in an atmosphere of a growth gas having a composition of CCM) at a pressure of about 0.2 Torr. As a result, the thickness of the shallow contact hole 26B is approximately 3,700 mm.
A W buried layer 24B is formed and a deep contact hole 2 is formed.
An 0C buried layer 24A with a thickness of about 5,000 layers is formed in the shallow contact hole 26B in consideration of overflow of the buried layer from the shallow contact hole due to variations in growth rate using the conventional method. 370
When filling the buried layer with a return limit of about 0 people, compared to the 6,300 level difference formed on the buried layer of a deep contact hole that is filled with a buried layer of the same thickness at the same time, the level difference is 130OA, that is, 20%. The step difference between the shallow contact hole and the deep contact hole was also reduced by about 25% compared to the conventional method.

Note that the method of the present invention is not limited to the above-mentioned embodiments, and similar effects can be obtained even when a high-melting point metal other than copper or W, or a silicide of a high-melting point metal is used in the buried layer.

〔Effect of the invention〕

As explained above, according to the present invention, a conductive layer is simultaneously buried in a shallow contact hole and a deep contact hole formed on the same substrate by selective vapor phase growth, and then a conductive layer is formed above the shallow contact hole. The difference between the step formed above the deep contact hole and the step formed above the deep contact hole can be reduced compared to the conventional method, and can be formed into a minute step with no significant difference.

Therefore, the present invention has the effect of preventing a decrease in yield and reliability due to disconnection of wiring in manufacturing a semiconductor device or the like having a multilayer wiring structure having contact holes of different depths.

[Brief explanation of drawings]

1(a) to 1(d) are process cross-sectional views for explaining the principle of the present invention, FIG. 2 is a relationship between the growth time of W and the embedding thickness when the underlying conductive substrate is Si and WSi2, and FIG. Figures (a) to f
e) is a process cross-sectional view of one embodiment according to the method of the present invention, and FIGS. Conductive base, 2 is an insulating film, 3A is a deep contact hole, 3B is a shallow contact hole, 4 is a conductive layer, 5 is a tapered part, 104 is a growth nucleus, D3A and D3B are upper opening diameters of the contact hole, D
IA and D+a are the exposed diameters of the underlying conductive substrate, and j A+ and t 81 are the deposition thicknesses. (B) (W) A Invention α 佇KO Theory - Use Q'1 Ichizu Diagram (Part 2) (B) (B) (Lottery 2
Figure 1 (Part 1) - Xa, Q Fs'l (rn; n)
T road series 1, h1 rest hS1 and "WSiz's 4th ηW growth J Haruma and buried υ thickness Zano Seki 1,000 p. Drawing diagram (Part 1)
Nio 7 cut tfllla Yutoaki's 2) 4 Ii light, direction 67 l', -4 unlight colored object image 1 Nio 1 tsubo σσD diagram

Claims (4)

[Claims] (1) When embedding a conductive layer in contact with the underlying conductive substrate at the bottom of the contact hole by selective vapor deposition only in the contact hole, the exposed area of the underlying conductive substrate at the bottom of the contact hole and the contact 1. A method of manufacturing a semiconductor device, comprising the step of controlling the filling speed of the conductor layer into the contact hole by relatively changing the ratio of the hole to the opening area. (2) When embedding a conductive layer in contact with the underlying conductive substrate at the bottom of the contact hole by selective vapor growth only in the contact hole, the material of the underlying conductive substrate exposed at the bottom of the contact hole is 1. A method of manufacturing a semiconductor device, comprising the step of controlling the filling speed of the conductor layer into the contact hole by changing the filling speed of the conductor layer into the contact hole. (3) simultaneously embedding a conductor layer in contact with the underlying conductive substrate at the bottom of the contact hole by selective vapor deposition into a plurality of contact holes of different depths formed in an insulating film on the same substrate; In a method for manufacturing a semiconductor device including a step of reducing a step difference between the contact hole portion and the upper surface of the insulating film, when forming the plurality of contact holes having different depths, 1. A method of manufacturing a semiconductor device, comprising the step of forming a ratio of exposed area of a transparent substrate to be smaller than the ratio of a deep contact hole. (4) simultaneously embedding a conductive layer in contact with the underlying conductive substrate at the bottom of the contact hole by selective vapor deposition into a plurality of contact holes of different depths formed in an insulating film on the same substrate; In a method of manufacturing a semiconductor device, which includes a step of reducing a step difference between the contact hole portion and the upper surface of the insulating film, a region of a base conductive substrate disposed below a shallow contact hole that is exposed at least at the bottom of the contact hole; A method for manufacturing a semiconductor device, comprising the step of forming the conductive material using a conductive material that has a slower growth nucleation rate during selective vapor growth than the underlying conductive substrate surface exposed at the bottom of the deep contact hole.