JPH0438592U - - Google Patents

Info

Publication number
JPH0438592U
JPH0438592U JP7872590U JP7872590U JPH0438592U JP H0438592 U JPH0438592 U JP H0438592U JP 7872590 U JP7872590 U JP 7872590U JP 7872590 U JP7872590 U JP 7872590U JP H0438592 U JPH0438592 U JP H0438592U
Authority
JP
Japan
Prior art keywords
time data
set time
subtraction
flowchart
storage means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7872590U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7872590U priority Critical patent/JPH0438592U/ja
Publication of JPH0438592U publication Critical patent/JPH0438592U/ja
Pending legal-status Critical Current

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  • Measurement Of Predetermined Time Intervals (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例に係わる電子腕時計
の外観図、第2図は上記電子腕時計の内部回路を
示すブロツク図、第3図はRAM13の主要な内
部構成図、第4図はプログラム全体の流れを示す
フローチヤート、第5図は第4図のフローチヤー
トのステツプSA6のタイマ処理を詳述するフロ
ーチヤート、第6図は第4図のフローチヤートの
ステツプSA4のキー処理を詳述するフローチヤ
ート、第7図はモードをまとめて説明する図、第
8図はタイマモードの際の表示の例を示す図であ
る。 1……腕時計ケース、2……液晶表示装置、1
0……制御部、11……ROM、12……キー入
力部、13……RAM、14……発振器、15…
…分周回路、16……タイミングジエネレータ、
18……表示部、S1,S2,S3,S4,S5
,S6……スイツチ。
Figure 1 is an external view of an electronic wristwatch according to an embodiment of the present invention, Figure 2 is a block diagram showing the internal circuit of the electronic wristwatch, Figure 3 is a diagram of the main internal configuration of the RAM 13, and Figure 4 is a program. Flowchart showing the overall flow; FIG. 5 is a flowchart detailing the timer processing in step SA6 of the flowchart in FIG. 4; FIG. 6 is a flowchart detailing the key processing in step SA4 in the flowchart in FIG. 4. FIG. 7 is a diagram for explaining the modes collectively, and FIG. 8 is a diagram showing an example of the display in the timer mode. 1...Watch case, 2...Liquid crystal display device, 1
0...control unit, 11...ROM, 12...key input unit, 13...RAM, 14...oscillator, 15...
...Frequency divider circuit, 16...Timing generator,
18...Display section, S1, S2, S3, S4, S5
, S6...Switch.

Claims (1)

【実用新案登録請求の範囲】 複数の設定時間データを記憶する記憶手段と、 該記憶手段が記憶する複数の設定時間データの
中から任意の設定時間データを選択する選択手段
と、 該選択手段により選択された設定時間データを
減算する減算手段と、 該減算手段により減算された設定時間データを
表示する表示手段とを有することを特徴とするタ
イマ装置。
[Scope of Claim for Utility Model Registration] Storage means for storing a plurality of set time data; selection means for selecting arbitrary set time data from among the plurality of set time data stored by the storage means; and by the selection means. A timer device comprising: subtraction means for subtracting selected set time data; and display means for displaying the set time data subtracted by the subtraction means.
JP7872590U 1990-07-26 1990-07-26 Pending JPH0438592U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7872590U JPH0438592U (en) 1990-07-26 1990-07-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7872590U JPH0438592U (en) 1990-07-26 1990-07-26

Publications (1)

Publication Number Publication Date
JPH0438592U true JPH0438592U (en) 1992-03-31

Family

ID=31622248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7872590U Pending JPH0438592U (en) 1990-07-26 1990-07-26

Country Status (1)

Country Link
JP (1) JPH0438592U (en)

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