JPS6376955U - - Google Patents

Info

Publication number
JPS6376955U
JPS6376955U JP16858586U JP16858586U JPS6376955U JP S6376955 U JPS6376955 U JP S6376955U JP 16858586 U JP16858586 U JP 16858586U JP 16858586 U JP16858586 U JP 16858586U JP S6376955 U JPS6376955 U JP S6376955U
Authority
JP
Japan
Prior art keywords
order
data
storage means
switch
changing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16858586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16858586U priority Critical patent/JPS6376955U/ja
Publication of JPS6376955U publication Critical patent/JPS6376955U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Calculators And Similar Devices (AREA)
  • Electric Clocks (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の回路ブロツク図、
第2図は上記実施例の時計の外観を示す平面図、
第3図はRAMの記憶内容を示す説明図、第4図
は上記実施例の時計の全体の動作を示すフローチ
ヤート、第5図は本考案の要部動作を示すフロー
チヤート、第6図は表示部に表示されるデータの
変化を示す説明図である。 1……時計本体、2……表示部、3……発振回
路、4……分周回路、8……ROM、9……入力
部、11……RAM、S〜S……スイツチ。
FIG. 1 is a circuit block diagram of an embodiment of the present invention.
FIG. 2 is a plan view showing the appearance of the watch of the above embodiment;
FIG. 3 is an explanatory diagram showing the memory contents of the RAM, FIG. 4 is a flowchart showing the overall operation of the clock of the above embodiment, FIG. 5 is a flowchart showing the main operation of the present invention, and FIG. FIG. 6 is an explanatory diagram showing changes in data displayed on the display unit. DESCRIPTION OF SYMBOLS 1... Watch body, 2... Display section, 3... Oscillation circuit, 4... Frequency division circuit, 8... ROM, 9... Input section, 11... RAM, S1 to S5 ... Switch.

Claims (1)

【実用新案登録請求の範囲】 順序が決められている複数のデータを記憶する
データ記憶手段と、 この記憶手段の複数のデータのうち表示すべき
データの順序を記憶する順序記憶手段と、 この順序記憶手段に記憶されている順序のデー
タを読出して表示する表示手段と、 1回の操作毎に前記順序記憶手段の順序を所定
数づつ変更するスイツチと、 このスイツチが1回操作される毎に変更される
数を変更する手段とを有することを特徴とするデ
ータ記憶表示装置。
[Claims for Utility Model Registration] A data storage means for storing a plurality of data in a predetermined order; an order storage means for storing the order of data to be displayed among the plurality of data in the storage means; and this order. a display means for reading out and displaying data in the order stored in the storage means; a switch for changing the order of the order storage means by a predetermined number each time the switch is operated; and means for changing the number to be changed.
JP16858586U 1986-10-31 1986-10-31 Pending JPS6376955U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16858586U JPS6376955U (en) 1986-10-31 1986-10-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16858586U JPS6376955U (en) 1986-10-31 1986-10-31

Publications (1)

Publication Number Publication Date
JPS6376955U true JPS6376955U (en) 1988-05-21

Family

ID=31101597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16858586U Pending JPS6376955U (en) 1986-10-31 1986-10-31

Country Status (1)

Country Link
JP (1) JPS6376955U (en)

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