JPH0438583U - - Google Patents
Info
- Publication number
- JPH0438583U JPH0438583U JP7960090U JP7960090U JPH0438583U JP H0438583 U JPH0438583 U JP H0438583U JP 7960090 U JP7960090 U JP 7960090U JP 7960090 U JP7960090 U JP 7960090U JP H0438583 U JPH0438583 U JP H0438583U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- current source
- constant current
- voltage
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
Description
第１図は本考案の一実施例を示す回路構成図、
第２図は第１図の回路のタイムチヤート図、第３
図は他の実施例を示す回路構成図、第４図は本考
案を適用するスイツチ回路の概念図、第５図は従
来の回路構成図、第６図は従来例によるタイムチ
ヤートである。
１……第１の定電流源、２……第２の定電流源
、３……ノツト回路、４……アンド回路、ＣＬ…
…負荷容量、Ｑ１，Ｑ２，Ｑ３，Ｑ４……ＦＥＴ
、Ｄ１……ダイオード。
FIG. 1 is a circuit diagram showing an embodiment of the present invention;
Figure 2 is a time chart of the circuit in Figure 1, and Figure 3 is a time chart of the circuit in Figure 1.
4 is a conceptual diagram of a switch circuit to which the present invention is applied, FIG. 5 is a conventional circuit diagram, and FIG. 6 is a time chart according to the conventional example. DESCRIPTION OF SYMBOLS 1...First constant current source, 2...Second constant current source, 3...Knot circuit, 4...AND circuit, CL...
...Load capacity, Q 1 , Q 2 , Q 3 , Q 4 ...FET
, D 1 ... diode.
Claims (1)
ンオフする第１のＦＥＴと、この第１のＦＥＴの
オンオフに応じて流れる第１の定電流源からの電
流に関連してバイアス電圧を重畳した高電圧パル
ス入力をスイツチングする第２のＦＥＴと、前記
第１のＦＥＴに連動し前記第２のＦＥＴがオフ時
にのみ出力をシヤントする第３のＦＥＴと、前記
第１のＦＥＴとグランドの間に設けた第２の定電
流源とを有し、前記第１の定電流源の電流より前
記第２の定電流源の電流を大とするとともに、前
記第２のＦＥＴがオフとなり前記バイアスの立下
がり電圧が変化して所定の電圧になつたとき前記
第３のＦＥＴをオンにする手段を具備したことを
特徴とするスイツチ回路。 A first FET that is turned on and off in relation to the high or low level of a control signal, and a high voltage with a bias voltage superimposed in relation to the current from a first constant current source that flows in response to the on and off of this first FET. a second FET that switches pulse input; a third FET that operates in conjunction with the first FET and shunts the output only when the second FET is off; and a third FET that is provided between the first FET and ground. a second constant current source, the current of the second constant current source is made larger than the current of the first constant current source, the second FET is turned off, and the falling voltage of the bias is A switch circuit comprising means for turning on the third FET when the voltage changes to a predetermined voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7960090U JPH0438583U (en) | 1990-07-26 | 1990-07-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7960090U JPH0438583U (en) | 1990-07-26 | 1990-07-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438583U true JPH0438583U (en) | 1992-03-31 |
Family
ID=31623903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7960090U Pending JPH0438583U (en) | 1990-07-26 | 1990-07-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438583U (en) |
-
1990
- 1990-07-26 JP JP7960090U patent/JPH0438583U/ja active Pending