JPH0438139U - - Google Patents
Info
- Publication number
- JPH0438139U JPH0438139U JP7999390U JP7999390U JPH0438139U JP H0438139 U JPH0438139 U JP H0438139U JP 7999390 U JP7999390 U JP 7999390U JP 7999390 U JP7999390 U JP 7999390U JP H0438139 U JPH0438139 U JP H0438139U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- variable resistance
- voltage dividing
- digital variable
- resistance block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
従来の並列比較形Ａ／Ｄコンバータの回路図、第
３図は従来の並列比較形Ａ／Ｄコンバータでゼロ
スケールオフセツトを補正する際の回路図である
。
１……デコーダ、２〜８……コンパレータ、９
……電圧分割用抵抗（3/2Ｒ）、１０〜１５……
電圧分割用抵抗（Ｒ）、１６〜２０……デイジタ
ル可変用抵抗、２１……基準抵抗、２２，２３…
…トランジスタ、２４〜２９……アナログスイツ
チ、３０……抵抗コントローラ、３１……コント
ローラ、３２……ＶＤＤ端子、３３……Ｖｉｎ端
子、３４……ＶＲＥＦ端子、３５……ＧＮＤ端子
、３６……ＢＯ端子（デイジタル出力０ビツト目
）、３７……Ｂ１端子（デイジタル出力１ビツト
目）、３８……Ｂ２端子（デイジタル出力２ビツ
ト目）、３９……比較信号ライン、４０……コン
トロール端子、４１……デイジタル可変抵抗ブロ
ツク、４２……コントロール信号ライン、４３…
…電圧分割用抵抗（1/2Ｒ）、４４……可変抵抗
、４５……オフセツトＧＮＤ端子（可変抵抗４２
によりゼロスケールオフセツトを補正した場合）
、４６……基準電圧源。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional parallel comparison type A/D converter, and Fig. 3 is a circuit diagram of a conventional parallel comparison type A/D converter. FIG. 4 is a circuit diagram for correction. 1...Decoder, 2-8...Comparator, 9
...Voltage division resistor (3/2R), 10 to 15...
Voltage division resistor (R), 16-20... Digital variable resistor, 21... Reference resistor, 22, 23...
...Transistor, 24-29...Analog switch, 30...Resistance controller, 31...Controller, 32...VDD terminal, 33...Vin terminal, 34...VREF terminal, 35...GND terminal, 36...BO Terminal (digital output 0th bit), 37...B1 terminal (digital output 1st bit), 38...B2 terminal (digital output 2nd bit), 39...comparison signal line, 40...control terminal, 41... ...Digital variable resistance block, 42...Control signal line, 43...
...Voltage dividing resistor (1/2R), 44...Variable resistor, 45...Offset GND terminal (variable resistor 42
(When zero scale offset is corrected by
, 46...Reference voltage source.
Claims (1)
電圧分割用抵抗と、電圧分割用抵抗の各接続点か
らの基準電圧と変換対象のアナログ電圧とが入力
される複数のコンパレータとを備えたＡ／Ｄコン
バータにおいて、前記電圧分割用抵抗の最低電圧
側に設けられて抵抗値を段階的に変更できるデイ
ジタル可変抵抗ブロツクと、前記電圧分割抵抗及
びデイジタル可変抵抗ブロツクと並列に設けた基
準抵抗に電流を供給する定電流源と、前記基準電
圧の入力端子及び前記アナログ電圧の入力端子と
前記コンパレータの入力端との間にそれぞれ設け
られて前記電圧分割用抵抗と前記コンパレータと
に前記低電流源から同一値の電流を供給し得るス
イツチと、ゼロスケールオフセツト補正の指令信
号により起動して前記スイツチを介して定電流源
から供給される電流に基づく所定のコンパレータ
の比較結果が所定値以下になるまでスイツチを当
該状態に保持すると共に前記デイジタル可変抵抗
ブロツクの抵抗値を変化させるコントローラとを
備えたことを特徴とするＡ／Ｄコンバータ。 A comprising a plurality of voltage dividing resistors connected in series to which a reference voltage is applied, and a plurality of comparators to which the reference voltage from each connection point of the voltage dividing resistors and the analog voltage to be converted are input. In the /D converter, a digital variable resistance block is provided on the lowest voltage side of the voltage dividing resistor and can change the resistance value in stages, and a reference resistor is provided in parallel with the voltage dividing resistor and the digital variable resistance block. a constant current source that supplies a voltage from the low current source to the voltage dividing resistor and the comparator, and is provided between the reference voltage input terminal, the analog voltage input terminal, and the input terminal of the comparator, respectively. A comparison result between a switch capable of supplying the same value of current and a predetermined comparator based on the current supplied from a constant current source via the switch activated by a zero scale offset correction command signal becomes less than a predetermined value. 1. An A/D converter comprising: a controller that maintains the switch in the relevant state until the end of the digital variable resistance block and changes the resistance value of the digital variable resistance block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7999390U JPH0438139U (en) | 1990-07-26 | 1990-07-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7999390U JPH0438139U (en) | 1990-07-26 | 1990-07-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438139U true JPH0438139U (en) | 1992-03-31 |
Family
ID=31624656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7999390U Pending JPH0438139U (en) | 1990-07-26 | 1990-07-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438139U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6885364B1 (en) | 1999-09-11 | 2005-04-26 | Sony Computer Entertainment Inc. | Control apparatus and outputting signal adjusting method therefor |
-
1990
- 1990-07-26 JP JP7999390U patent/JPH0438139U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6885364B1 (en) | 1999-09-11 | 2005-04-26 | Sony Computer Entertainment Inc. | Control apparatus and outputting signal adjusting method therefor |
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