JPH0438137U - - Google Patents

Info

Publication number
JPH0438137U
JPH0438137U JP8054090U JP8054090U JPH0438137U JP H0438137 U JPH0438137 U JP H0438137U JP 8054090 U JP8054090 U JP 8054090U JP 8054090 U JP8054090 U JP 8054090U JP H0438137 U JPH0438137 U JP H0438137U
Authority
JP
Japan
Prior art keywords
counter
overflow
exclusive
underflow
bit state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8054090U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8054090U priority Critical patent/JPH0438137U/ja
Publication of JPH0438137U publication Critical patent/JPH0438137U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の構成図、第2図は
第1図のカウンタの動作説明図、第3図は従来に
おけるアツプダウンカウンタの構成例を示した図
、第4図は第3図のカウンタの動作説明図である
。 2……カウンタ、3……排他的論理和ゲート。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the counter shown in FIG. 1, FIG. 3 is a diagram showing an example of the structure of a conventional up-down counter, and FIG. FIG. 4 is an explanatory diagram of the operation of the counter in FIG. 3; 2...Counter, 3...Exclusive OR gate.

Claims (1)

【実用新案登録請求の範囲】 オーバーフローとアンダーフローを検出する機
能をもつたアツプダウンカウンタにおいて、 カウンタのMSBのビツト状態とMBSよりも
1桁だけ下位にあるビツトのビツト状態を排他的
論理和をとる排他的論理和ゲートを有し、この排
他的論理和ゲートの出力レベルによりオーバーフ
ローまたはアンダーフローの発生を検出し、前記
MSBのビツト状態によりオーバーフローとアン
ダーフローを区別することを特徴とするアツプダ
ウンカウンタ。
[Claims for Utility Model Registration] In an up-down counter with a function of detecting overflow and underflow, the bit state of the MSB of the counter and the bit state of the bit one digit lower than the MBS are subjected to exclusive ORing. The up-down device is characterized in that it has an exclusive OR gate, detects the occurrence of overflow or underflow based on the output level of the exclusive OR gate, and distinguishes between overflow and underflow based on the bit state of the MSB. counter.
JP8054090U 1990-07-27 1990-07-27 Pending JPH0438137U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8054090U JPH0438137U (en) 1990-07-27 1990-07-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8054090U JPH0438137U (en) 1990-07-27 1990-07-27

Publications (1)

Publication Number Publication Date
JPH0438137U true JPH0438137U (en) 1992-03-31

Family

ID=31625698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8054090U Pending JPH0438137U (en) 1990-07-27 1990-07-27

Country Status (1)

Country Link
JP (1) JPH0438137U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02189026A (en) * 1989-01-17 1990-07-25 Mitsubishi Electric Corp Detector for overflow and underflow of counter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02189026A (en) * 1989-01-17 1990-07-25 Mitsubishi Electric Corp Detector for overflow and underflow of counter

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