JPH0438017B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a parallel processing computer, and in particular to a multiple instruction stream multiple data stream type ( MIMD
type) related to parallel processing computers.

[Background of the invention]

BACKGROUND ART Parallel processing computers that perform parallel processing using multiple processors have been developed in order to rapidly obtain numerical solutions for scientific and technical calculations, particularly partial differential equations. A typical example is ACM Transactionson
Computer Systeme, Vol 1, No. 3,
Auqust1983, p195−221 “PACS: Aparallel
Microprocessor Array for Scientific
Calculations”.

This computer connects adjacent processors and
It is a so-called close connection type in which array processors are arranged in a two-dimensional or two-dimensional array, and has the advantage of easy connection between processors, but has the disadvantage that it takes a long time to transfer data between distant processors.

Furthermore, since the processor arrangement is fixed in terms of hardware, there is a problem that calculation efficiency deteriorates depending on the problem to be processed, as shown in the following example.

(1) When processing a one-dimensional problem (for example, ∂φ/∂t=∂ ² φ/∂x ² ) with a two-dimensional array processor, use a processor with only one row or one column as shown in Figure 2a. However, it is common to allocate calculation grid points as shown in FIG. In the former case, processor 1
The number of grid points handled by each platform increases, and the calculation time increases. In the latter case, since the data transfer direction differs depending on the location of the processor, extra processing time is required for this determination.

(2) Two-dimensional calculation (e.g. ∂φ/∂t=∂ ² φ/∂x ² +∂ ²
The processing using the φ/∂y ² explicit difference decomposition method requires a longer processing time because the number of data to be transferred is larger in a one-dimensional array processor than in a two-dimensional array processor. For example, if calculations for 16 x 16 grid points are processed by 16 one-dimensional array processors and 4 x 1 two-dimensional array processors, both processors handle calculations for 16 grid points, but the number of data transferred between adjacent processors is , there are 16 in a two-dimensional array and 32 in a one-dimensional array.

As mentioned above, even for the same problem, depending on the processor arrangement, the amount of data to be transferred or the amount of processing per processor may increase.If the processor arrangement is fixed, these problems cannot be solved. However, this resulted in a decrease in efficiency.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel processing computer that can form an optimal processor array depending on the problem to be processed in order to execute parallel processing with high efficiency.

[Summary of the invention]

A feature of the present invention is that in a parallel processing computer in which a plurality of processors are arranged in a two-dimensional array and the processors are connected in each row and column constituting the two-dimensional array, the processors in the plurality of rows or columns are arranged in a row-by-row manner. Alternatively, a bus connection mechanism having a function of serially connecting each column is provided.

The present invention was made based on the following considerations.

When finding a numerical solution to a partial differential equation using parallel processing using multiple processors, data transfer between the processors is involved. Therefore, reducing the time required for data transfer leads to reducing the overall calculation time. Possible means for shortening the data transfer time include increasing the transfer speed and reducing the number of transferred data, but the present invention focuses on the latter reduction in the number of transferred data.

Figure 3 shows the two-dimensional Poisson equation ∂φ/∂t=∂ ² φ/∂x
Transfer between processor array and calculation grid point array when solving ² + ∂ ² φ/∂y ² (t: time, x, y: position in row, column direction, φ: variable to be sought) using explicit difference method This shows the number of data. In the part marked in parentheses in the same figure, the number of processor columns is greater than the number of calculation grid point columns, so even processors in the same row may take charge of calculation grid points in different rows, which makes it difficult to determine the data transfer destination. Requires extra processing. In other words, Figure 3 shows that even for the same problem, the number of transferred data changes depending on the processor arrangement, and processing other than the original calculation increases.M/N=m/n (M, N: Processor row) , number of columns, m, n: number of rows and columns of calculation grid points), the efficiency becomes better.

Therefore, in the present invention, in a two-dimensional array of processors, a function is provided to one-dimensionally connect processors in different rows or columns, and the number of data transferred between processors is minimized according to the lattice array of the applied problem. Arrays can now be changed.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a parallel processing computer according to the present invention. In Figure 1, P _i,j (i=1
~M, j=1~N) is a processor, S ₁ (i=1~
M-1) indicates a bus connection mechanism, and CU indicates a control processor. The processors P _i,j are arranged two-dimensionally, and adjacent processors in rows and columns are connected by row-direction and column-direction data transfer buses, respectively. The bus connection mechanism S _i is located between the processors in row i and the processors in row i+1, and is connected to the final processor P _i,N in row i and the first processor P _i+1,1 in row i+1 by a data transfer bus. Adjacent bus connection mechanisms (S _i , S _i-1 and S _i+1 ) are also connected by a data transfer bus.

The bus connection mechanism S _i has four bus input/output ports.
It connects and disconnects ports 1 to 4, and a block diagram is shown in FIG. In FIG. 4, 11 is a gate control circuit, and 21 to 24 are gate circuits. The gate circuits 21 to 24 have a function of electrically connecting the input and output lines when the gate control signals gc1 and gc2 are ON, and electrically insulating the input and output lines when the gate control signals gc1 and gc2 are OFF. The gate control circuit 11 turns on one of the gate control signals gc1 and gc2 in response to the bus connection control signal bc _i from the control processor CU.

When gate control signal gc1 is ON, gate circuits 21 and 22 are conductive, so port1 and
port3 and port2 and port4 are connected. Similarly, when gate control signal gc2 is ON, gate circuits 23 and 24 are conductive, and port1, port2, and port
3 and port4 are connected.

Here, from FIG. 1, port 1 of the bus connection mechanism S _i is connected to the processor in the i row and the last column, port 2 is connected to the data transfer bus of the processor in the i+1 row and first column, and ports 3 and 4 are connected to the bus connection mechanism S i. S _i-1 ,
It is connected to port 4 and port 3 of S _i+1 , respectively. Therefore, when the gate control signal gc1 is turned ON, the i-row and i+1-row processors are separated, and gc2 becomes
When ON, the processor in row i+1 is connected after the processor in row i and the last column, and row i and row i+1 are the same row.

Therefore, if the gate control signal gc1 is turned ON in all the bus connection mechanisms S _i to S _N1-1 , there will be no connection between rows, resulting in a two-dimensional array processor with M rows and N columns, and conversely, if gc2 is turned ON in all bus connection mechanisms, M because all rows are connected
×N one-dimensional array processors are formed. Furthermore, by connecting and disconnecting each bus connection mechanism S _i , various processor arrays can be formed.

Figure 5 shows an example of the configuration of a processor array. In this example, there are 4 rows and 4
The basic configuration is a two-dimensional array of columns, and three bus connection mechanisms S ₁ to _{S 3} are provided between each row. bus attachment
Assuming that when the bus connection control signal bc ₁ given to S _i is "0", the rows are separated, and when it is "1", the rows are connected, then the combination of the bus connection control signals bc _i given to each bus connection mechanism S _i is as follows: As shown in FIG. 5, processor arrays with complex shapes such as squares, rectangles, and uneven shapes can be formed.

However, since the connection of the data transfer bus in the column direction is always the same as the basic configuration: P _1,j →P _2,j →……→P _M,j →P _1,j , changing the processor arrangement The data transfer distance becomes longer. For example _, in the 2 _rows and 8 columns configuration _shown in _{FIG . 1} route is executed. However, if the method allows data transfer between distant processors to be performed easily and quickly, this will pose little problem in terms of program processing and time, and will essentially be treated the same as data transfer between adjacent processors. I can do it.

FIG. 6 specifically shows the bus connection mechanism S _i shown in FIG. 4 using a logic circuit. In FIG. 6, the bus connection control signal bc is composed of a connection signal cnc that specifies connection or disconnection between rows with "1" (connection) or "0" (disconnection), and a trigger signal trg that executes the connection or disconnection operation. FF is a D-type flip-flop, G1 to G4 are logic elements commonly called three-state buffers, and the gate control circuit 11 in FIG. ~24 are each 1
This can be realized extremely easily using a set of three-state buffers G1 to G4.

As described above, in the parallel processing computer of the present invention, the processor array is variable, and it is possible to form the most efficient processor array according to the lattice point array shape of the problem to be processed.

Although the above-mentioned embodiments have been shown in which a bus connection mechanism is provided in each row, it is clear that the same function can be obtained even if the bus connection mechanism is provided in each column. Furthermore, it is also possible to provide bus connection mechanisms for both rows and columns, and use them as needed depending on the application problem.

The control processor CU has a function of providing a bus connection control signal bc _i to each bus connection mechanism S _i . The simplest example of this is to provide a switch corresponding to each bus connection control signal bc _i , and manually control each bus connection mechanism.
It controls S _i . Alternatively, a processor and a digital signal output circuit may be used to determine the optimal processor array from the calculation grid point array, and the result may be used to provide the bus connection signal bc _i to the bus connection mechanism S _i via the digital signal output circuit. It is possible.

FIG. 7 shows an example of a calculation method for determining an optimal processor arrangement from a calculation grid point arrangement.
In this example, the number of calculation grid point rows and columns are m, n,
The number of rows and columns of the processors is M and N, and the number of grid points is greater than the number of processors. The specific steps are as follows.

(1) As initial values, find the matrix ratio a of the calculation grid point and the matrix ratio α of the processor, and set the number of arrangement changes I=0.

(2) Compare the calculated lattice point matrix ratio a and the processor matrix ratio α, and if a>α, update the number of array changes I to change the processor array, and change the processor matrix ratio α.

(3) Repeat (2) until a=α or a<α, and stop when α becomes equal to or greater than the number of processors.

(4) From the number of array changes I obtained in the above steps,
Create bus connection control signals. Considering binary data BC of M-1 bits, it is assumed that the lower bits become bus connection control signals to bus connection mechanisms S ₁ , S ₂ ...S _M-1 in order, and when it is "1", it is connected to the adjacent row. shall be taken as a thing.

Binary data BC is set as K = 2 ^I , and i K (i = 1, 2,
...) is created by setting one bit to "0" and setting the other bits to "1".

Next, an example of calculation by the parallel processing computer of the present invention will be shown.

(1) Two-dimensional problem Two-dimensional Poisson equation ∂φ／∂t＝∂ ² φ／∂x ² +∂ ² φ
/∂y ² (t: time, x, y: position in row and column directions, φ: variable to be sought) will be considered. That is, φ ^(k+1) _i,j = λφ ^(K) _i-1,j + (1-2λ)φ ^(K) _i,j +
λφ ^(K) _i+1,j +λφ ^(K) _i,j-1 + (1−2λ)φ ^(K) _i,j +λφ ^(K) _i,
j+1 (λ=Δt/Δx ² =Δt/Δy ² , Δt: time interval,
Δx, Δy: lattice point spacing, i, j: time representing the two-dimensional lattice arrangement, K: time step) are the boundary conditions φ ^(K) _p,j = C ^(K) _p,i , φ ^(K) _n+1,j ＝C ^(K) _n+1,j φ ^(K) _i,p ＝C ^(K) _i,p ，φ ^(K) _i,o+1 ＝C ^(K) _1,o+1 , and calculate φ _i, j at each grid point i,j.

Here, the number of processors is assumed to be 256, and the basic configuration M rows and N columns is 16 rows and 16 columns. Also, consider 16 rows and 256 columns of calculation grid points. The specific calculation procedure is shown below.

(i) Before executing the calculation of φ _i,j, the control processor
Change the processor array using the CU using the procedure described above. Since the matrix ratio of calculation grid points is 256/16=16 and the processor matrix ratio is 1, according to the calculation method described above, the number of times the arrangement is changed is 2, and the processor arrangement is changed to 4 rows and 64 columns. As a result, the lattice point array for which each processor is responsible for calculations has four rows and four columns.

(ii) Each processor transfers a total of 16 edge data of the 4 rows and 4 columns of calculation grid point array to the adjacent processor. In other words, the subscript of the grid point is i′,
j′, φ ^(K) _i ′ _,1 (i′=1 to 4) is on the left, φ ^(K) _i
′ _,4 (i′=
1 to 4) to the right, φ ^(K) _1,j ′ (j′=1 to 4) to the top,
φ _4,j ′ (j′=1 to 4) is transferred to the processor below.

₍ iii ⁾ _Each processor calculates φ ^{(k+ 1)} Calculate _i ′ _,j ′.

(iv) Update k and repeat (ii) and (iii).

If this problem is executed without changing the processor array, each processor will calculate grid points of 1 row and 16 columns. Therefore, in this case, the number of data transferred between processors is 1 x 2 + 16 x 2 = 34
This is more than twice the calculation according to the present invention.

(2) One-dimensional problem One-dimensional problem with the same equation as above ∂φ/∂t=∂ ² φ/∂
Consider x ² . The number of processors is 256 with 16 rows and 16 columns.
The number of calculation grid points is 256, which is the same as the number of processors.

The calculation procedure is exactly the same as the two-dimensional problem, and is as follows.

(i) Change the processor array to 1 row and 256 columns. Each processor is responsible for one grid point.

(ii) Each processor transfers data φ ^(K) to the left and right processors.

(iii) Calculate φ ^(k+1) using data φ ^(K) of the self-processor and data from the left and right sides.

(iv) Update k and repeat (ii) and (iii).

When this problem is calculated without changing the processor arrangement, the grid points are assigned to each processor as shown in FIG. If only one row of processors is used as shown in Figure 2a, each processor will calculate 16 grid points, and it is clear that the calculation time will be significantly increased compared to the method of the present invention. . Furthermore, when the grid points are allocated as shown in FIG. 2b, the number of grid points handled by each processor is one, which is the same as in the present invention, but the data transfer direction is different between the center and the ends of each row. That is, data is transferred to the left and right processors at the center, but the processors at the left and right ends are transferred to the left or right, and above or below, depending on their position. Therefore, during data transfer processing, it is necessary to determine the position of the own processor and to determine the transfer direction based on this determination. Therefore, these increases in processing result in an increase in calculation time compared to the method of the present invention.

In the above embodiment, a plurality of bus connection mechanisms are provided, but by increasing the number of switching circuits in the bus connection mechanism, it is possible to connect processors in any number of rows or columns with one bus connection mechanism. A one-dimensional connection is also possible.

〔Effect of the invention〕

As described above, according to the present invention, the arrangement of processors can be changed according to the grid point shape of the applied problem, and the number of data transferred between processors can be minimized, thereby reducing the time required for data transfer. This has the effect of improving calculation efficiency.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of the parallel processing computer of the present invention, Figure 2 is an example of grid point assignment when processing a one-dimensional problem using a conventional parallel processing computer, and Figure 3 is based on the processor array and calculation grid point array. A table showing the difference in the number of transferred data, FIG. 4 is a block diagram showing the configuration of the bus connection mechanism in FIG. 1, FIG. FIG. 7 is a flowchart showing the processor array calculation procedure. P _ij ...processor, S _i ...bus connection mechanism, CU...control processor, 11...gate control circuit,
21 to 24...Gate circuit, bc _i ...Bus connection control signal, gc1, gc2...Gate control signal.

Claims (1)

[Scope of Claims] 1. In a parallel processing computer configured by arranging a plurality of processors in a two-dimensional array and connecting the processors in each row and column constituting the two-dimensional array, A parallel processing computer characterized by having a bus connection mechanism that has a function of serially connecting units or columns. 2. In the parallel processing computer according to claim 1, a plurality of the bus connection mechanisms are provided corresponding to each row or column, and each bus connection mechanism has an input/output terminal connected to a processor bus or other bus connection. A parallel processing computer comprising four switching circuits connected to a mechanism and a control circuit that controls opening and closing of each switching circuit. 3. In the parallel processing computer according to claim 2, the control circuit within the bus connection mechanism comprises 1
A parallel processing computer characterized in that opening and closing are controlled simultaneously by bus connection control signals from two control processors.