JPS6148033A - Memory address control circuit for table arithmetic - Google Patents

Abstract

PURPOSE:To heighten the generality by changing over control lines such as write enable line, address line and data line used for a table, by a multiplexer according to a designated mode. CONSTITUTION:Receiving an address signal from a data processor and a control signal of a various modes or the like, a memory address control circuit 2 feeds a memory address signal, data input signal and memory write enable signal and the like to a RAM1. The change-over of input and output of various signals by a data select circuit 3 is determined by a type of a table operation to be carried out. A mode select section 4 selects its operating mode by a control signal concerning a mode and stores it in, for example, an internal register. A data select control section 5 controls a data select circuit section 3 in accordance with a mode selected by the mode select section 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a table reference arithmetic circuit, and particularly to a RAM
This invention relates to a memory address control circuit for table calculations that makes it possible to control calculations based on various table references with a single circuit by efficiently controlling the addresses of randomly accessible memories (hereinafter referred to as random memories) such as ROM and ROM. It is something.

[Conventional technology and problems]

Recently, as memory has become cheaper and control can be made faster using an hour wheel, it has become increasingly common to perform various 6II arithmetic operations by referring to tables in memory. Particularly in the field of image quality processing, for example, the amount of data to be processed is large and high speed is required, so a variety of arithmetic circuits that refer to tables are used.

Conventionally, many table reference arithmetic circuits are constructed using random memories. However, since the random memory connection method is fixed, it is necessary to build different circuits depending on the calculation content.

Therefore, for example, density (level) conversion, pixel-to-pixel calculation, histogram calculation, etc., which are often used in image processing, etc.
Conventionally, in order to satisfy various calculations such as projection calculations, a plurality of circuits are required, which has the disadvantage of increasing the circuit scale.

[Means for solving problems]

The present invention aims to solve the above problems by connecting signal lines such as address lines, data lines, and write enable lines of a random memory (RAM or ROM) used as a table.
↑By switching with a multiplexer and controlling the data flow according to the specified mode, the same
- Provides a system that can implement various table operations using hardware circuits. That is, the table calculation memory address control circuit of the present invention is a table calculation memory address control circuit in a table reference calculation circuit using a random memory as a table, and includes an address line for a memory chip constituting the random memory, A data select circuit unit that selects and switches data lines and write enable lines, and one operation in a combination that includes at least two operations among density conversion, inter-pixel operation, histogram calculation, and projection operation. a mode selection section that selects based on a signal related to the mode; and a data selection control section that controls the data selection circuit section according to the mode indicated by the mode selection section and causes the random memory to input and output operation data corresponding to the selected mode. It is characterized by having the following. Hereinafter, embodiments will be described with reference to the drawings.

〔Example〕

Fig. 1 is a schematic configuration of an embodiment of the present invention, Fig. 2 is a diagram for explaining general table calculations, Fig. 3 is an illustration for explaining table calculations for density conversion, and Fig. 4 is a table for inter-pixel calculations. Figure 5 is a diagram for explaining table calculations for histogram calculation, Figure 6 is a diagram for explaining projection in image processing, Figure 7 is a diagram for explaining table calculations for projection, and Figure 8 is a diagram for explaining table calculations for histogram calculation.
Detailed block diagram of the illustrated memory address control circuit, No. 9
The figure is an explanatory diagram of control in density conversion/pixel-to-pixel calculation mode.
FIG. 10 is an explanatory diagram of control in histogram mode, FIG. 11 is an explanatory diagram of control in projection mode, FIG. 12 is an example of a memory address control chip that is an LSI version of the memory address control circuit shown in FIG. Figure 12 is an example of a concentration conversion calculation circuit using the illustrated chip;
An example of an inter-pixel calculation circuit using the illustrated chip, FIG. 15 shows an example of a histogram calculation circuit using the thousand knob shown in FIG. 12, and FIG. 16 shows an example of a projection calculation circuit using the chip shown in FIG. show.

First, before explaining the present invention in detail, 1. Referring to FIGS. 2 to 7, the table calculation method and the seven-degree conversion, inter-pixel calculation, histogram calculation, and projection calculation related to the present invention will be explained.

In the case of calculations using the so-called table reference method, Figure 2 (a)
As shown in the figure, when input data is input to a table in which calculation logic is stored in advance, calculation results corresponding to the input are output. In actual hardware, as shown in FIG. 2(b), a random memory 1 is used as a table, input data is applied to the address line, and output is obtained from the data line. If you need to change the contents of the table, use R as random memory 1.
If using AM and a table with fixed contents is sufficient, use R.
Use OM.

For example, when converting the density (level) of each pixel in image processing using a table calculation, there is a control unit for loading the table into memory, inputting data to the address line of the memory, and transmitting the calculation result to the data line. 2i11I of the control extracted from the control is required, that is, FIG.
b) As shown in the figure, the random memory 1 is set to an stale state using the write enable line, and table data corresponding to the address signal on the address line is supplied from the data line to initialize the table. Thereafter, by applying input data to the address line and reading out the contents of the random memory 1, the required output data can be obtained from the data line, as shown in FIG. 3(b). Note that when a ROM is used as the random memory 1, table load control is only necessary (the calculation control shown in FIG. 3(b)).

Figure 4 shows an example of inter-pixel calculations, for example, 8 bits, 8 pins, 1 pin.
16 bits of data is obtained from -. Initialization by table loading writes 16-bit data using a 16-bit address, as shown in FIG. 4(a). At the time of calculation, input data of each pixel is given to the upper 8 bits of the address line and the 8 bits of the lower address line, respectively, as shown in FIG. 4(b).
Obtain the /3i ¥ calculation result of 16 hinoto.

In image processing, for example, how many pixels have a density of "00"?
How many pixels have density "Ol", ..., density r F
Sometimes a histogram is required, such as how many pixels there are in FJ. Calculation of such a histogram requires control 3a as shown in FIGS. 5(a) to 5(c). That is, for the initial 1υI setting, the data line is set to "0" and all addresses in the memory are cleared, as shown in FIG. 5(a). And Figure 5 (
b) As shown in the figure, the contents of random memory 1 are read out using the density value of each pixel scanned sequentially as an address, and +1
The circuit C1 adds "1" and stores the result at the same address. When all pixels have been scanned, the number of density values can be obtained on the data line by applying the g degree value to the address line, as shown in FIG. 5(c).

For example, in pattern recognition in image processing, etc., a so-called projection /iO calculation is required. Projection is a process of sequentially adding data that meets certain conditions. For example, for a multivalued image memory GM with 8 bits per pixel as shown in FIG. 6, the sum of pixel data in the row direction or the pixel data in the column direction It is designed to find the sum of This operation is also the seventh
There are three types of control J11 as shown in the figure (a) to c).
Is required. FIG. 7(a) shows the initial 1-to-1 control for clearing. During calculation, as shown in Figure 7 (b),
Adder circuit A inserts an address in the row or column direction into the address line and adds the contents of that address and the input data of the pixel value.
Add by DD. Then, the addition result is stored at the same address. Finally, in Figure 7 () 1) /10 <
, the projection result can be obtained by specifying addresses in the row or column direction on the address lines.

As explained above, when performing table calculations, different controls are required for each input/output terminal of the memory chip of the random memory l. Therefore, conventionally, the scale of such a circuit has increased, but according to the present invention, as explained below, the above case can be controlled with a single control circuit.

FIG. 1 shows a schematic configuration of a table calculation circuit using the present invention. In the figure, 1 is a random memory such as RAM or ROM, 2 is a memory address control circuit according to the present invention, and 3 is a random memory 1. A data select circuit section 4 selects various modes of switching control for the data select circuit section 3, and a mode select section 1.5 selects the data select circuit section 3 according to the specification of the mode select section 4. It represents a data selection control section that supplies 11 signals in accordance with the control system.

The memory address control circuit 2 receives control signals such as a system address signal, a system data signal, a write enable signal, an input data signal, and various modes from a data processing device that is a host device or other hardware. A memory address signal, a data input number 1S, a memory write enable signal, etc. are supplied to the random memory 1. It also receives data output from the random memory 1.

The manual input and output switching of the various signals by the data selection circuit section 3 is determined by the type of table calculation to be performed. Mi-Ki Tatsumi jp:! <A! . Note that this mode includes a table load/initialization mode, a continuous calculation result mode, etc. as necessary. Data select ili'l? The J11 section 5 controls the data selection circuit section 3 according to the mode selected by the mode selection section 4.

FIG. 8 shows a detailed internal block diagram of the memory address control circuit 2 shown in FIG.

In the figure, 11 to 15 are multiplexers (MPX), 1
6 is a flip-flop (FF), 17 is a counter, 18
19 and 20 are adder circuits, 21 is an input cover sofa, 22 and 23 are output cover sofas, and 24 is a mode register.

The data selection circuit section 3 shown in FIG. 1 includes five multiplexers 11 to 15, one flip-flop 16, one +1 circuit 18, and two sets of adder circuits 19. 20, and these address AO-A7, input data PDO-PD7, system data DO-D7, and memory address MAO-MA?
, data output DOO~DO7, data human power DiO~Di
Performs switching of signals between T. This switching is performed by the data selection control section 5 sending out a selection signal and a timing signal according to the contents of the mote register 24 set by the mode selection section 4, as described below. An example of this control will be explained below with reference to FIGS. 9 to 11.

FIG. 9 shows a connection configuration related to control in the density conversion mode and the inter-pixel calculation mode. First, in table low F, the multiplexer 11 selects addresses AO to Δ7 and transfers them to memory addresses MAO to Δ7. M
A7, and the multiplexer 13 selects the system data DO~D7 and sends it to the data input DiO~D.
By sending data to i7, table data is written to random memory l.

Then, at the time of calculation, the input data PDO-PD7 is selected by the multiplexer 12, and the output thereof is supplied as the memory address MAO-MA7 via the multiplexer 11. As a result, input data PDO to PD7
The contents of the table in the random memory 1 having the address is output from the data outputs D00 to DO7 to the system data DO to D7 via the output sofa 22.

FIG. 1O shows a connection configuration related to control in the histogram mode. First, at initialization, multiplexer 11 selects addresses AO to A7, and multiplexer 13 selects system data DO to D7.

Therefore, by turning off the cover sofa 21,
“0” can be written to random memory 1.

During calculation, the multiplexer 12 inputs the input data PD
O to PD7 are selected, multiplexer 11 selects the output of multiplexer 12, multiplexer 14 selects the output of +1 circuit 18, and multiplexer 13 selects the output of multiplexer 14. As a result, input data PDO to PD7 are transferred to memory address MA.
Read the data from O to MA7, add 1 to the value,
The result is written to the same memory address MAO-MA7.

Furthermore, when saving the wasted results, multiplexer 11 selects addresses AO to A7 and outputs Hanofa 2.
2 to ON, data output D from random memory 1
Obtain OO-DO7.

FIG. 11 shows the connection configuration related to the control J11 in the projection mode. First, at initialization, remove multi-shake (1) selects address AO-A7, and multiplexer 13 selects system data DO to D7. . And then there is the hippo sofa 21.

In addition to clearing the random memory 1 as FF, the flip-flop 16 is sent through the multiplexer 15 to
()”.

When performing projection calculation, multiplexer 12 and counter 1
7, the multiplexer 11 selects the output of the multiplexer 12, the multiplexer 14 selects the output of the adder 19, the multiplexer 13 selects the output of the multiplexer 14, and the multiplexer 15 selects the output of the adder 1820. control to select. As a result, the value of counter 17 is transferred to memory address MAO-MΔ7.
The data output DOO-'DO7 is obtained, the value is added to the input data PDO-PD7, and the result is stored in the same memory address MAO-MA7.

At the same time, the value of the flip-flop 16 and the value of the manual data PDO to PD7 are added by the adder circuit 20, and the result is written into the flip-flop 16.

When saving the results of the projection calculation, multiplexer 11 transfers addresses AO to A7 to memory address MAO.
~MA7, the output Hanofa 22 is turned on, and the contents of the random memory l are read. Alternatively, by turning on the output sofa 23, the contents of the flip-flop 16 are read out.

By controlling as described above, one memory address control circuit 2 can support control circuits of arithmetic circuits in various modes.

This memory address;li control circuit 2 can be made into a one-chip LSI as shown in FIG. 12 by realizing circuits such as the multiplier shown in FIG. 8 by combining Hesynoxels. This memory address system 9
The J11 chip 30 has, for example, a 58-pin terminal as shown in the figure. In particular, memory addresses MAO to MA7, memory data manual input DiO to Di7, and memory data output DC
IO-DO7, memory write enable, is connected to random memory that stores the table.

In order to select the calculation mode and control type for one calculation, it is possible to provide multiple pins, or one terminal MOD
It is also possible to prepare only E and select the mote to be selected depending on the system addresses AO to A7.

This memory address control chip 30 performs control on an 8-bit basis, but in order to achieve 16-bit accuracy in histogram calculation, for example, a carry circuit such as +1 circuit 18 shown in FIG. In and carry-in 1- terminals Cin and Cout are provided.

FIG. 13 shows an example of an ink face for density conversion using the first printing tip 30. 8-bit parallel data can be obtained by memory addresses MAO to MA7 from the memory address control chip 30.

FIG. 14 shows the memory address control chip 7 shown in FIG. 12.
3 shows an example of an interface for inter-pixel calculations using the processor 30. I6 from two pixel data of each 8 bits
In order to be able to obtain the calculation result of the bit node, two memory address control wholesale chips 3 (1-1.30-2
has been established. The lower 8 bits are controlled by the memory address control chips 30 to 111, and the upper 8 bits are controlled by the memory address control chip 30-2.

FIG. 15 shows an example of a histogram calculation interface using the first medical chip 30. In order to make the histogram product 16 hinotes, a memory address control chip 3Q-1 and a 7 memory address control chip 30-2 are connected in cascade. Parallel 8-bit human power data Pl)
ONPD7 has 1000 knobs 30-1 for controlling both memory addresses.
．． 30-2. For example, when the histogram value corresponding to the density is further counted up from the upper limit [255], the carryout Cout signal from the chimp 30-1 for the memory address control 11 is
Carry-in C of memory address control chip 30-2
A chip 30-2 for memory address system i'Itl, which is dedicated to the in terminal, performs a counting operation.

FIG. 16 shows an example of an ink face for projection calculation using the first printing chip 30. The projection accuracy is 16 bits, random memory 1-1 is the lower hide, random memory 1-2 is
carries the value of the upper byte, and the carry-out Cout signal from the adder circuit 1 (not shown in FIG. , the memory address control chip 30-2 sets the upper hide value of the projection calculation to the corresponding address of the random memory 1-2.

Of course, the present invention is capable of controlling one of at least a plurality of /i11 calculation controllers jj8 for density conversion, pixel calculation, histogram calculation, projection operation, etc. by an external signal.
It suffices if it is capable of carrying out a large number of arithmetic and control functions, and any one of these can be selected as needed; it is not limited to one that performs all arithmetic control. Needless to say, there is no such thing.

〔Effect of the invention〕

As described above, according to the present invention, by using a control circuit that switches the address and data lines of a memory chip using a multiplexer, it is possible to configure a table reference calculation circuit that can handle various calculations, thereby making it possible to provide versatility. It is possible to provide a circuit with excellent performance, and it is possible to easily construct an arithmetic circuit of 3,11, and to reduce the circuit scale.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram of an embodiment of the present invention, Fig. 2 is a diagram for explaining general table calculations, Fig. 3 is a diagram for explaining table calculations for density conversion, and Fig. 4 is a diagram showing the 'i' between pixels. j”lj
'Jγ table calculation diagram, Figure 5 is a table calculation diagram for histogram calculation, Figure 6 is a diagram to explain projection in image processing, Figure 7 is a projection table calculation diagram, and Figure 8 is Fig. 1 is a detailed diagram of the memory address control circuit shown in Figure 1. 1 in mode
Lill? , llI explanatory diagram, FIG. 12 is an example of a memory address control chip in which the memory address control circuit shown in FIG. Figure 14 shows an example of an inter-pixel calculation circuit using the chip shown in Figure 12, Figure 15 shows an example of a histogram calculation circuit using the chip shown in Figure 12, and Figure 16 shows an example of a histogram calculation circuit using the chip shown in Figure 12.
The figure shows an example of a projection calculation circuit using the chip shown in FIG. 12. In the figure, ■ is a random memory, 2 is a memory address control circuit, 3 is a data selection circuit section, 4 is a mode selection section, 5
11 to 15 are multiplexers; 16 is a flip-flop; 17 is a counter; 18
19 and 20 are adder circuits, 21 is an input cover sofa, 22 and 23 are output cover sofas, and 30 is a memory address control chip. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Mori 1) Hirugu and 1 person) Sai 3 Figure 24 Tomoe 5 [! 1

Claims (1)

[Claims] A memory address control circuit for table operation in a table reference arithmetic circuit that uses random memory as a table, and a data select circuit section that selects and switches address lines, data lines, and write enable lines for memory chips constituting the random memory. a mode selection unit that selects one operation based on a mode signal from a combination including at least two or more operations among density conversion, inter-pixel calculation, histogram calculation, and projection calculation; a data selection control section that controls the data selection circuit section according to the mode indicated by the section and inputs/outputs operation data corresponding to the mode selected with respect to the random memory. circuit.