JPH0437673B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an inverter that obtains variable voltage and variable frequency output, and particularly relates to an inverter control device that is effective when a control section circuit is integrated into an integrated circuit.

[Technical background of the invention]

For example, when controlling the rotation speed of an AC motor to perform constant torque operation, it is possible to use a variable voltage, variable frequency power supply to control the motor speed while keeping the ratio of motor terminal voltage and frequency constant. It is done. In this case, an inverter is the most common variable voltage, variable frequency power source.

FIG. 1 shows the configuration of a typical three-phase bridge inverter main circuit 1. As shown in FIG. In this case, a transistor is used as the switching element,
Each arm of the three-phase bridge is connected to a transistor Tr ₁ ,
It consists of transistors Tr ₂ , Tr ₃ , Tr ₄ , Tr ₅ and Tr ₆ , and a flywheel diode D is connected between the collector and emitter of each of these transistors Tr ₁ to Tr ₆ . And transistors Tr ₁ and Tr ₄ ,
The mutual connection points of Tr ₂ and Tr ₅ and Tr ₃ and Tr ₆ are respectively output terminals T _U , _TV , and _TW , and these output terminals
A three-phase AC motor as a load is connected to T _U , _TV , and _TW . Furthermore, the inverter main circuit 1 with this configuration
is supplied with power from DC power supply 2, and the transistor
Tr ₁ to Tr ₆ are pulse width modulated (hereinafter simply PWM).
By adopting a switching method (referred to as a method), a three-phase AC output is obtained from the output terminals T _U , T _V , T _W , and the frequency is determined by each transistor.
It can be adjusted by changing the switching period of Tr ₁ to Tr ₆ . Note that 3 is a capacitor for smoothing DC power.

FIG. 2 shows a conventional inverter control circuit. To simplify the explanation, only one phase will be described. In Fig. 2, 4 is a frequency setting circuit that outputs a frequency setting signal _S1 for setting the output frequency f of the inverter main circuit 1, and this frequency setting signal S ₁ is applied to a rate multiplier 6 and a storage element, ie ROM (read only memory) 8. 5 is an oscillator for generating a clock signal _S2 which determines the output frequency f. The rate multiplier 6 is used to control the output voltage V of the inverter main circuit 1 to have a predetermined ratio relationship with the set frequency f, and divides the clock signal _S2 at a division ratio according to the frequency setting signal S1 _. A new clock signal S ₂ a is output by changing the frequency. 7 is the clock signal output from rate multiplier 6
This is a binary counter for forming a readout circuit that counts S ₂ a. The ROM 8 is adapted to receive the output from the binary counter 7 and the frequency setting signal S ₁ from the frequency setting circuit 4, and this ROM 8 has voltages corresponding to the set frequencies f ₁ to fn of the inverter main circuit 1. In this example, the predetermined logic pattern to obtain the data is stored for 180 degrees every 30 degrees, and the binary counter 7 reads out the ROM 8 with each 30 degrees as one cycle, and outputs 0 to the output terminals D ₀ to D ₅ . °~30°, 30°~60°, 60°~90°
,
90°~120°, 120°~150°, 150°~180° data signal
Output S ₄ . 9 is a hexadecimal counter that receives the carry signal _S3 from the binary counter 7;
8 to output a select signal S ₅ for causing the data selector 10 to select the data signal S ₄ . In this way, data selector 1
A signal _S6 corresponding to 0° to 180° in electrical angle is output to the output of 0 from the frequency setting circuit 4, that is, at a frequency corresponding to the set speed. 11 is an inverting circuit, which outputs a signal
A signal S ₇ conjugate to S ₆ is obtained, and the inverter main circuit 1
For transistor Tr ₁ , S ₆ is given, and for Tr ₄ , S ₇ is given, and S ₆ and S ₇ are given electrical angles of 180° to 360° for Tr ₄ and Tr _1, respectively. It becomes a signal of °.

[Problems with background technology]

According to this circuit configuration, in this example, the ROM 8 consists of 8 bits or 256 words of data for 180 degrees every 30 degrees, the speed setting is 6 bits or 64 steps, and 1 word is 8 bits, then 8 × 256
×64 and 128K bits will be used.

If, for example, the control section shown in the dashed-dotted line in Fig. 2 is to be integrated into an integrated circuit due to downsizing of equipment or economical demands, it would be difficult to integrate the ROM8 used if the control section is integrated with the same circuit configuration. Capacity is determined. On the other hand, the 30° worth of data stored in the ROM 8 consists of the pulse train Mo obtained by comparing the sine wave Sa and the triangular wave Sb, as shown in Fig. 3, into a predetermined number of words (256 words in this example). It has been quantified and applied. The larger the number of words, the closer it becomes to the pulse train obtained by comparing the sine wave and the triangular wave, and the output of the inverter main circuit 1 can obtain an AC waveform with less high frequency components. Depending on the quality of the characteristics of the motor being operated and the quality of rotation, economical constraints may force a reduction in the capacity of the ROM 8, that is, the number of words constituting 30 degrees worth of data.

However, as mentioned above, if this circuit configuration were to be integrated into an integrated circuit, the capacity of the ROM 8 would be limited to one, which would be uneconomical.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and its object is to provide an inverter control device that allows the capacity of a storage element to be varied to suit required motion characteristics.

[Summary of the invention]

The inverter control device of the present invention controls switching elements of the inverter main circuit on and off using data stored in storage elements in voltage patterns corresponding to each set frequency, thereby establishing a predetermined ratio relationship between frequency and voltage. In an inverter designed to obtain a constant variable frequency variable voltage, in addition to a main data selector for outputting a control signal to turn on and off the switching element to a control unit excluding the storage element, a carry signal of a binary counter is input to the storage element. The structure is equipped with an auxiliary data selector that switches according to the capacity.This makes it possible to use memory elements of different capacities even if the control section is integrated, which is economically advantageous. This is how it was done.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 4 to 6. To simplify the explanation, only one phase will be described. In Figure 4, the circuit configuration is similar to the conventional example, but the 30° of ROM8
The upper 4 bits (Q ₄ ,
Carry signals S ₈ to S ₁₁ are output from Q ₅ , Q ₆ , Q ₇ ), respectively, and are input to an auxiliary data selector 12B, which will be described later. That is, 12A is a main data selector, and 12B is an auxiliary data selector.The main data selector 12A is the same as the data selector 10 described as the conventional column in FIG. 2, but the auxiliary data selector 12B is added according to the present invention. It is what was done. This auxiliary data selector 12B forms a part of the control unit 20, for example, as shown by the dotted line in the figure, and for example, when the instruction signals S ₁₃ and S ₁₄ are respectively logical values (1, 1), only the gate 16 is activated. Open,
Gates 13 to 15 close and auxiliary data selector 1
From the output gate 17 of 2B, the same signal as the carry signal _S11 is outputted to the hexadecimal counter ₉ as the output signal S12 of the auxiliary data selector 12B. Similarly, when S ₁₃ and S ₁₄ are logical values (0, 0), the same signal as the carry signal S ₈ is output from the output gate 17, and when S ₁₃ and S ₁₄ are (0, 1), S If S ₁₃ and S ₁₄ are (1, 0), _{the same signal as S 10 is} output.

To explain the operation of the circuit shown in Fig. 4 configured as above, Fig. 4 is an example using a ROM 8 with a capacity of 128K bits, and the frequency setting signal _S1 from the frequency setting circuit 4 is a rate multiplier. 6 and ROM8. The rate multiplier 6 receives the clock signal _S2 from the oscillator 5 and divides the clock signal at a division ratio according to the frequency setting signal S1 so that the output voltage V of the inverter main circuit ₁ has a predetermined ratio relationship with the set frequency f. The frequency of S ₂ is changed and a new clock signal S ₂ a is output. The output S ₂ a of the rate multiplier 6 is input to a binary counter 7, which outputs a binary signal from output parts Q ₀ to _{Q 7} .
The binary signal is repeatedly addressed from the address indicated by S ₁ × 2 ⁸ to 256 addresses, and is output from the output section D ₀ to ROM 8 of the ROM8.
Electrical angle 0° ~ 30°, 30° ~ 60°, 60° ~ from D ₅ respectively
Data for 90°, 90° to 120°, 120° to 150°, and 150° to 180° is output. On the other hand, the 256-decimal carry signal S ₁₁ from the highest output part Q ₇ of the binary counter 7 is input to the main data selector 12A, and the instruction signals S ₁₃ and S ₁₄ of the auxiliary data selector 12B have logical values (1, 1), respectively. Data selector output signal determined by _S12
The same signal as _S11 is output. _S12 is input to the hexadecimal counter 9 and is output to the output section _D0 to _D5 of the ROM8.
It is used as the select signal _S5 of the main data selector 12A that sequentially selects the data. Main data selector 1
2A selects data D ₀ to D ₅ of the ROM 8 sequentially according to the select signal S ₅ and outputs the base signal (electrical angle 0° to 180°) of the transistor Tr ₁ of the inverter main circuit 1.
Output pattern data _S6 . On the other hand, this pattern data S ₆ enters the inverting circuit 11 and is output as a signal for the transistor Tr ₄ of the inverter main circuit 1, and is also used as data for the base signal 180° to 360° of Tr ₁ .

Figure 5 is an example of using 64K bits as ROM8, and the auxiliary data selector 12B
By setting the instruction signals S ₁₃ and S ₁₄ to logical values (1, 0), the output part Q ₀ ~
The Q ₆ signal moves ROM 8 from the address indicated by S ₁ × 2 ⁷ .
128 addresses are repeatedly addressed, the 128-decimal carry signal _S10 from the output part _Q6 of the binary counter 7 is input to the auxiliary data selector 12B, and the output signal
The same signal as _S10 is obtained at _S12 . Thereafter, in the case of 256K bits, data synthesis is performed in the same manner, and the data is obtained as the base signal of transistors Tr ₁ and Tr ₄ of the inverter main circuit 1.

Figure 6 is an example of using 32K bits as ROM8, and the auxiliary data selector 12B
By setting the instruction signals S ₁₃ and S ₁₄ to logical values (0, 1), the same signal as S ₉ can be obtained as the output signal S ₁₂ of the auxiliary data selector 12B. Thereafter, it is obtained as the base signal of Tr ₁ and Tr ₄ of the inverter main circuit 1 in the same manner as in the case of 256K bits and 128K bits. Transistor Tr ₂ of inverter main circuit 1,
For Tr ₅ , Tr ₃ , and Tr ₆ , in the same way that D ₀ , _{D 1 ,} D ₂ , D ₃ , D ₄ , and D _{5 correspond to Tr 1 and Tr 4 ,} Input D ₄ , D ₅ , D ₀ ,
By making D ₁ , D ₂ , D ₃ and D ₂ , D ₃ , D ₄ , D ₅ , D ₀ , D ₁ correspond to each other, a base signal can be obtained using the same selection signal S ₅ .

According to the above configuration, for example, the control section 2 of the inverter shown by the two-dot chain line in FIG.
When converting 0 into an integrated circuit, there is no longer the conventional restriction of one type of ROM capacity for one circuit, and instead there are 128K bits, 64K bits, 32K bits, and 16K bits.
You can use four types of BIT ROM,
Therefore, it is economically advantageous to be able to select the capacity of the ROM that matches the quality of the characteristics and quality of rotation of the motor driven by the inverter.

In addition, although the example described the case of three phases,
It goes without saying that the single-phase case can also be realized by using the signal for one phase.
In addition, there are four types of auxiliary data selector 12B.
Although a method has been adopted in which the ROMs are selected and specified using two instruction signals S ₁₃ and S ₁₄ , n types of ROMs may be selected and specified using m types of instruction signals.

〔Effect of the invention〕

As described above, the present invention makes it possible to use ROMs of different capacities by providing the auxiliary data select, so that it is possible to select a ROM that matches the required motor operating characteristics when integrating the control unit into an integrated circuit. This makes it possible to realize an inverter control device with a good balance between cost and performance.

[Brief explanation of drawings]

Fig. 1 is a wiring diagram showing the conventional inverter main circuit configuration, Fig. 2 is a block diagram showing the control circuit of the conventional inverter main circuit, Fig. 3 is a diagram showing a method for determining the contents to be stored in ROM, Figures 4 to 6
The figures are block diagrams showing one embodiment of the present invention in different usage states. In the figure, 4 is a frequency setting circuit, 5 is an oscillator, 6 is a rate multiplier, 7 is a binary counter,
8 is ROM (memory element), 9 is hexadecimal counter, 12
A is a main data selector, and 12B is an auxiliary data selector.

Claims (1)

[Claims] 1. An oscillator that generates a clock signal with a constant period that determines the output frequency, a rate multiplier that divides the frequency of the oscillator clock using a frequency setting signal as a division ratio and changes the frequency, and a voltage that corresponds to the frequency setting value. A memory element that stores the on/off timing of the switching element of the inverter so as to obtain a pattern, a binary counter that receives the output clock signal of the rate multiplier and addresses the memory element at a constant cycle, and a carry signal of this binary counter. an auxiliary data selector that switches according to the storage capacity of the storage element, a hexadecimal counter that counts the output of the auxiliary data selector, and main data that uses the output of the storage element as data and the output of the hexadecimal counter as a select signal. An inverter control device consisting of a selector.