JPH0437307A - Noise eliminating device - Google Patents

Abstract

PURPOSE:To reproduce a period of a fundamental signal by resetting an RS flip-flop circuit with an output signal of a delay device with a positive reset input terminal and setting the RS flip-flop circuit with an output signal of a delay device with a negative reset input terminal. CONSTITUTION:A delay device 1 with a positive reset input terminal is reset when an input signal fed to an input terminal 3 is at a high level. A delay device 2 with a negative reset input terminal is reset when the input signal fed to the input terminal 3 is at a low level. An RS flip-flop circuit 5 is set by an output signal Q2 of the delay device 2 with a negative reset input terminal and reset by an output signal Q1 of the delay device 1 with a positive reset input terminal and gives an output signal to an output terminal 6. Even when a noise signal is superimposed not only for a period at a low level but also for a period at a high level, the effect of the noise signal is excluded and the period of the fundamental signal is correctly reproduced.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a noise removal device that is capable of digitally removing noise components contained in an original signal and accurately reproducing the period of the original signal. This is related to equipment.In conventional technology when transmitting signals, it is unavoidable that noise gets mixed into the original signal.Noise removal devices are installed in the transmission path to ensure that information is transmitted correctly even if noise gets mixed in. There is a possibility that noise mixed into the original signal will cause errors in the transmitted information! If the noise is generally an extremely narrow pulse, and it may be superimposed on the rising or falling edge of the original signal's pulse, then the period of the received signal is substantially equal to that of the original signal. ＼ Noise can get mixed in between the pulses that make up the original signal, or it can be superimposed on the pulses of the original signal and cancel it locally, causing what was originally one pulse to appear as if it were two pulses. An example of a conventional noise removal device will be explained with reference to FIGS. 3 and 4. This device! -1 As shown in Figure 3, even if a delay device 31 with a negative polarity reset input terminal is provided, this is the top input terminal 3.
During the period when the input signal applied to the input terminal 2 is at low level, the delay device 31 with negative polarity reset input terminal is in the reset state, and the output signal obtained at the output terminal 34 becomes low level. When the input signal is at a high level, the delay device 31 with a negative polarity reset input terminal enters the reset release state and starts counting the number of pulses of the clock signal CLK applied from the clock signal input terminal 33, and the number of pulses is kept constant. When the count is reached, that is, when a certain period of time T has elapsed after the start of counting, a high-level output signal is generated at the output terminal 34.The delay device 31 with a negative polarity reset input terminal outputs a low-level input to the input terminal 32. When a signal is applied, a high-level output signal is generated until the signal is reset, and as shown in FIG. ,
During the period when it is at high level, the delay device 31 with negative polarity reset input terminal counts the number of pulses of the clock signal CLK.
If you set the time below to be sufficiently longer than the pulse width of the noise component, the noise component will disappear and the input signal will go to low level by the time time T is counted, and even if it is reset, the output signal will remain at low level. Therefore, no noise component appears at the output terminal 34.
When the input signal reaches time T, the delay device 31 with negative polarity reset input terminal generates a high-level output signal and continues to generate it until it becomes low level, causing the noise signal A to be superimposed on the original signal. Doing L
Problems to be Solved by the Invention Even if Noise Components Are Removed In this noise removal device, the delay device 31 with a negative polarity reset input terminal simply compares the pulse width of the input signal with a certain reference value, and its output is Output terminal 34
Therefore, when a noise signal that changes the input signal to low level during the period when the original signal is high level is mixed in, such as noise signal B shown in Figure 4, the resulting noise component cannot be removed. SUMMARY OF THE INVENTION It is an object of the present invention to provide a noise removal device capable of accurately reproducing the cycle of an original signal by removing noise components that become low level mixed in during the high level period of the original signal. Means for Solving the Problem Noise Removal Device of the Invention Top Delay device with positive polarity reset input terminal and delay device with negative polarity reset input terminal 9! ,
A delay device equipped with an RS flip-flop circuit and with a positive reset input terminal takes an input signal as a reset signal, generates an output signal at a second level different from the input signal while the input signal is at the first level, and when the input signal is at the first level. A delay device with a negative polarity reset input terminal counts clock signal pulses at a second level and generates an output signal at a first level when the counted value reaches a certain value. conversely generates an output signal of a first level different from the level of the period cylinder 2 whose input signal is the second input, and counts the clock signal pulses during the period when the input signal is at the first level, The RS flip-flop circuit generates a second level output signal when the count value reaches a certain value, and the RS flip-flop circuit uses the output signal of a delay device with a positive polarity reset input terminal as a reset signal, and uses a negative polarity reset input terminal as a reset signal. Using the output signal of the delay device with an input terminal as a set signal In the noise removal device of the present invention, the 41RS flip-flop circuit is reset with the output signal of the delay device with a positive polarity reset input terminal, and the delay device with a negative polarity reset input terminal is set. Since the noise signal is superimposed on the basic signal, the influence of this noise signal can be eliminated and the period of the basic signal can be reproduced. An example will be explained with reference to the drawings. Fig. 1 is a block diagram showing the configuration of this embodiment, and Fig. 2 is a signal waveform diagram for explaining its operation. In Fig. 1, 1 2 is a delay device with a positive reset input terminal; 2 is a delay device with a negative reset input terminal; terminal 3 is a common input terminal; terminal 4 is a clock signal C;
The delay device 1 with a positive reset input terminal as an LK input terminal is reset when the input signal applied to the input terminal 3 is at a high level, and the Glock signal input terminal 4 is used only when the input signal is at a low level. A module that counts the number of pulses of the clock signal CLK from the clock signal CLK and generates a high-level output signal Q1 when time T has elapsed after the start of counting, that is, when the counted value of the number of pulses of the clock signal CLK reaches a certain value. Then, the output signal Q remains high until the input signal becomes high level and a reset is applied.
Here, the noise signal is usually a pulse component with a narrow pulse width, and the time T is set longer than the pulse width. It is reset when the input signal from terminal 3 is at low level, and the number of pulses of clock signal CLK from clock signal input terminal 4 is counted only while the input signal is at high level. When the count value of the number of pulses of the clock signal CLK reaches a certain value, a high-level output signal Q2 is generated.Then, the high-level output signal Q2 is generated until the input signal becomes low level and a reset is applied. After outputting signal Q2, M5 is RS
This is a flip-flop circuit, and is set by the output signal Q2 of the delay device 2 with a negative polarity reset input terminal, and reset by the output signal QI of the delay device 1 with the positive polarity reset input terminal, and generates an output signal at the output terminal 6. When the input signal applied to terminal 3 is a signal in which no noise signal is superimposed on the original signal, a signal in which a noise signal with a narrow pulse width is superimposed, and a signal with a relatively narrow pulse width. The operation when the signal is a signal with a wide noise signal superimposed on it will be explained using Figure 2.If a pulse-like noise signal A is mixed in at time 1 just before the original signal rises, then at that rise. The delay device 1 with a positive polarity reset input terminal enters the reset state, and its output signal Q1 becomes low level. At this time, the delay device 2 with a negative polarity reset input terminal is set and enters the state of counting the number of pulses of the clock signal CLK. (When the noise signal A disappears and falls at time L2 before time T elapses,
The delay device 2 with negative polarity reset input terminal is reset11.
The output state of the RS flip-flop circuit 5 is affected by this noise signal A. At time 3, the input signal changes from low level to high level, and at its rising edge, the delay device 2 with negative polarity reset input terminal starts clocking. It starts counting the number of pulses of the signal CLK, and generates the output signal Q2 when time T has elapsed after the start.On the other hand, as is clear from the above, the input signal is Since it is at a high level, it is in a reset state and does not generate an output signal.
~ As a result, the RS flip-flop circuit 5 is set, and when the input signal that generates an output signal at the output terminal 6 falls at time 5, the delay device 2 with a negative polarity reset input terminal is reset, and its output signal When Q2 goes to low level, at the same time, the delay device 1 with positive polarity reset input terminal starts counting the number of pulses of the clock signal CLK. When the noise signal A is mixed in, the delay device 1 with a positive polarity reset input terminal is reset. On the other hand, the delay device 2 with a negative polarity reset input terminal is set again and starts counting the number of pulses of the clock signal CLK. When the noise signal disappears, the delay device 1 with a positive reset input terminal is set and the clock signal CLK is output again.
At the same time, even if the delay device 2 with a negative polarity reset input terminal is reset, the input signal continues to be at a low level, and at time t8, when time T has elapsed from time t7, the counted value of the number of pulses is reached. reaches a predetermined value, and the delay device 1 with positive polarity reset input terminal generates the output signal QI 6
．． The RSS flip-flop circuit 5 is reset by this output signal Q1, and the output signal of the output terminal 6 is at a low level. Since the pulse width is narrower than the time T, the delay device 2 with negative polarity reset input terminal remains in the reset state.
Delay device 1 with positive polarity reset input terminal operates according to this noise component, and its output signal Q1 becomes low level.
When the input signal returns to high level at time t8, the delay device 1 with positive polarity reset input terminal generates a high level output signal Q1 after a time T, and the L RSS flip-flop circuit 5 detects the change in this output signal Q1. When the input signal becomes high level at the rising edge of the original signal, the top of the delay device with a positive polarity reset input terminal is reset, and even if the delay device 2 with a negative polarity reset input terminal is set, the negative polarity is reset. The delay device 2 with an input terminal generates a high-level output signal Q2 after a time T when the clock signal CLK does not start counting, that is, at time j+2, and sets the RSS flip-flop circuit 5. As a result, a high-level signal is output to the output terminal 6. Even if the output signal appears, the noise signal B appears at time j+3.
is superimposed on the original signal and the input signal becomes low level, the delay device 2 with negative polarity reset input terminal is reset and the output signal Q2 becomes low level.At time j+a, the noise signal disappears and the input signal becomes high level. When the delay device 2 with a negative polarity reset input terminal counts the clock signal CLK and generates the high level output signal Q2 again after time T, the output signal Q1 of the delay device 1 with a positive polarity reset input terminal is at a low level, the RSS flip-flop circuit 5 continues to generate a high-level output signal, but when the original signal falls at 1% of the time and the input signal becomes a low level, the delay circuit with a negative polarity reset input terminal is activated. 2 is reset and the delay device 1 with a positive polarity reset input terminal is set. From this point on, the delay device 1 with a positive polarity reset input terminal counts the clock signal CLK. RS that generates QI
The S flip Flora circuit 5 receives this high level output signal Q.
1, and the output signal at the output terminal 6 becomes low level.As is clear from FIG. The period of (time jz - time (3)) and both are equal.In other words, when a signal in which a noise signal is mixed into the original signal is input, the period of the original signal can be correctly reproduced. Since the noise removing device G1R5 flip-flop circuit is reset by the output signal of the delay device with a positive polarity reset input terminal and set by the output signal of the delay device with a negative polarity reset input terminal, it can be used not only during the low level period of the basic signal. A noise signal is superimposed during the high level period, and it may be possible to eliminate the influence of this noise signal and correctly reproduce the period of the basic signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the noise removal device according to the present invention. FIG. 2 is a signal waveform diagram for explaining its operation. FIG. 3 is a block diagram showing the configuration of a conventional noise removal device. Fig. 4 is a signal waveform diagram for explaining the operation of a block diagram showing an example.Delay device with positive polarity reset input terminal 2...
...Delay device with negative polarity reset input terminal 3.Old...
Input terminal, 4... Input terminal for clock signal CLK, 5... Group RS flip-flop circuit 6.
...output terminal. Name of agent: Patent attorney Shigetaka Awano

Claims (1)

[Claims] an input terminal to which an input signal is applied; a clock signal input terminal to which a clock signal is applied; and a second level which is different from the first level for a period in which the input signal is a reset signal and the input signal is at a first level. a positive polarity that generates an output signal at a level of , counts clock signal pulses during a period when the input signal is at a second level, and generates an output signal at a first level when the counted value reaches a certain value; a delay device with a reset input terminal, the input signal being a reset signal, and generating an output signal at a first level different from the second level during a period when the input signal is at a second level; a delay device with a negative polarity reset input terminal that counts clock signal pulses during a period when is at a first level and generates an output signal of a second level when the counted value reaches a certain value; an RS flip-flop circuit that uses an output signal of the delay device with an input terminal as a reset signal and uses an output signal of the delay device with a negative polarity reset input terminal as a set signal; and an output terminal to which the output signal of the RS flip-flop circuit is supplied. A noise removal device equipped with.