JPH04373023A - Data processor - Google Patents

Abstract

PURPOSE:To decrease the stop of a pipe-lined processing generated at the time of branching according to a branching instruction by continuously executing following instructions and canceling an instruction preceding to the instruction of a branching destination even when the branching instruction is detected. CONSTITUTION:When the branching instruction is detected by a first processing means 4 to decode the instruction and the address of the branching destination is calculated by a second processing means 5 to calculate an operand address, the address is stored in a branching address register 21. For example, when a non-condition branching instruction is decided to be branched to the branching destination address by the second processing means 5 and a condition branching instruction is decided to the branching destination address by a fourth processing means 7 to execute calculation, a branch judgement part 19 detects the branch and instructs it to cancel control parts 9-13 on respective stages that a non- branch side instruction discriminated as an unwanted instruction is canceled. When it is decided that the instruction is not branched to the branching destination address, no instruction is canceled, and the pipe-lined processing is continuously advanced as it is.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus that performs pipeline processing, and relates to a structure for reducing stagnation in pipeline processing that occurs when processing branch instructions.

Currently, CPUs that execute most instructions in one cycle through pipeline processing have been commercialized and put into practical use in various data processing devices. However, since pipeline processing stalls when executing a branch instruction, there is a need for a method for suppressing the drop in efficiency of pipeline processing in such cases. In order to satisfy this requirement, it is necessary to increase the efficiency of pipeline processing by continuing pipeline processing even when a branch instruction is detected.

0003

2. Description of the Related Art When a conventional data processing device detects a conditional branch instruction, it predicts in advance whether the probability of branching is high or the probability of not branching is high, before it is known whether the branch condition is satisfied or not. Then, pipeline processing was performed starting from the instruction with the highest probability. Generally speaking, in program loop processing, the one with a higher probability of the branch condition being met is used to construct the loop, and the one with a lower probability of the branch condition being met is used to exit the loop. This is because the probability of predicting whether to branch or not to branch is correct can be increased.

However, when a conditional branch instruction is detected in a process where the probability of branching cannot be specified, such as program process selection, unlike in loop processing, there is a possibility that the prediction of branching or non-branching will be correct. It will be quite low. Therefore, in general, when a conditional branch instruction is detected in a program's process selection, non-branch instructions are processed in advance until the branch condition is determined, thereby avoiding pipeline processing stagnation when the branch condition is not met.

FIG. 4 is a diagram illustrating a conventional example. Here, we assume a data processing device in which the number of pipeline stages is "5", and the first stage decodes instructions, and the second stage decodes instructions.
It is assumed that the operand address is calculated in the third stage, the operand fetch is performed in the third stage, the operation is performed in the fourth stage, and writing is performed in the fifth stage. The data processing device is “
It is assumed that "Instruction 1" to "Instruction 5" are executed, and each "Instruction 1" among them is a branch instruction, and the branch destination instruction for each branch instruction, that is, "Instruction 1" is as shown in FIG. 4(a). In (b), it is "instruction 3", and in (c), it is "instruction 4".

[0006] In addition, "DC", "AC", "OF" in the figure
, "OE", and "OW" are abbreviations for processing, and the number mark following the abbreviation corresponds to the number attached to the end of each instruction in the left column to identify the instruction. For example, “D
C1" is the process related to "instruction 1", and "DC3" is the process related to "instruction 1".
This is the process related to instruction 3''.

Further, "DC" indicates the first stage of instruction decoding processing, "AC" indicates the second stage of address calculation processing, "OF" indicates the third stage of operand fetch processing, "
"OE" indicates the calculation process in the fourth stage, and "OW" indicates the write process in the fifth stage. In the figure, the vertical lines that separate the abbreviations of these processes are those that divide time into stages. It is assumed that time is flowing to the right in the figure.

FIG. 4A shows processing when "instruction 1" is an unconditional branch and the branch destination instruction is "instruction 3". As shown in FIG. 4A, it can be seen that two stages of stagnation occur between the unconditional branch instruction and the execution of the branch destination instruction.

In addition, in FIG. 4(b), "instruction 1" is a conditional branch instruction, and the branch destination instruction when the condition is satisfied is "instruction 3".
As shown in Figure 4(b), when the branch condition is met, there is a stagnation of three stages between the conditional branch instruction and the execution of the branch destination instruction. It can be seen that the establishment or failure of the branch condition is determined at the stage where the arithmetic processing of the conditional branch instruction is performed, that is, at "OE1".

FIG. 4(c) shows "instruction 1" as in FIG. 4(b).
” is a conditional instruction, and the difference is that when the branch condition is met, the branch destination instruction is “instruction 4” instead of “instruction 3”.
That's where it is. In FIG. 4(c), as in (b), it is found that the branch condition is established at the "OE1" stage, and in the end, there is a stagnation of three stages between the conditional branch instruction and the execution of the branch destination instruction. It can be seen that this is occurring.

[0011]

[Problems to be Solved by the Invention] As described above, in conventional data processing devices, when an unconditional branch instruction or a conditional branch instruction is detected in program processing selection and a branch is to be taken, a large delay occurs. There was a problem in that it caused That is, there is a problem in that the pipeline processing is stalled for a certain period of time before moving from a branch instruction to execution of the branch destination instruction.

SUMMARY OF THE INVENTION In view of these conventional problems, it is an object of the present invention to suppress the stagnation of pipeline processing that occurs at the time of branching in a data processing device.

[0013]

According to the invention, the above objects are achieved by the means set out in the claims.

That is, the invention according to claim 1 provides a data processing apparatus that has a buffer for storing instructions prefetched from a storage section and performs pipeline processing by sequentially passing instructions taken out from the buffer to processing means in a plurality of stages. comprising means for continuously executing instructions after the unconditional branch instruction when an unconditional branch instruction is detected; and means for holding a branch destination address of the unconditional branch instruction; and execution by the processing means. means for comparing the address of an instruction to be executed with the branch destination address, and when the instruction at the branch destination address is being executed by the processing means, after the unconditional branch instruction and at the branch destination address, This data processing device is provided with means for canceling a previous command.

The invention according to claim 2 provides a data processing device which has a buffer for storing instructions pre-fetched from a storage section and performs pipeline processing by sequentially passing instructions taken out from the buffer to processing means in a plurality of stages. comprising a means for continuously executing instructions after the conditional branch instruction when an instruction is detected, a means for holding a branch destination address determined by the condition of the conditional branch instruction, and an instruction executed by the processing means. and means for comparing the branch address with the branch destination address, and the condition of the conditional branch instruction is a condition for branching, and the instruction at the branch destination address is executed by the processing means. The data processing apparatus further includes means for canceling an instruction after the conditional branch instruction and before the instruction at the branch destination address.

The invention of claim 3 provides a flag holding section for each stage of the plurality of stages of processing means, and determines whether the address of the instruction being executed by the processing means at each stage is after the branch destination address. 3. The data processing apparatus according to claim 1, further comprising means for storing a flag indicating the instruction in the flag holding section of each stage, and means for canceling the instruction according to the flag stored in the flag holding section.

According to the fourth aspect of the invention, an instruction address register is provided for each stage of the plurality of stages of processing means, and the address of the instruction being executed by the processing means of each stage is stored in the instruction address register of each stage. 3. The data processing apparatus according to claim 1, further comprising means for comparing the address of the instruction address register with a branch destination address, and means for canceling the instruction according to the comparing means.

[0018]

[Operation] The present invention focuses on the fact that in the case of a branch in the process selection of a program, the branch is often to a nearby forward address. Process. As the preprocessing progresses, in many cases, the preprocessing of the branch destination instruction begins before it is known which instruction is to be executed next. Therefore,
At that time, if a branch occurs and unnecessary instructions are being executed, those unnecessary instructions can be canceled.

FIG. 1 is a diagram explaining the principle of the present invention. As in the conventional example, FIG. 1 assumes a data processing device in which the number of pipeline stages is "5", in which the first stage decodes the instruction, the second stage calculates the operand address, and the second stage decodes the instruction. It is assumed that operand fetch is performed in the third stage, calculation is performed in the fourth stage, and writing is performed in the fifth stage. The data processing device executes "instruction 1" to "instruction 5" listed in the left column of FIGS. 1(a) to (c), each "instruction 1" is a branch instruction, and each The branch destination instruction for the branch instruction is "instruction 3" in FIGS. 1(a) and (b), and "instruction 4" in FIG. 1(c).

In addition, in FIG. 1, as in the conventional example, “D
"C", "AC", "OF", "OE", and "OW" are process abbreviations, and the numbers following the abbreviations correspond to the numbers assigned to identify the instructions in the left column. .for example,"
"OE1" is a process related to "instruction 1", and "OE3" is a process related to "instruction 3".

Further, "DC" indicates the first stage instruction decoding process, "AC" indicates the second stage address calculation process, "OF" indicates the third stage operand fetch process, "
"OE" indicates the calculation process in the fourth stage, and "OW" indicates the write process in the fifth stage. In the figure, the vertical lines that separate the abbreviations of these processes are those that divide time into stages. It is assumed that time is flowing to the right in the figure.

In any of the cases shown in FIGS. 1(a) to 1(c), the first stage processing means for decoding the instruction is "instruction 1".
It can be seen that the decoding from "instruction 5" to "instruction 5" continues even after the branch instruction "instruction 1" is detected.The processing means in the second to fifth stages also detect the branch instruction. The instructions after the branch instruction continue to be executed as if they had not been executed.

When a branch is to be taken by a branch instruction, looking at the stagnation of pipeline processing in each of FIGS. 1(a) to (c), it is found that the amount of time required for one stage in FIGS. 1(a) and (b) is A stagnation has occurred, and it can be seen in FIG. 1(c) that a stagnation of two stages has occurred. In this branching case, "instruction 2" in FIGS. 1(a) to 1(c) and "instruction 3" in FIG. 1(c) are canceled as unnecessary instructions.

Comparing FIG. 4, which shows the conventional example, and FIG. 1, which shows the present invention, the comparison between FIG. 4(a) and FIG. 1(a) shows that the time for one stage is reduced. It can be seen that there is a difference, and the stagnation time of pipeline processing in the case of the present invention is half that of the conventional method. Similarly, Fig. 4(b
) and FIG. 1(b), the stagnation in the case of the present invention is one-third that of the conventional method.
A comparison with c) shows that stagnation is two-thirds of the previous level.

[0025]

[Embodiment] FIG. 2 is a diagram showing an embodiment of the present invention.
An example of the configuration of a data processing device that performs pipeline processing is shown. It is assumed that each stage of the pipeline processing shown in FIG. 1 is processed by each of the processing means 4 to 8 shown in FIG. Instructions taken out from the storage section 1 are stored in an instruction buffer 2 and supplied to a first processing means 4 that performs instruction decoding.

The instructions decoded here are the second processing means 5 for calculating the operand address, the third processing means 6 for fetching the operand, the fourth processing means 7 for executing the operation, and the writing of the operation result. The data are sequentially processed by the fifth processing means 8. Pipeline control section 2
0 performs pipeline control of each processing means 4-8.

When a branch instruction is detected in the first processing means 4 that performs instruction decoding and the branch destination address of the branch instruction can be calculated in the second processing means 5 that calculates the operand address, the branch destination address is It is stored in the address register 21.

Thereafter, the address comparator 3 compares the address of the instruction inputted from the instruction buffer 2 to the first processing means 4 and the branch destination address of the branch address register 21, and the address of the instruction inputted to the first processing means 4 is compared. When the address of the instruction is equal to or greater than the branch destination address, a flag indicating that the instruction is a branch-side instruction is set in the flag holding unit 14. This flag is shifted backwards as the pipeline progresses,
It is set in each flag holding section 15-18.

When a branch instruction is processed in any one of the second processing means 5 to fifth processing means 8, for example, in the case of an unconditional branch instruction, the second processing means 5 calculates the operand address, and in the case of a conditional branch instruction, an operation is performed. In the fourth processing means 7 that performs execution, if it is determined that the branch will be taken to the branch destination address, the branch determination unit 19 detects the branch and sends unnecessary instructions to the cancellation control units 9 to 13 of each stage. Instructs to cancel non-branching instructions that are found to be .

Branch-side instructions after the branch destination instruction are continuously processed in the pipeline without being canceled. on the other hand,
If it is determined that the program will not branch to the branch destination address, the pipeline processing continues without canceling either the non-branch side instruction or the branch side instruction.

FIG. 3 is a diagram showing another embodiment of the present invention. First, it is assumed that each stage of the pipeline processing shown in FIG. 1 is processed by each of the processing means 34 to 38 shown in FIG. The instructions retrieved from the storage section 31 are stored in an instruction buffer 32 and supplied to a first processing means 34 that performs instruction decoding.

The instructions decoded here are the second processing means 35 for calculating the operand address, the third processing means 36 for fetching the operand, the fourth processing means 37 for executing the operation, and the writing of the operation result. The data are sequentially processed by the fifth processing means 38. The pipeline control unit 50 performs pipeline control of each processing means 34 to 38.

First processing means 34 for decoding instructions
detects a branch instruction, and when the second processing means 35 for calculating operand addresses calculates the branch destination address of the branch instruction, this branch destination address is stored in the branch address register 51. Thereafter, the address of the instruction input from the instruction buffer 32 to the first processing means 34 is
It is stored in the instruction address register 44.

The contents of this instruction address register 44 are as follows:
It is shifted backward with the flow of pipeline processing and stored in each instruction address register 45-48. Each address comparing unit 52-56 compares the contents of the branch address register 51 with the contents of the corresponding instruction address register 45-48, and the corresponding processing means 34-38 executes the non-branch side instruction. It notifies whether the instruction on the branch side is being executed.

If it is determined that the branch instruction branches to the branch destination address in any of the second processing means 35 to fifth processing means 38, the branch determination unit 49 detects the branch and determines the branching at each stage. Instructs the cancellation control units 39 to 43 to cancel the non-branch side instruction. On the other hand, if it is determined that the branch will not be branched to the branch destination address, the pipeline processing continues as is.

[0036]

As explained above, according to the present invention, pipeline processing is continuously performed in advance for branches to forward adjacent addresses that occur during two-branch selection and multi-branch selection in program processing. Therefore, there is an advantage that the interruption time of pipeline processing can be reduced in unconditional branch instructions and conditional branch instructions, and the processing speed of the data processing device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing another embodiment of the invention.

FIG. 4 is a diagram illustrating a conventional example.

[Explanation of symbols]

1, 31 Storage section 2, 32 Instruction buffer 3, 52-56 Address comparison section 4, 34
First processing means 5, 35 Second processing means 6, 36 Third processing means 7, 37 Fourth processing means 8, 38 Fifth processing means 9-13, 39-43 Cancellation control section 14-
18 Flag holding section 19, 49 Branch judgment section

Claims (4)

[Claims] Claim 1: In a data processing device that has a buffer for storing instructions pre-fetched from a storage unit and performs pipeline processing by sequentially passing instructions taken out from the buffer to processing means in multiple stages, an unconditional branch instruction is detected. In some cases, the unconditional branch instruction includes a means for continuously executing instructions after the unconditional branch instruction, a means for holding a branch destination address of the unconditional branch instruction, and an address of the instruction to be executed by the processing means and the branch. means for comparing the instruction with the branch destination address, and means for canceling the instruction after the unconditional branch instruction and before the instruction at the branch destination address when the instruction at the branch destination address is being executed by the processing means. A data processing device comprising: 2. When a conditional branch instruction is detected in a data processing device that has a buffer for storing instructions prefetched from a storage unit and performs pipeline processing by sequentially passing instructions taken out from the buffer to processing means in multiple stages. To,
It comprises means for continuously executing instructions after the conditional branch instruction, means for holding a branch destination address determined by the condition of the conditional branch instruction, an address of the instruction to be executed by the processing means, and a means for holding the branch destination address determined by the condition of the conditional branch instruction. and when the condition of the conditional branch instruction is a condition for branching and the instruction at the branch destination address is executed by the processing means, after the conditional branch instruction A data processing device further comprising means for canceling an instruction before the instruction at the branch destination address. 3. A flag holding section is provided for each stage of the plurality of stages of processing means, and a flag indicating whether the address of the instruction being executed by the processing means at each stage is after the branch destination address is stored in each stage. 3. The data processing apparatus according to claim 1, further comprising means for storing the flag in the flag holding section, and means for canceling the instruction according to the flag stored in the flag holding section. 4. Means for providing an instruction address register for each stage of the plurality of stages of processing means, and storing the address of the instruction being executed by the processing means of each stage in the instruction address register of each stage; 3. The data processing apparatus according to claim 1, further comprising means for comparing an address of an instruction address register with a branch destination address, and means for canceling the instruction according to the comparing means.