JPH0437290A - Signal processor for video printer - Google Patents

Abstract

PURPOSE:To realize freeze processing of a picture, picture arithmetic processing and print processing and to process a video signal in compliance an NTSC system and a video signal inputted independently with one coding processing by adopting the digital demodulation method by means of a picture arithmetic means. CONSTITUTION:The above processor is provided with plural picture arithmetic means 5(27, 28) including a digital demodulator and means 12, 18, 21 selecting the arithmetic means 5(27, 28) and executes the signal processing in matching with both a video signal in compliance with the NTSC system as an input signal and the video signal comprising separated luminance and chrominance signals and with each signal form. The picture arithmetic means 5(27, 28) contribute to no adjustment, high performance and low cost in the demodulation processing and execute the picture arithmetic processing in matching with an input signal. Thus, the processor copes with the video signal in compliance with the NTSC system as the input signal and the video signal separated into the luminance signal and the chrominance signal and a full color hard copy picture is obtained by one coding.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing device for a video printer that outputs full-color hard copy images.

[Prior Art] FIG. 12 is a block diagram showing a signal processing device for a video printer disclosed in, for example, Japanese Unexamined Patent Publication No. 179677/1983.

In the figure, (101) is an A/D circuit II that encodes an input video signal, (102) is an image memory that stores encoded data in a predetermined pixel configuration, and (103) is an image memory (102). A D/A circuit decodes the read encoded data into a video signal, (104) is an analog demodulation circuit for the restored video signal, (105) is an analog modification circuit for the demodulated signal, and (106) is an R (red) circuit from the modified signal. )G (green)B
(Blue) Inverse matrix circuit for restoring the signal, (107)
is an encoder circuit that generates a video signal from RGB signals. Also, (108) is an inverse matrix circuit (106)
Multi-brake, yx (hereinafter referred to as M
PX) circuit, (109) is an A/D circuit IV that re-encodes the MPX signal, (110) is a line memory that temporarily stores encoded data, and (111) is a thermal head (112) that is subject to thermal control. as line memory (110
) is a printing circuit that generates thermal control data according to encoded data read from the printer. Note that the A/D circuit Ill (
101), image memory (102) and D/A circuit (1
03) executes freezing processing of the desired image, and connects an analog demodulation circuit (104), an analog correction circuit (105), an inverse matrix circuit (106), and an encoder circuit (107).
) executes the correction processing of the frozen image, and the MPX circuit (1
0B), A/D circuit IV (109), and line memory (
110), printing circuit (111) and thermal head (
112) executes print processing.

Next, the operation will be explained.

Input video signals conforming to the NTSC system etc. are A/D
It is encoded in circuit III (101). The encoded data is sequentially stored for one screen from a predetermined position in the image memory (102). This operation completes the image freeze processing mode. This frozen image data is read out in a predetermined order from a predetermined location in the image memory (102), decoded by a D/A circuit (103), and restored to the original video signal. This video signal is separated into a luminance component Y and color components (RY, B-Y) by a demodulation circuit (104). The amplitude value and the like of this separated signal are modified by an analog modification circuit (105), and the luminance and hue are adjusted to desired values. This modified signal is converted into two RGB signals by an inverse matrix circuit (106). The RGB signal is processed by an encoder circuit (
107) into a video signal compliant with the NTSC system,
Output as a monitor signal. Corrections can be made while referring to this monitor image. This is an overview of the image retouching processing mode.

On the other hand, the RGB signals are multiplexed in the MPX circuit (108) and encoded again in the A/D circuit IV (109). The encoded data is stored in the line memory (110).
The processing operations on the monitor display are converted into print processing operations. That is, a predetermined number of lines is temporarily stored, where one line is the number of pixels in the vertical direction of the image aspect vector (approximately 480 pixels in the NTSC system). Line memory (11
The RGB data read from the printing circuit (11
1).

The printing circuit (111) performs conversion processing of Y (yellow), M (magenta), and C (cyan) ink corresponding to RGB data into density data and thermal control data for the purpose of controlling gradation. Run the thermal head (112)
The amount of heat generated is controlled on a pixel-by-pixel basis. This thermal control is performed two-dimensionally to obtain a single ink hardcopy image.

This retouching process and printing process are repeated for the number of inks used to obtain a full-color hard copy image.

This is an overview of the print process.

In this way, by providing the image freeze processing means, correction processing means, and print processing means, it is possible to obtain a preferable hard copy image of a desired image.

[Problems to be Solved by the Invention] Since the signal processing device of a conventional video printer is configured as described above, encoding and D/A processing (hardware processing) are performed twice within the same device for printing. Copying is also assumed to be a D/A operation in a broad sense), and there are problems such as image quality deterioration such as a decrease in S/N ratio, reliability decrease due to circuit redundancy, and high price. , for example NT as the input signal
There were problems such as only processing video signals compliant with the SC system.

This invention was made in order to solve the above-mentioned problems, and employs a digital demodulation method using image calculation means, and performs image freeze processing, image calculation processing, and printing in one encoding process. It is an object of the present invention to provide a signal processing device for a video printer that can process both a video signal conforming to the NTSC system and a video signal in which a luminance signal and a color signal are independently input as input signals.

[Means for Solving the Problems] A signal processing device for a video printer according to the present invention includes a plurality of image calculation means including a digital demodulator and a means for selecting the calculation means, and uses an NTSC-compliant signal processing device as an input signal. It is configured to handle both a video signal and a video signal obtained by separately inputting a luminance signal and a chrominance signal, and to perform signal processing tailored to each signal format.

[Function] The image calculation means in the present invention contributes to making demodulation processing unnecessary, improving performance, and reducing cost, and also functions to enable image calculation processing to be performed in accordance with input signals.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figure, (1) and (2) represent the input terminal ■ and the input terminal ■ of the video signal, (3) and (4) represent the A/D circuit I and the A/D circuit ■ that encode the video signal, and ( 5) is an image calculator that performs calculations on image data, (6) is a clock regeneration circuit that generates synchronization signals and reference clock signals from the input video signal, and (7) is an overall sequence control and control of each part. A controller that generates data and control signals. Note that the other components are the same as those described in the conventional example.

FIG. 2 shows an embodiment of the image arithmetic unit (5).

In the figure, (10) and (11) are input terminals for video data, (12), (18) and (21) are selectors ■, selector ■, and selector ■ for selecting one from two people,
(13) is a 3-state (hereinafter referred to as 3ST) buffer, (14), (15), (16) and (17) are connection terminals with the image memory (102), and (19) is a 3-state (hereinafter referred to as 3ST) buffer. Filter I to extract, (20
) is, for example, a filter that emphasizes the high frequencies of an image, (22)
is a subtracter, (23) is a luminance data output terminal, (24)
is a color data output terminal, (27) is a write block of the image arithmetic unit, and (28) is a read block.

Figure 3 shows filter I that extracts color data from video data.
An example of (19) is shown below.

In the figure, (30) is an input terminal for video data, (31
) is an IH (H is the time of one horizontal scanning line) delay element (hereinafter referred to as lH-DLY), (32) is a (1/2) multiplier, and (33) is a (-1/4) multiplier. (34) is an adder ■, (37) is a filter IV with band-pass characteristics, (3
8) is a delay circuit, (35) is a color data output terminal, (3
6) is an output terminal for timing-adjusted video data of interest.

Figure 4 shows, for example, a filter that emphasizes the outline (20)
An example is shown below.

In the figure, (40) is an input terminal for luminance data, etc.
41) is a one-pixel delay element (hereinafter referred to as IDLY),
(42) is a (-1/8) multiplier, (43) is an adder ■,
(46) is a (-1) multiplier, (44) is an output terminal for the calculation result, and (45) is an output terminal for timing-adjusted luminance data of interest.

FIG. 5 shows one embodiment of the image memory (102).

In the figure, (51) and (52) are DRAM memory I and DRAM memory ■, (53) is an address selector, and (54)
) is a freeze controller that manages image freeze mode address data, (55) is a display controller that manages display mode addresses, and (56) is a print controller that manages print mode addresses.

FIG. 6 shows an embodiment of the printing circuit (111).

In the figure, (61) is an RGB arithmetic unit, (62) is a pixel decomposer for color conversion, (63) is a print selector, (
64) is a memory, (65) is a head driver, (66) is an address generator for printing processing, (67) is a print calculator, (68) is a printing controller, (69) is a helad data This is the HD output terminal.

Next, this operation will be explained in detail.

In an input mode in which the input signal is a video signal Y/C based on the NTSC system, the video signal Y/C is input to the input terminal I(1). The input signal Y/C is directly encoded in the A/D circuit I(3). As conditions for this encoding, the number of quantization bits = 8 bits, the sampling frequency = 4 * fsc (fsc: subcarrier frequency = 3.58 MHz), and the pixel configuration 768 (H) * 480 (V) are adopted. This encoded data is called video data Y/C.

The video data Y/C is input to the input terminal (
10), passes through selector I (12) and 3ST buffer (13), and connects to connection terminals (14) and (15).
is transferred from the image memory (102) to the image memory (102).
Data for one screen is stored in a predetermined order from a predetermined position in 02).

At this time, the address data of the freeze controller (54) in FIG. 5 is selected by the address selector (53) and input to DRAM memory I (51) and DRAM memory II (52), and the video data Y/ C is DRAM memory I (
51) and DRAM memory I[(52), the data is temporarily stored in any one of the DRAM memories. In other words, D.R.A.
M memory I (51) and DRAM memory (52) are managed by a freeze controller (54). This input mode
Now, only a few (two images) can be frozen.

Furthermore, when the input signal is an input mode 2 video signal consisting of a luminance signal and a color signal, the luminance signal is input to input terminal I (1
) and directly encoded by the A/D circuit I(3).

On the other hand, the color signal is input to the input terminal (2) and directly encoded by the A/D circuit (4). The encoded data are called luminance data Y and color data C, respectively. The encoding conditions are the same as those for the video signal Y/C.

The luminance data Y is input to the input terminal (10) of the image calculator (5).
, passes through the 3ST buffer (13), and is transferred from the connection terminal (14) to the image memory (102). On the other hand, color data C is input to the input terminal (11) of the image calculation unit (5).
input from selector I (12) and 3ST buffer (
13) and from the connection terminal (15) to the image memory (1
02).

At this time, the address data of the freeze controller (54) in FIG. 5 is selected by the address selector (53) and input to DRAM memory I (51) and DRAM memory II (52), and the brightness data , DRAM memory T (51)
As for color data C, luminance data Y and color data C for one screen are simultaneously temporarily stored in a DRAM memory II (52) from a predetermined position in a predetermined order. In other words, in this input mode 2, a small number of images can be frozen.

In the above embodiment, the image arithmetic unit (5) has the configuration shown in FIG. 2, but the write block (27) may have the configuration shown in FIG. 11.

FIG. 11 shows the write block (27) of the image arithmetic unit (5).
) is shown. In the figure, (91) is a Y/C encoder that calculates NTSC-compliant video data Y/C from luminance data Y and color data C, and (92) is a selector (2) that selects one of the two.

Next, the operation will be explained.

In input mode 1, the video signal Y/C is input as in the previous embodiment.
is directly encoded by the A/D circuit I (3), and the encoded video data Y/C is input to the input terminal (10) shown in FIG. Selector IV (92) and Selector I (12)
selects the video data Y/C and transfers the 3ST buffer (1
3) and is output from the connection terminals (14) and (15), and is stored in the image memory (102) in the same manner as described above.

Furthermore, in input mode 2, the luminance signal is encoded by the A/D circuit I(3) and the color signal is encoded by the A/D circuit I(3), as in the previous embodiment. The encoded luminance data Y is
The color data C is input from the input terminal (10) shown in FIG. 11, and the color data C is input from the input terminal (11). A Y/C encoder (91) calculates video data Y/C based on the NTSC system from the luminance data Y and color data C.

When selector IV (92) selects brightness data Y and selector I (12) selects color data C, the brightness data Y and color data C pass through the 3ST buffer (13) and are connected to the connection terminal (14). and from (15) the image memory (
102).

At this time, the address data of the freeze controller (54) in FIG. DRAM memory I (51)? ,
:, color data C is stored in the DRAM memory r1(52)J, : luminance data Y and color data C for one screen are simultaneously temporarily stored in a predetermined order from a predetermined position.

Also, selector IV (92) is connected to Y/C encoder (9
When selecting the output video data Y/C of 1), the video data Y/C is selected from the selector (12) and the 3ST buffer (
13) and is transferred to the image memory (102) from the connection terminals (14) and (15), and data for one screen is stored in a predetermined order from a predetermined position in the image memory (102).

At this time, the address data of the freeze controller (54) in FIG. 5 is selected by the address selector (53) and input to the DRAM memory I (51) and DRAM memory N (52), and the video data C is DRAM memory I (5
1) and DRAM memory n (52), it is temporarily stored in any one of the DRAM memories.

In other words, the write block (27) of the image processor (5)
By making the configuration shown in FIG. 11, when the input data is video data Y/C, it is the same as the embodiment shown in FIG. 2, but when the input data is luminance data Y and color data C, teeth,
There is an advantage that it is possible to select between storing luminance data Y and color data C in the image memory (102) and calculating and storing video data Y/C. Here, video data Y/C is l/C compared to luminance data Y and color data C.
This means that it has been compressed to 2.

With the above operations, the freeze mode for the desired image is completed.

To move to the next mode, 3ST buffer (13)
Set the output to the off state.

If the freeze data in the image memory (102) is video data Y/C, it is read out (bl and b2) under the address management of the display controller (45) in FIG.
5).

Video data Y/ of the DRAM RAM memory I) input from the input terminal (16) of the image arithmetic unit (5) shown in FIG.
DRAM memory II input from C and (17)
(52) (7) Video data Y/rot, selector ■(
18) Te is selected. In other words, selector I[(1,8)
performs an operation of selecting either the image in DRAM memory I (51) or the image in DRAM memory 1,' n (52).

The selected video data Y/C is filtered by filter I shown in FIG.
(19) is delayed by I H-D LY (31) and becomes data f, e, and d. The data is operated on by a (1/2) multiplier (32) and a (-1/4) multiplier (33). The adder (34) calculates s=0.5 *e-0,25(d+f),
Unnecessary components other than color data C are removed from the data S sequence by a filter (37) having bandpass characteristics. This output data is outputted from the output terminal (35) as color data C, while the timing of e is adjusted by the delay circuit (38) and outputted from the output terminal (36) as focused video data Y/C. 21). Sent video data Y
/C and color data C are selected by a selector I[I (21), and a subtracter (22) performs the calculation Y m = Y / CC. With this operation, separation of the luminance data Y and color data is completed, and the luminance data Ym is output from the output terminal (23).
However, color data Cm is output from the output terminal (24).

In other words, the image arithmetic unit (5) has separated the video data Y/C stored in the image memory (102) into luminance data Ym and color data Cm.

On the other hand, if the freeze data in the image memory (102) is luminance data Y and color data C, the display controller (5
Under the address management of 5), luminance data Y is read out from the DRAM (51) (bl), and color data C is read out from the DRAM memory II (52) (b2).
) and is transferred to the image processing unit (5).

Selector II (18) of the image arithmetic unit (5) shown in FIG.
) selects the luminance data Y input from the connection terminal (16) and sends it to the filter II (20).

The selected luminance data Y is the fill II shown in FIG.
(20) IH-DLY (31) and IDLY (41)
), resulting in data d, eS f, g, h.

The data is transmitted through the (l/2) multiplier (32) and (-1/8)
It is calculated by a multiplier (42). The adder (34) s=
0.5 *e Calculate -0,125(d+f+g+h), use the (-1) multiplier (46) to output (-5) from the output terminal (44), and output e as the luminance data of interest Y. Output from terminal (45). When the data read from the image memory (102) is luminance data Y and color data, the selector (21) selects the 1 side of the input. Filter (2
The luminance data Y and (-8) output from the terminal (0) are selected by the selector I[[(21), the subtracter (22) performs the calculation Ym=Y-(s), and the output terminal (23 ) is output.

On the other hand, the color data C input from the connection terminal (17) is time-adjusted by the delay circuit (25) and selected by the selector (21).
) and output as Cm from the output terminal (24).

In other words, the image arithmetic unit (5) has enhanced the outline of the luminance data Y stored in the image memory (102).

Through the processing of the image arithmetic unit (5) described above, the luminance data Ym and color data Cm separated from the video data Y/C,
Or the brightness data Ym and color data Cm with contour emphasis
is obtained. These luminance data Ym and color data Cm are each restored into analog signals by a D/A circuit (103). The encoder circuit (107) generates a video signal Y/C from this restored signal and outputs it as a monitor signal.

At this time, the synchronization signal (m) etc. reproduced by the clock reproduction circuit (6) are added to form a video signal compliant with the NTSC system. The above explanation is an overview of the display mode.

Next, the print mode will be explained.

FIG. 7 shows the order in which video data Y/C is read from the image memory (102) in display mode and print mode.

In the figure, (A) relates to the display mode and the video data Y
/C is read out in units of lines of 768 pixels in the order of 1→3→5→...2→4...

(B) relates to the print mode, in which p pixels in l line are read out sequentially from line l every q (q=1 or 2) lines up to 480 lines, and then line 1
The next p pixels are read out in the same way. This reading is performed for one screen.

FIG. 8 shows the operational positional relationship between the synchronization signal and the freeze, display, and print modes.

In the figure, (A) shows a synchronization signal represented by -horizontal scanning section H, and (B), (C), and (D) show operating positions of each mode with ON. As shown in the figure, the display mode and print mode operate almost simultaneously on a time-sharing basis.

When the data stored in the image memory (102) is video data Y/C, the DRAM memory I (51) and DR
When the above operation is performed on one of the AM memories II (52) and the data stored in the image memory (102) is luminance data Y and color data C, the DRAM memory I
(51) and DRAM Memory II (52) simultaneously.

The print mode will be explained with reference to FIGS. 7 and 8.

Video data Y/Y read out from the image memory (102) under the address management of the print controller (56) in FIG.
C or brightness data Y and color data C are processed by an image processing unit (
5). Luminance data Ym and color data Cm are output from the image arithmetic unit (5) in the same process as in the display mode. However, it is necessary to satisfy the condition p≧r, where r is the number of pixels required for the calculations of filter circuit I (19) and filter circuit N (20) inside the image arithmetic unit (5).

In addition, I H-D LY (31) and delay circuit (25
) may be changed as appropriate depending on the p value and the process may be performed.

The two obtained data are transferred to the printing circuit (111).

Next, the operation of the printing circuit (111) will be explained.

The input luminance data Ym and color data Cm are restored to RGB data by an RGB arithmetic unit (61). The RGB data is decomposed into achromatic data and chromatic data by a pixel decomposer (62). These two data are stored in the print selector (
63), the table conversion ROM of the memory (64), and the print arithmetic unit (67) which adds the partial data obtained by the table conversion to YMC ink density data. The ink density data is temporarily stored in a memory (64) for time axis adjustment under the control of an address generator (66). The ink density data read from the memory (64) at a predetermined timing is transferred to the head driver (65), and thermal control data H of the thermal head (112) is transferred to the head driver (65).
It is converted to D (head data). This head data H
D is transferred to a thermal head (112) and thermally transferred. These entire sequences are controlled by the print controller (6
8) is controlled.

The details of the printing circuit are disclosed by the present inventors in Japanese Patent Laid-Open No. 64-216696.

In current video printers, YSM and C sublimation dye inks are sequentially thermally transferred, so the print mode is repeated three times for each ink to obtain a hard copy of the desired image.

The above is an overview of the printer mode.

In the above embodiment, the image arithmetic unit (5) may have the configuration shown in FIG. 2 or the configuration shown in FIG. 9.

In FIG. 9, (70) is a filter (2), (71) is a coefficient generator that specifies the multiplication coefficient of the filter III (70), and (72) is a selector (2) that selects one of the two.

FIG. 10 shows an embodiment of filter I[[(70).

In the figure, (80) is an input terminal for the multiplication coefficient from the coefficient generator (71), (81) is an input terminal for video data Y/C or luminance data Y, and (82) is an input terminal for the coefficient generator (71).
), (83) is the adder ■, (84) is the output terminal of the pixel of interest, (85) is the adder II [the addition of (83) This is the output terminal for the result.

Next, the operation will be explained. However, the image processing unit (5
The operations other than ) are the same as those in the previous embodiment, and will therefore be omitted.

Video data Y/ read out from the image memory (102)
C passes through selector II (18) to filter ■ (7
0) is input to the input terminal (81). The video data Y
/C is l H-D L Y (31) and l D L Y
(41) d.

6. f, g, h, i, j, and l. Further, from the input terminal (80), 1 to 9 are specified as the multiplication coefficients of the multiplier (82), and the multiplier (82) and adder (83) output s=, 1*l+, 2*d+ to 3* to + K 4 * h + K 5 * e 10K 6
*The operations 7*j+, 8*f+, and 9*i are performed on g+. The multiplication coefficient is K1=
0 to 2 = -1/4 K 3 = OK K 4 = 0 K5 = 1/2 K 6 = OK K 7 = 0 K8 = -1/4 K 9 = 0, but are limited to these values. isn't it. The calculation result S is outputted from the output terminal (85) as color data C,
In addition, e from the output terminal (84) is the focused video data Y/C.
is output as The video data Y/C and color data C are subjected to the calculation Y m = Y / CC in a subtracter (22), and luminance data Ym is outputted from an output terminal (23). Further, the selector IV (72) selects the color data C output from the filter III (70) and outputs it from the output terminal (24) as color data Cm.

On the other hand, when brightness data Y and color data C are read from the image memory (102), the brightness data Y input from the connection terminal (16) is passed through the selector n (18) to the filter I ([input terminal of (70) 81).The luminance data Y is input to LHDLY(31) and IDL
Y(41) gives d, e, f, g, h, i, j, and l.

Further, from the input terminal (80), 1 to 9 are specified as the multiplication coefficients of the multiplier (82), and the multiplier (82) and the adder
In (83), the following calculations are performed: 5=Kl*I+, 2*d+, 3*, 10, 4*h+, 5*e+, 6*g+, 7*j+, 8*f+, 9*i. In the case of the same characteristics as the filter I (19) shown in FIG. 3, the multiplication coefficients are as follows: K1=0 K2=1/8 to 3=0 K4=1/8 to 5=-1/2 to 6= A value of 7-0 K8=1/8 K9=0 is used for 1/8, but the value is not limited to this.

The calculation result S is output from the output terminal (85), and e is output as the luminance data of interest Y from the output terminal (84). The luminance data Y and color data C are subjected to the calculation Ym=Y-s in a subtracter (22), and the luminance data Ym is outputted from an output terminal (23). Further, the selector rV (72) selects the color data C input from the connection terminal (17) and whose timing has been adjusted by the delay circuit (25), and outputs it from the output terminal (24) as color data Cm.

The following operations are the same as those in the display mode and print mode of the previous embodiment.

Further, in the above embodiment, the filter I (19) is the third
Although the configuration shown in the figure is not limited to this, any configuration may be used as long as it is a technology that separates luminance data and color data from video data (, filter n (20)).
described outline enhancement as an example of image calculation, but a filter that smoothes the image, removes noise, etc. on the luminance data Y may also be used. Also, filter I
[+ Although the configuration of (70) was explained with reference to FIG. 10,
The present invention is not limited to this, and a filter with any configuration and coefficients can be used.

Further, the delay means shown in the figure is not an essential means because an equivalent function can be realized by the read address signal of the memory.

[Effects of the Invention] As described above, according to the present invention, the input signal is NT
It is possible to configure a signal processing device that supports video signals compliant with the SC method and video signals that are input separately into luminance signals and color signals, and can obtain full-color hard copy images with -degree encoding. This has the effect of realizing an economical printer device in which the signal processing section is easily integrated into an LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a signal processing device of a video printer according to an embodiment of the present invention, FIG. 2 is a diagram showing an embodiment of an image processing unit, and FIG. A diagram showing an example of a filter that separates data and color data, FIG. 4 is a diagram showing an example of a filter that emphasizes the outline of an image, and FIG. 5 is an overview of the image memory section. Figure 6 is a diagram showing an example of the printing circuit, Figure 7 is a diagram showing the difference in data reading methods between display mode and print mode, and Figure 8 is a diagram showing the synchronization signal and each mode. 9 is a diagram showing an example of the readout program of the image arithmetic unit. FIG. 10 is a diagram showing an example of a filter that can specify coefficients.
FIG. 1 is a diagram showing an embodiment of a write block of an image arithmetic unit, and FIG. 12 is a diagram showing a conventional embodiment. In the figure, (1) and (2) are input terminals for video signals, (3) is A/D circuit I, (4) is A/D circuit ■, (5) is image arithmetic unit, and (6) is clock The regeneration circuit, (7) is the controller, (
lO) and (11) are input terminals for encoded video data, etc., (12) is a selector ■, (13) is a 3-state buffer, (14) (15) (16) and (17)
is a connection terminal, (18) is a selector ■, (19) is a filter i, (20) is a filter ■, (21) is a selector ■, (22) is a subtractor, (23) and (24) are image arithmetic units. (30) is the input terminal of filter I (19), (31) is a one-line delay element, (32) is (
1/2) multiplier, (33) is (-1/4) multiplier, (3
4) is an adder ■, (35) and (36) are output terminals, (3
7) is a filter ■, (38) is a delay circuit, (40) is an input terminal of filter II (20), (41) is a one-pixel delay element, (42) is a (-1/8) multiplier, ( 43) is an adder ■, (44) (45) is an output terminal, (46) is a (-1) multiplier, (51) is a DRAM memory ■, (52
) is the DRAM memory ■, (53) is the address selector, (
54) is a freeze controller, (55) is a display controller, (5
6) is a print controller, (61) is an RGB arithmetic unit, and (6) is a print controller.
2) is a pixel decomposer, (63) is a print selector, (64
) is the memory, (65) is the head driver, (66) is the address generator, (67) is the print calculator, (68) is the printing controller, (69) is the output terminal of the Herad data HD, (
70) is a filter ■, (71) is a coefficient generator, (72)
is selector ■, (80) (81) is filter I[[(
70) input terminal, (82) is multiplier, (83) is adder ■, (84) (85) is output terminal, (91) is Y/
, C encoder, (92) is selector ■. Also,
(101) is A/D circuit ■, (102) is image memo 1, (103) is D/A circuit, (104) is analog demodulation circuit, (+05) is analog correction circuit, (106) +
Or an inverse matrix circuit, (107) is an encoder circuit,
(108) is MPX circuit, (1,09) is A/D circuit■
, (110) +i line memory (111) is a printing circuit, and (112) l is a thermal head. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Diagram

Claims (2)

[Claims] (1) A signal processing device for a video printer device that obtains a full-color hard copy image, which (a) directly converts a video signal compliant with the NTSC system or a video signal inputted separately into a luminance signal and a color signal into an image. (b) Memory means for freezing and storing at least two screens of video data or at least one screen of the brightness data and color data; (c) The video data or brightness data. and a means for selectively transmitting color data according to the input form; (d) an image calculation means for processing the video data or luminance data and color data read from the memory means; (e) from the calculation data. A means for generating a monitor video signal; (f) a means for performing printing based on the calculated data; (g) a means for reproducing a synchronization signal, a reference clock signal, etc. from the input video signal; A control means for managing sequence operations, mode management, etc., the image calculation means has an NTSC
If video data that conforms to the system is frozen,
Signal processing for a video printer, characterized in that it separates luminance data and color data from the video data, and when the luminance data and color data are frozen, performs calculations such as image edge enhancement and noise removal. Device. (2) A signal processing device for a video printer device that obtains a full-color hard copy image, which (a) directly converts a video signal compliant with the NTSC system or a video signal inputted separately into a luminance signal and a color signal into an image. (b) Memory means for freezing and storing at least two screens of video data or one screen of the brightness data and color data; (c) The video data or the brightness. (iv) an image calculation means that performs calculation processing on the data and color data according to the input form and transmits the data to the memory means, and also performs calculation processing on the video data or luminance data and color data read from the memory means; A means for generating a monitor video signal from the computed data; (e) a means for performing printing based on the data to be computed; (f) a means for reproducing a synchronization signal, a reference clock signal, etc. from the input video signal; ) control means for managing the entire sequence operation, mode management, etc., and when the input signal is a video signal separated into a luminance signal and a color signal, the image calculation means converts the encoded data of the input signal into an NTSC system. 1. A signal processing device for a video printer, characterized in that the signal processing device generates video data in accordance with the above and freezes it in a memory means.