JPH04372040A - High speed bus architecture - Google Patents

Abstract

PURPOSE:To provide the bus architecture without deterioration of a processing efficiency by preventing the contention of the access between the I/O and the access between the CPU and the I/O in the bus architecture of the information processor having a plurality of I/Os. CONSTITUTION:A CPU1, a main memory 2, and a plurality of I/Os 7 are connected to a system bus 4 under the control of a system bus arbiter 3, and a plurality of I/Os 7 are connected to an I/O bus 6 directly connecting the only I/Os 7 under the control of the I/O bus arbiter 5. A system bus control part and an I/O bus control part are independently provided on an interface controller 12. Since the access between the I/O and the access between the CPU and the I/O are not contended, the processing efficiency of the CPU is not deteriorated and the high speed processing of the entire system can be enabled.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus architecture in an information processing apparatus provided with a plurality of input/output devices (hereinafter referred to as I/O).

0002

2. Description of the Related Art As an example of the bus architecture of a conventional information processing device having multiple I/Os, Japanese Patent Laid-Open No. 2-43
A data transfer device disclosed in Japanese Patent No. 655 can be cited.

[0003] In this bus architecture, a communication control device corresponding to an information processing device is connected to a central processing unit (hereinafter referred to as C
It consists of a system bus monitoring control unit that controls the entire communication control device including PU), and multiple line support units that are I/O,
They are connected by a system bus. Each line corresponding section includes a local processor for controlling the line, a program memory, a line control controller, a DMA controller, a transmission/reception data buffer, a system bus control controller for interfacing with the system bus, and the like.

[0004] Here, the operation of transferring data from one line corresponding section A to another line corresponding section B will be explained, focusing on the transfer on the system bus. When the line corresponding unit A receives the data from the line and takes the received data into the transmission/reception data buffer, the local processor issues a data transfer request to the system bus controller. The system bus controller requests the system bus supervisory control unit for bus rights to the system bus. The system bus supervisory control unit that has been requested the bus right takes the bus right from the CPU when the access currently using the system bus ends, and transfers the bus right to the system bus control controller. The system bus control controller that has obtained the bus right takes out data from the transmit/receive data buffer and sends it onto the system bus. Here, the system bus controller of the other line corresponding section B recognizes that the signal on the system bus is for its own line corresponding section B,
It takes in the data on the system bus and writes it to the transmission/reception data buffer, and notifies the other party's line corresponding section A that the data on the system bus has been received. Then, the system bus controller of the line correspondence section B is the system bus control controller of the line correspondence section B.
The local processor is notified that the data transferred from the controller has been written to the transmit/receive data buffer. Line handling section B transmits data according to instructions from the local processor. On the other hand, the system bus control controller of the line handling unit A, which has received the notification that the data has been taken in from the line handling unit B, returns the bus right to the system bus supervisory control unit. The system bus control controller that has been returned the bus right returns the bus right to the CPU. In this way, one data transfer is performed.

[0005]

In the above-mentioned prior art, when data is transferred between arbitrary line compatible units, the CPU of the system bus supervisory control unit is forced to wait for accessing another line compatible unit. Conversely, if the CPU of the system bus supervisory control section is accessing the line correspondence section, data transfer between any other line correspondence sections is made to wait. That is, if access to the CPU's I/O and access between the I/Os occur simultaneously, contention will occur on the system bus and the processing efficiency of both will decrease.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus architecture that does not cause a decrease in processing efficiency by not causing access contention.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a CPU, a main memory, a plurality of I/Os, one or more buses (first bus group) connecting these, and each In an information processing device consisting of a bus arbiter for a bus, a second bus that connects only arbitrary I/Os and is not connected to other buses, a bus arbiter that controls the second bus, and an interface for each bus to each I/O. The system is equipped with a bus control section that controls the

[0008]

[Operation] In the above means, when the CPU accesses any I/O, the CPU accesses the target I/O via the first bus group. At this time, each bus arbiter
It recognizes the access from U, transfers bus rights, and connects each bus. The accessed I/O is handled by the first bus group controller
Recognizes access from PU and responds. On the other hand, the above I/
Data transfer between I/Os on the same first bus, which is different from O, is performed via the second bus under arbitration by the second bus arbiter. Therefore, accesses from the CPU to I/Os and accesses between I/Os on the same first bus do not overlap.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, a first embodiment of the present invention will be explained. FIG. 1 is a system configuration diagram of an information processing device. The information processing device includes a CPU 1 and a CPU that control the entire device.
The main memory 2 stores information such as programs executed by U1, and various I/Os 7a-7n (in this embodiment, I/Os 7a-7n).
The maximum number of O's is 14. ), CPU1, main memory 2
and system bus 4 that connects various I/Os 7a-7n.
, a system bus arbiter 3 that controls the system bus 4.
, I/O bus 6 and I/O bus 6 connecting various I/Os 7a-7n.
It consists of an I/O bus arbiter 5 that controls the O bus 6. The I/O 7a is an I/O that directly performs communication, and includes a communication control processor 8a that controls communication, a program memory 9a that stores a communication control program, a local bus 13a that connects these, and a data buffer that holds transmitted and received data, etc. 10a, a line controller 11a that controls the line interface, a system bus 4, an I/O bus 6,
It consists of an interface controller 12a that controls the interface of a local bus 13a, a data buffer 10a, and a line controller 11a. The I/O 7n is also an I/O that directly performs communication, and has the same configuration as the I/O 7a. Moreover, I/O7b-7l also has a similar configuration. FIG. 2 shows the interface controllers 7a and 7n.
FIG. The interface controller 12 includes a system bus control section 14 that controls access from the system bus 4, an I/O bus control section 15 that controls access to the I/O bus 6, and a local bus 13.
a local bus control unit 19 that controls access to the data buffer 10; a line controller control unit 20 that controls the line controller 11; an arbiter 17 that arbitrates access to the data buffer 10 from these control units; It consists of a data buffer access control section 18 that performs control, and a H/W (hardware) register 16 that performs settings for the interface controller 12 and exchanges information via each bus. FIG. 3 is a memory map of the CPU 1. Main memory 2 is allocated to 64KB from address 0, and system bus arbiter 3 and I/O bus arbiter 5 are allocated from address 10000H.
Allocate H/W registers to set the operation of 20
After address 000H, 64 KB is allocated to each I/O 7, the first 32 KB is allocated to the data buffer 10, and then the H/W register 16 in the interface controller 12.
Allocate the total space to 1MB. The start address of each I/O7 is 20000 in the order of I/O7a to I/O7n.
Assign from address H to address F0000H. FIG. 4 is a memory map of the I/O 7. Address 0 to 6
4KB is allocated to program memory 9, 64KB from address 10000H is allocated to main memory 2, 20000
After address H, 64 KB is allocated to each I/O 7, the first 32 KB is allocated to the data buffer 10, and then the H/W register 16 in the interface controller 12 is allocated, making the total space 1 MB. The starting address of each I/O 7 is assigned from address 20000H to address F0000H in the order of I/O 7a to I/O 7n.

In the information processing apparatus configured as described above, at the same time as the CPU 1 accesses the data buffer 10a of the I/O 7a or the communication control processor 8a of the I/O 7a accesses the main memory 2, the I/O 7a and I/O 7n We will explain the case of accessing between. FIG. 5 is a sequence diagram of this embodiment. The communication control processor 8n copies data from the data buffer 10a to the data buffer 10n. The communication control processor 8n communicates with the interface controller 1 via the local bus 13n.
Data buffer 10a (address 20000H) for 2n
A data read request is issued (40). The local bus control unit 19n in the interface controller 12n is
It recognizes that the communication control processor 8n is accessing address 20000H, and activates the I/O bus control unit 15n. The I/O bus control unit 15n controls the I/O via the I/O bus 6.
A request for bus rights is made to the O bus arbiter 5 (41). I/O
If the I/O bus 6 is unused, the bus arbiter 5
The bus right is transferred to the /O bus control unit 15n (42). The I/O bus control unit 15n that has obtained the bus right outputs the data read request for the data buffer 10a received from the local bus control unit 19n onto the I/O bus 6 (43). on the other hand,
The I/O bus control unit 15a in the interface controller 12a of the I/O 7a detects that the signal address 20000H on the I/O bus 6 is an access request to the data buffer 10a, and activates the arbiter 17a. If the data buffer 10a is not accessed, the arbiter 17a passes the signal received from the I/O bus control section 15a to the data buffer access control section 18a. The data buffer access control unit 18a reads the data in the data buffer 10a according to the signal (44),
The data is sent to the I/O bus controller 15 via the arbiter 17a.
Pass it to a (45). The I/O bus control unit 15a controls the I/O
The data is passed to the I/O bus control unit 15n via the bus 6 (46). The I/O bus control unit 15n passes the data to the communication control processor 8n via the local bus control unit 19n and the local bus 13n (47), and grants bus rights to the I/O bus arbiter 5 via the I/O bus 6. release (48)
. The communication control processor 8n instructs the local bus control unit 19n via the local bus 12n to write the data to address F0000H of the data buffer 10n (49). The local bus control unit 19n has an address F0.
The address 000H is recognized as the address of the data buffer 10n of the own I/O 7n, and the arbiter 17n is activated. If the data buffer 10n is not accessed, the arbiter 17n passes the signal requested by the local bus control section 19n to the data buffer access control section 18n. The data buffer access control unit 18n writes data to the data buffer 10n according to the signal (50).
. In this way, the data buffer 10a (address 2
0000H) to the data buffer 10n (address F0000H). On the other hand, the CPU 1 performs access between the main memory 2 and the data buffer 10a of the I/O 7a. The CPU 1 reads the contents of the address 1000H of the main memory 2 via the system bus 4 (20, 21). At this time, system bus arbiter 3
does nothing. CPU 1 transfers data to data buffer 10
It is output to the system bus 4 as data to a (address 20000H) (22). The system bus control unit 14a of the interface controller 12a recognizes that the signal on the system bus 4 indicates access to the data buffer 10a, and activates the arbiter 17a. If the data buffer 10a is not accessed, the arbiter 17a passes the request signal from the system bus controller 14a to the data buffer access controller 18a. The data buffer access control unit 18a writes data to the data buffer 10a according to this request (23
). As described above, from CPU1 to data buffer 1
Since access to 0a is performed without going through the I/O bus 6, the CPU 1 can repeatedly access the data buffer 10a even while copying data from the data buffer 10a to the data buffer 10n. Furthermore, access between the main memory 2 and the data buffer 10a of the I/O 7a can be performed by the communication control processor 8a of the I/O 7a. The communication control processor 8a is connected to the local bus 13.
A data read request for the main memory 2 (address 3000H) is issued to the interface controller 12a via the interface controller 12a (30). Interface controller 12a
The local bus control section 19a within the system recognizes that the communication control processor 8a is accessing address 3000H, and starts the system bus control section 14a. The system bus control unit 14a requests bus rights to the system bus arbiter 3 via the system bus 4 (31). The system bus arbiter 3 requests bus ownership from the CPU 1 (32). At this time, if CPU1 is accessing (24, 25) CPU
1 is the system bus arbiter 3 after the access is completed.
transfer the bus rights (33). In response to this, the system bus arbiter 3 transfers the bus right to the system bus control unit 14a (34). System bus control unit 1 that has obtained bus rights
4a outputs the data read request for the data buffer 10a received from the local bus control unit 19a onto the system bus 4 (35). According to this, main memory 2 to 3
The data at address 000H is output onto the system bus 4 (36). The system bus control unit 14a passes the data to the communication control processor 8a via the local bus control unit 19a and the local bus 13a (37), and releases the bus right to the system bus arbiter 3 via the system bus 4 (37).
38). Then, the system bus arbiter 3 releases the bus right to the CPU 1 (39). The CPU 1 which has obtained the bus right outputs the previously read data (25) to the system bus 4 as data to the data buffer 10a (26). The system bus control unit 14a of the interface controller 12a recognizes that the signal on the system bus 4 indicates access to the data buffer 10a, and activates the arbiter 17a. If the data buffer 10a is not accessed, the arbiter 17a passes the request signal from the system bus controller 14a to the data buffer access controller 18a. Data buffer access control unit 18
A writes data to the data buffer 10a according to the request (27). In this way, access is performed between the CPU 1 or main memory 2 and the I/O 7a.

Next, a second embodiment of the present invention will be explained. In this embodiment, a case of an information processing apparatus having a configuration different from that of the first embodiment will be described. FIG. 6 is a system configuration diagram of the information processing device. The information processing device includes a CPU 1 that controls the entire device, a main memory 2 that stores information such as programs executed by the CPU 1, a processor bus 52 that connects the CPU 1 and the main memory 2, and a processor that controls the processor bus 52. Bus arbiter 51, various I/Os 7a-7n (maximum of 14 I/Os in this embodiment), system bus 4 connecting various I/Os 7a-7n, system bus arbiter that controls the system bus 4. 3. A bidirectional buffer 53 that connects the processor bus 52 and the system bus 4, and various Is separate from the system bus 4.
I/O bus 6 and I/O bus 6 connecting /O7a-7n
The I/O bus arbiter 5 controls the I/O bus arbiter 5. I/O
7a is an I/O that directly performs communication, and includes a communication control processor 8a that controls communication, a program memory 9a that stores a communication control program, a local bus 13a that connects these, and a data buffer 1 that holds transmitted and received data, etc.
0a, a line controller 11a that controls the line interface, and an interface controller 12a that controls the interface of the system bus 4, I/O bus 6, local bus 13a, data buffer 10a, and line controller 11a. The I/O 7n is also an I/O that directly performs communication, and has the same configuration as the I/O 7a. Moreover, I/O7b-7l also has a similar configuration. The internal block diagram of the interface controller 12 is shown in Figure 2.
It is similar to Furthermore, the memory maps of the CPU 1 and I/O 7 are similar to those in FIGS. 3 and 4, respectively.

[0013] In the information processing apparatus with this configuration, CPU1 to I
/O7a access to data buffer 10a or I
/O7a communication control processor 8a to main memory 2
A case will be described in which access is made between I/O 7a and I/O 7n at the same time as access is made between I/O 7a and I/O 7n. FIG. 7 is a sequence diagram of this embodiment. Data copying from the data buffer 10a to the data buffer 10n is the same as in the first embodiment. On the other hand, the CPU 1 performs access between the main memory 2 and the data buffer 10a of the I/O 7a. C.P.
U1 reads the contents of address 1000H of main memory 2 via processor bus 52 (60, 61)
. At this time, the processor bus arbiter 51 does nothing. The CPU 1 stores the data in the data buffer 10a (address 2
processor bus 52 as data to address 0000H).
(62). The processor bus arbiter 51 recognizes this and requests the bus right from the system bus arbiter 3 (63). System bus arbiter 3 is system bus 4
If it is unused, the bus right is passed to the processor bus arbiter 51 (64). The processor bus arbiter 51 that has obtained the bus right outputs the data on the processor bus 52 onto the system bus 4 via the data buffer 53 (65). The system bus control unit 14a of the interface controller 12a recognizes that the signal on the system bus 4 indicates access to the data buffer 10a, and activates the arbiter 17a. If the data buffer 10a is not accessed, the arbiter 17a passes the request signal from the system bus controller 14a to the data buffer access controller 18a. Data buffer access control section 1
8a writes data to the data buffer 10a in accordance with the general request (66). When the access is completed, the processor bus arbiter 51 returns the bus right to the system bus arbiter 3 (67). In this way, access from the CPU 1 to the data buffer 10a is performed without going through the I/O bus 6, so even when data is being copied from the data buffer 10a to the data buffer 10n, the CPU
1 can access the data buffer 10a. Furthermore, access between the main memory 2 and the data buffer 10a of the I/O 7a can be performed by the communication control processor 8a of the I/O 7a. The communication control processor 8a communicates with the main memory 2 (address 3000H) to the interface controller 12a via the local bus 13a.
A data read request is issued (68). The local bus control unit 19a in the interface controller 12a is
It recognizes that the communication control processor 8a is accessing address 3000H, and starts the system bus control unit 14a. The system bus control unit 14a requests bus rights from the system bus arbiter 3 via the system bus 4 (69). In response, the system bus arbiter 3 requests bus ownership from the processor bus arbiter 51 (70). Further, the processor bus arbiter 51 requests bus ownership from the CPU 1 (71). At this time, if the CPU 1 is accessing, the CPU 1 transfers the bus right to the processor bus arbiter 51 after the access is completed (72). In response, the processor bus arbiter 51 transfers the bus right to the system bus arbiter 3 (73). Furthermore, the system bus arbiter 3 transfers the bus right to the system bus control unit 14a (74). System bus control unit 14a that has obtained bus rights
outputs the data read request signal of the main memory 2 received from the local bus control unit 19a onto the system bus 4. The system bus arbiter 3 outputs the signal on the system bus 4 onto the processor bus 52 via the data buffer 53 (75). Data at address 3000H is output from main memory 2 onto processor bus 52 in accordance with the signal. The processor bus arbiter 51 outputs data onto the system bus 4 via the data buffer 53 (
76). The system bus control unit 14a passes the data to the communication control processor 8a via the local bus control unit 19a and the local bus 13a (77), and releases the bus right of the system bus 4 to the system bus arbiter 3 via the system bus 4. (78). In response to this, the system bus arbiter 3 releases the bus right of the processor bus 52 to the processor bus arbiter 51 (79). Furthermore, the processor bus arbiter 51 controls the bus right of the processor bus 52 by C.
Release to PU1 (80). In this way, access from the communication control processor 8a to the main memory 2 is
Since this is done without going through the O bus 6, the data buffer 10a
The communication control processor 8a can repeatedly access the main memory 2 even while copying data from the data buffer 10n to the data buffer 10n.

[0014] In the above two embodiments, an I/O that performs direct communication is used as the I/O, but by using these embodiments with other I/O such as floppy disks and hard disks, it is possible to improve the speed at the time of data transfer. Bus contention can be prevented.

[0015]

Effects of the Invention According to the present invention, there is no conflict between accesses between I/Os and between CPUs and I/Os.
Even if the number of I/Os increases or a large amount of data is transferred between I/Os, the processing efficiency of the CPU does not decrease, and the entire system can perform high-speed processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device according to a first embodiment of the present invention;

FIG. 2 is a block diagram of the interface controller of the information processing device of the present invention;

FIG. 3 is a memory map of the CPU of the information processing device of the present invention;

FIG. 4 is an I/O memory map of the information processing device of the present invention;

FIG. 5 is a processing sequence diagram of the first embodiment of the present invention;

FIG. 6 is a block diagram of an information processing device according to a second embodiment of the present invention;

FIG. 7 is a processing sequence diagram of a second embodiment of the present invention.

[Explanation of symbols]

1... CPU, 2... Main memory, 3... System bus arbiter, 4... System bus, 5... I/O bus arbiter, 6
...I/O bus, 7...I/O, 8...communication control processor,
9...Program memory, 10...Data buffer, 12...
interface controller.

Claims (6)

[Claims] 1. An information processing device comprising a central processing unit, a main storage device, a plurality of input/output devices, one or more buses connecting these, and a bus arbiter for each of the buses, wherein any of the input/output devices A second bus that connects only between each other and is not connected to other buses, a bus arbiter that controls the second bus, and a bus control unit that controls the interface of each bus for each input/output device. High-speed bus architecture. 2. An information processing device comprising a central processing unit, a main memory, a plurality of input/output devices, a first bus connecting these devices, and a bus arbiter that controls usage rights of the first bus. A high-speed bus characterized in that a second bus connects only output devices, the bus arbiter controls the right to use the second bus, and each input/output device is provided with a control unit for the second bus. architecture. 3. A central processing unit, a main memory, a first bus that connects these, a bus arbiter that controls the right to use the first bus, a plurality of input/output devices, and a second bus that connects the input/output devices. an information processing device comprising: the bus arbiter that controls the right to use the bus and the second bus; and a buffer that connects the first bus and the second bus;
A third bus to which only the input/output devices are connected separately from the second bus, a bus arbiter that controls the right to use the third bus, and each of the input/output devices is provided with the third bus control unit. High-speed bus architecture. 4. The LSI according to claim 1, wherein a first bus control unit for connecting to the first bus group and a second bus control unit for connecting to the second bus are independently provided. . 5. The LSI according to claim 2, wherein the first bus control unit for connecting to the first bus and the second bus control unit for connecting to the second bus are independently provided. . 6. The LSI according to claim 3, wherein a second bus control section for connecting to the second bus and a third bus control section for connecting to the third bus are independently provided.