JPH0437133A - Wiring formation of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the need for performing a resist process and form a fine wiring pattern as well even though there are remarkable irregularities on a substrate by performing the irradiation of charged particles selectively to a part where wiring is to be formed on an insulating film and depositing a conductive metallic substance selectively on a part where irradiation is carried out after performing deposition treatment so as to deposit the conductive metallic substance. CONSTITUTION:In wiring formation of a semiconductor device equipped with wiring on an insulating film 22, deposition treatment is performed in order to deposit a conductive metallic substance by performing the irradiation of charged particles selectively to a part where wiring is to be formed on the insulating film 22 and deposition treatment mentioned above comprises a process which deposits the conductive metallic substance selectively on a part 123 that receives irradiation. The charged particles take the form of focused ion beams and further, the deposition of the conductive metallic substance is performed by CVD where the gas of alkylaluminum halide and hydrogen are used and it is preferable to make the above conductive metallic substance consist of Al or a metallic substance which has Al for its main ingredients. Further, Al is deposited only on a region 123 which receives ion beam irradiation and simultaneously it is deposited also in a throughhole 124.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device for forming fine wiring patterns of semiconductor devices such as memory photoelectric conversion devices and signal processing devices mounted on various electronic devices. The present invention relates to a wiring forming method.

(Prior Art) Conventionally, as shown in FIGS. 11(A) to 11(C), the wiring pattern of an integrated circuit is formed by depositing a conductive material on the entire surface of an insulating film, patterning a photoresist, and then patterning a photoresist.
The desired wiring shape was obtained by removing unnecessary portions by etching using a patterned resist as a mask.

In FIG. 11(A), 130 is a semiconductor active layer;
1 is the lower layer AJ2. 132 is the insulating layer (S102 or Si3
N4), 133 is upper layer A! , 134 is an antireflection film, 1
35 is a resist, and 136 is a concave portion of the resist directly above the through hole.

To achieve this structure, after forming the wiring pattern of the lower layer AA 131, an insulating film 132 is deposited on the entire surface, and then through holes are opened. Thereafter, Aρ or Aj2-3i or the like is deposited to a thickness of about 1 μm over the entire surface at a substrate temperature of 250° C., for example, by magnetron sputtering. Further, for patterning, 2000 layers of polyimide silane as an antireflection film 134 during exposure and 1 μm of ordinary resist 135 are applied.

During the overexposure period after the resist has been exposed to the bottom, polyimide silane absorbs light energy that would not be absorbed by the resist alone, and also decomposes itself. This prevents excess light from hitting areas that are not originally desired to be exposed and causing the resist in those areas to decompose. This improves the accuracy of buttering. Excimer light source (ArF line, λ=186n
The wiring pattern is exposed using an exposure machine such as an exposure machine having a lens with an aperture ratio NA of 0.4°, and the resist and reflective film are removed. This situation is shown in Figure 11 (B).
Shown below. Thereafter, the Afl exposed using the RIE method is removed by anisotropic etching, and the remaining resist and antireflection film are removed to obtain a desired wiring pattern (FIG. 11(C)).

[Problem that the invention is trying to solve]

However, these conventional wiring forming methods have the following technical problems that need to be solved.

(1) Since wiring materials generally have a high reflectance, light reflected and scattered on the surface of the wiring material in the exposed area may go around to areas that should not be exposed, causing the resist in those areas to be exposed. It was put away. Therefore, it has been difficult to pattern the resist faithfully to the mask pattern. This required an anti-reflection film directly above the wiring material, making the lens process complicated.

(2) When the unevenness of the base of the wiring material is larger than the depth of focus of the exposure machine, the resist is not sufficiently exposed, making it difficult to perform faithful resist patterning.

Below, regarding the point (2) above, Figure 12 (A) and 12
This will be explained using Figure (B).

In FIG. 12(A), 140 is the lower layer Ail wiring;
+41 is an interlayer insulating layer, 142a is an upper layer Afl deposited on the entire surface, 143 is a resist, 144 is an antireflection film, 1
45 is a light transmitting part of the exposure mask, 146a, 146b
Both are light-opaque parts of the exposure mask, and 147 is light condensed by a lens. 142b in Figure 12(B)
142c is the upper layer Au that has been properly patterned, and 142c is the upper layer AJ2 that has not been properly patterned.

FIG. 12(A) shows the state of exposure when there are severe irregularities on the surface of sea urchins due to steps in the base. Assume that the level difference between the bottoms of the resist to be etched is D, and the exposure is focused on the resist directly below the pattern 146a. At this time, if D≧^/NA2 (λ, exposure wavelength, NA/numerical aperture of lens), the light that should be exposed will not focus well on the resist directly under 146b. In the above equation, the value on the right side is a constant determined by the exposure machine called depth of focus. For example, a typical value of λ/NA2 is 1.2 μ.
If D≧12 μm, the resist and antireflection film immediately below 146b are not etched according to the pattern of 146b, and the resist remains unexposed as shown in FIG. 12(A). This remainder is caused by the light not being in focus, so setting a longer exposure time will not improve the image. After the exposure step shown in FIG. 12(A), when the wiring is etched in step 8, as shown in FIG. 12(B), the resist or the portions 142c that are not exposed according to the pattern sag on the An as shown in 142d. Therefore, a short circuit with the adjacent Aρ wiring is likely to occur.

On the other hand, in the latest LSI process, although the size is reduced in the horizontal direction, the size is not reduced in the vertical direction, and a step of 1 μm or more is often produced on the surface during the final wiring process. To make matters worse, the exposure wavelength λ has been changed to accommodate miniaturization.
If you try to decrease the numerical aperture NA and increase the numerical aperture NA, the depth of focus will become smaller and smaller.

As can be seen from the above explanation, the method of forming fine wiring patterns on highly uneven steps cannot sufficiently respond to improvements in the resolution of devices.

[Means for Solving the Problems (and Effects)] A wiring formation method for a semiconductor device according to the present invention is a wiring formation method for a semiconductor device having an insulating film on an insulating film, in which the wiring should be formed on the insulating film. The method is characterized by comprising the steps of selectively irradiating a portion with charged particles, performing a deposition process to deposit a conductive metal substance, and selectively depositing a conductive metal substance on the irradiated portion.

[Operations] According to the present invention, for example, an An
By selectively irradiating charged particles such as metal ions such as , Au, Ga, Cu, hydrogen ions, or ions such as Si and Be to desired locations, a deposition process is performed on the insulating film that has been irradiated with the charged particles. By selectively depositing a metal substance on the irradiated portion, it is possible to form a fine wiring pattern without the need for a resist process and even on a substrate with severe irregularities.

〔Example〕

<Embodiment> The present invention provides a method in which charged particles are selectively irradiated onto an insulating layer and through holes as shown in FIG. 2 using a charged particle irradiation means such as a focused ion beam device as shown in FIG. 1, for example. Thereafter, a conductive metal substance is selectively deposited only on the portions irradiated with charged particles using a selective vapor deposition method, thereby providing a method of forming wiring without a resist process.

The deposition method suitable for this formation method is the CVD method using alkyl aluminum hydride and hydrogen (described later).
(hereinafter referred to as the Al-CVD method).

In this method, high-quality Au is produced by reaction with the electron-donating surface.
2 or Al-based metals can be deposited. This method shows very good selectivity for depositing conductive metallic substances on electron-donating surfaces. Therefore, using this method, after selectively filling a metal substance into a contact hole having an electron-donating surface, a desired portion of the insulating film having a non-electron-donating surface is surface-modified by charged particle irradiation. An electron-donating surface can be formed. Once an electron-donating surface is formed in the form of a wiring pattern in this way, metal can be deposited with good selectivity again by the above-mentioned CVD method. Therefore, in combination with the Aj2CVD method, charged particles related to the surface reaction system of the Al1-CVD method, such as hydrogen ions and A1 ions, are more preferable as the charged particles to be implanted. By repeating this process again, a multilayer wiring structure of three or more layers can be obtained. The metal film thus formed exhibits excellent properties as a wiring material, as will be described later.

Electron-donating materials are those in which free electrons exist in the substrate, or in which free electrons are intentionally generated, and chemical reactions are promoted by electron transfer with source gas molecules attached to the substrate surface. A material with a surface that is

For example, metals and semiconductors generally correspond to this. In addition, materials in which a thin oxide film is present on the surface of a metal or semiconductor are also included in the electron-donating materials of the present invention, since chemical reactions can occur between the substrate surface and attached raw material molecules by electron transfer.

Similarly, even if the surface is made of an insulating material, for example, by irradiating it with charged particles,
The electron-donating properties of the present invention also include those in which the physical structure or chemical bonding state of the surface of the irradiated insulating film is changed so that a chemical reaction can occur between the substrate surface and the attached raw material molecules by electron transfer. Contained in the material.

Specific examples of electron-donating materials include Ga, In, Al1, etc. as group III elements, and P as group V elements.
, As, N, etc., or semiconductor materials such as monocrystalline silicon, amorphous silicon, or monocrystalline silicon or amorphous silicon. Or metals, alloys, silicides, etc. shown below, such as tungsten, molybdenum, tantalum, copper, titanium, aluminum, titanium aluminum, titanium nitride, aluminum silicon copper, aluminum palladium, tungsten silicide, titanium silicide, aluminum silicide, side, molybdenum silicide, tantalum silicide, etc.

Furthermore, examples of insulating materials include silicon oxide and silicon nitride, which have a surface that is chemically active when irradiated with charged particles.

On the other hand, materials forming the surface on which Afi or A11-Si is not selectively deposited, that is, non-electron-donating materials, include silicon oxide formed by thermal oxidation, CVD, etc., BSG, PSG, BPSG, etc. glass or oxide film, thermal nitride film, plasma CVD method, low pressure CVD method,
Examples include insulating materials that have a stable surface and do not easily exchange electrons on the surface, such as a silicon nitride film formed by ECR-CVD or the like.

Next, the above-mentioned CVD method will be explained in detail.

Here, an example is shown in which the inside of the contact hole is filled by the CVD method, and then metal is deposited on the entire surface of the insulating film by the well-known sputtering method and then buttered. The present invention improves the method of forming wiring on an insulating film and provides an even more excellent method of forming wiring.

Therefore, the following explanation will help you understand whether the film deposited by this CVD method has excellent properties and how it is an excellent method for forming wiring for semiconductor devices. Will.

(Film Forming Method) A film forming method suitable for forming the electrode according to the present invention will be described below.

This method is suitable for filling a contact hole with a conductive material in order to form an electrode having the above-described structure.

A film forming method suitable for the present invention is one in which a deposited film is formed on an electron-donating substrate by a surface reaction using an alkyl aluminum hydride gas and hydrogen gas (
(hereinafter referred to as the Al-CVD method). In particular, high-quality AILH can be deposited by using monomethylaluminum hydride (MMAH) or dimethylaluminum hydride (DMAH) as the raw material gas, using H2 gas as the reaction gas, and heating the substrate surface under a mixture of these gases. I can do it. Here, during Ai1 selective deposition, it is preferable to maintain the surface temperature of the substrate at a temperature higher than or equal to the decomposition temperature of the alkyl aluminum hydride and lower than 450°C by direct heating or indirect heating, more preferably higher than or equal to 260°C and lower than 450°C.
The temperature should preferably be 40°C or lower.

Methods for heating the substrate to the above temperature range include direct heating and indirect heating. In particular, if the substrate is maintained at the above temperature by direct heating, a high quality Al film can be formed at a high deposition rate. For example, the substrate surface temperature at the time of forming the An film is set to a more preferable temperature range of 260°C to 440°C.
℃, a high quality film can be obtained at a deposition rate higher than that in the case of resistance heating, which is 3000 to 5000 people/min. As a method of such direct heating (energy from the heating means is directly transmitted to the substrate to heat the substrate itself), for example, lamp heating using a halogen lamp, a xenon lamp, etc. can be used. In addition, there is resistance heating as a method of indirect heating, which uses a heating element etc. provided on a substrate support member disposed in a space for forming a deposited film to support the substrate on which the deposit is to be formed. I can do it.

By applying the CVD method to a substrate in which an electron-donating surface portion and a non-electron-donating surface portion coexist, Af
A single crystal of l is formed. This Al1 has excellent properties desired as an electrode/wiring material. In other words, the probability of occurrence of hillocks and the probability of occurrence of alloy spikes are reduced.

This is because high quality A℃ can be selectively formed on a surface made of a semiconductor or conductor as an electron-donating surface, and because the A and Q have excellent crystallinity, they can be easily bonded to the underlying silicon, etc. It is thought that the formation of alloy spikes due to eutectic reactions is hardly observed or extremely small. When used as an electrode in a semiconductor device, effects that go beyond the conventional concept of the A1 electrode and that could not be expected using conventional techniques can be obtained.

As mentioned above, it has been explained that Al2 deposited on an electron-donating surface, for example, in an opening formed in an insulating film and exposing the surface of a semiconductor substrate, has a single crystal structure.
According to this method, it is possible to selectively deposit metal films mainly composed of Al as shown below, and the film quality also exhibits excellent characteristics.

For example, in addition to alkyl aluminum hydride gas and hydrogen, S jH4, S 12Ha, S 13Ha, Si(C
H3) 4, S z C11a, S I H2Cβ2,
Gas containing Si atoms such as S i HCIt 3, Ti
CJ2. , TiBr4, Ti (CH3)4, etc.
Gas containing atoms, bisacetylacetonatocopper Cu ((:5LO2) 2
, bisdipivaloyl methanite copper Cru (C11Hre
02) 2, bishexafluoroacetylacetonatocopper C
A suitable combination of gases containing Cu atoms such as u (C5HF602) 2, etc. is introduced to create a mixed gas atmosphere, for example, A11-St, Al2-Ti%Aj2-Cu%AJ.
2-3i-Ti, AJ! Electrodes may be formed by selectively depositing a conductive material such as -3i-Cu.

In addition, since the Al-CVD method is a film forming method with excellent selectivity and the surface properties of the deposited film are good, a non-selective film forming method is applied to the next deposition step. The selectively deposited An11 mentioned above! By forming a metal film containing 81 or A1 as a main component also on 5in3 or the like as an insulating film, it is possible to obtain a suitable metal film with high versatility as wiring for semiconductor devices.

Specifically, such a metal film is as follows. Selectively deposited AjZ, Al1-5L, A11-Ti
%A11-Cu, Al1-5i-Ti.

Al-3i-Cu and non-selectively deposited Al2, Al2
-Si, Al2-Ti, Al-Cu, Al
Examples include combinations with 1-3i-Ti and Al-3i-Cu.

As a film forming method for non-selective volume, the above-mentioned Al-C
There are CVD methods, sputtering methods, etc. other than the VD method.

(Film Forming Apparatus) Next, a film forming apparatus suitable for forming the electrode according to the present invention will be described.

FIGS. 6 to 9 schematically show a continuous metal film forming apparatus suitable for the above-described film forming method.

As shown in FIG. 6, this metal film continuous forming apparatus includes a load lock chamber 311 which is connected to each other by gate valves 310a to 310f so as to be able to communicate with each other while shutting off the outside air, and a CVD reaction chamber as a first film forming chamber. 312, Rf etching chamber 313, sputtering chamber 314 as a second film forming chamber,
Each chamber is configured to be evacuated and depressurized by exhaust systems 316a to 316e, respectively. Here, the load lock chamber 31
Reference numeral 1 denotes a chamber for replacing the substrate atmosphere before the deposition process with an H2 atmosphere after exhausting in order to improve throughput performance. The next CVD reaction chamber 312 is a chamber in which selective deposition is performed on the substrate by the above-mentioned 81-CV [) method under normal pressure or reduced pressure, and the substrate surface to be deposited is heated to at least 200° C.
A substrate holder 318 having a heating resistor 317 that can be heated in the range of 450° C. is provided inside, and a CVD
A bubbler 3 is installed indoors through the raw material gas introduction line 319.
In step 19-1, raw material gas such as alkyl aluminum hydride, which has been bubbled with hydrogen and vaporized, is introduced.
Further, hydrogen gas as a reaction gas is introduced from the gas line 319'. The next Rf etching chamber 313 is a chamber for cleaning (etching) the surface of the substrate after selective deposition in an Ar atmosphere, and inside there is a substrate holder 320 that can heat the substrate to at least 100°C to 250°C. and Rf etching electrode line 3
21, and an Ar gas supply line 32.
2 are connected. The next sputtering chamber 314 is a chamber for non-selectively depositing a metal film on the substrate surface by sputtering in an Ar atmosphere, and has an internal temperature of at least 200°C to 200°C.
A substrate holder 323 heated in a range of 50°C and a target electrode 32 to which a sputter target material 324a is attached.
4 is provided, and an Ar gas supply line 325 is provided.
is connected. The last load lock chamber 315 is an adjustment chamber before the substrate is exposed to the outside air after the metal film deposition is completed.
It is configured to replace the atmosphere with N2.

FIG. 7 shows another configuration example of a continuous metal film forming apparatus suitable for applying the above-described film forming method, and the same parts as those described above are given the same reference numerals. The difference from the device in FIG. 7 is that a halogen lamp 330 is used as a direct heating means.
is provided, and the substrate surface can be directly heated.
To this end, the base holder 312 is provided with a claw 331 that holds the base in a floating state.

With this configuration, by directly heating the substrate surface, it is possible to further improve the deposition rate as described above.

As shown in FIG. 8, the metal film continuous forming apparatus having the above configuration actually includes the load lock chamber 311, the CVD reaction chamber 312, the Rf etching chamber 313, the sputtering chamber 314, and the transfer chamber 326 as a relay chamber. This is substantially equivalent to a structure in which the load lock chambers 315 are interconnected. In this configuration, the load lock chamber 311 is
It also serves as 5. As shown in FIG. 8, the transfer chamber 326 is provided with an arm 327h) as a transfer means that can rotate forward and backward in the AA direction and extend and retract in the BB direction. As shown by the arrows inside, the substrate is sequentially placed in the load lock chamber 3]1 according to the process.
It is now possible to move the film continuously from the CVD chamber 312, Rf etching chamber 313, sputtering chamber 314, and rotor-rotter chamber 315 without exposing it to outside air.

(Film Forming Procedure) A film forming procedure for forming electrodes and wiring according to the present invention will be described.

FIG. 10 is a schematic perspective view for explaining the film forming procedure for forming electrodes and wiring according to the present invention.

First, I will explain the outline. A semiconductor substrate with openings formed in an insulating film is prepared, and this substrate is placed in a film forming chamber, its surface is maintained at, for example, 260°C to 450°C, and DMAH gas and hydrogen gas are mixed to form an alkyl aluminum hydride. All is selectively deposited on the exposed portion of the semiconductor inside the opening by thermal CVD in a mixed atmosphere. Of course, as mentioned above, by introducing a gas containing 51 atoms etc., Aj2-5
A metal film mainly composed of Afl, such as i, may be selectively deposited. Next, a metal film containing Al or AJ2 as a main component is non-selectively formed on the selectively deposited AJ2 and the insulating film by sputtering. Thereafter, electrodes and wiring can be formed by patterning the non-selectively deposited metal film into a desired wiring shape.

Next, a substrate is prepared, which will be explained in detail with reference to FIGS. 7 and 10. The base is prepared, for example, by forming an insulating film with openings of various diameters on a single-crystal Si wafer.

FIG. 10(A) is a schematic diagram showing a part of this base. Here, 401 is a single crystal silicon substrate as a conductive substrate, and 402 is a thermally oxidized silicon film as an insulating film (layer). 403 and 404 are openings (exposed parts),
Each has a different caliber.

The procedure for forming the A and Q films, which will become the electrodes as the first wiring layer, on the substrate is as follows with reference to FIG.

First, the base body described above is placed in the load lock chamber 311. Hydrogen is introduced into this load lock chamber 31+ as described above to create a hydrogen atmosphere. And exhaust system 316b
The inside of the reaction chamber 3]2 is evacuated to approximately IX+0-6 Torr. However, the degree of vacuum in the reaction chamber 312 is 1xlO-8
Even if it is worse than Torr, a film of /12 can be formed.

Then, the DMA bubbled from the gas line 319
Supply H gas. H2 is used as the carrier gas for the DMAH line.

The second gas line 319° is for H2 as a reaction gas, and H2 is flowed from this second gas line 319°,
The reaction chamber 3 is opened by adjusting the opening degree of a slow leak valve (not shown).
12 to a predetermined value. A typical pressure in this case is approximately 1.5 Torr. DM from DMAH line
AH is introduced into the reaction tube. Total pressure approximately 1.5 Torr
, the DMAH partial pressure is approximately 5.0xlO-3Torr.

Thereafter, the halogen lamp 330 is energized to directly heat the wafer. In this way, Al1 is selectively deposited.

After a predetermined deposition time has elapsed, the supply of DMAH is temporarily stopped. The predetermined deposition time for one film deposited in this process is defined as the period until the thickness of the Al1 film on Si (single crystal silicon substrate 1) becomes equal to the film thickness of SiO2 (thermally oxidized silicon film 2). This time can be determined in advance by experiment.

At this time, the temperature of the substrate surface due to direct heating is approximately 270°C. According to the steps up to this point, the Le film 405 is selectively deposited inside the openings as shown in FIG. 10(B).

The above process is referred to as a first film forming process for forming an electrode in a contact hole.

After the first film forming step, the CVD reaction chamber 312 is
6b until a vacuum level of 5×10 −3 Torr or less is reached. At the same time, the Rf etching chamber 313 is
Evacuate to below X10-'Torr. After confirming that both chambers have reached the above degree of vacuum, the gate valve 310c is opened and the substrate is transported from the CVD reaction chamber 312 to the R
f Move to the etching chamber 313 and open the gate valve 310c.
Close. The substrate is transferred to the Rf etching chamber 313, and the Rf etching chamber 313 is heated to 1O-6 by the exhaust system 316c.
Evacuate until the degree of vacuum reaches Torr or less. Then R
Argon is supplied through the f-etching argon supply line 322, and the Rf-etching chamber 313 is
- Maintain an argon atmosphere of 3 Tor'r. Keep the Rf etching substrate holder 320 at about 200°C, and
Apply Rf power of 100W to the etching electrode 321 at 60°C.
The argon is supplied for about a second to cause argon discharge in the Rf etching chamber 313. In this way, the surface of the substrate is etched with argon ions, and unnecessary surface layers of the CVD deposited film can be removed. In this case, the etching depth is approximately 100 degrees equivalent to the oxide. Here, the surface of the CVD deposited film was etched in the Rf etching chamber, but the CVDII of the substrate being transported in vacuum was
Since the surface layer of U does not contain atmospheric oxygen, Rf
You can't beat it even without etching. In that case, Rf
The etching chamber 313 functions as a temperature changing chamber for changing the temperature for a short time when the temperature difference between the CVD reaction chamber 12 and the sputtering chamber 314 is large.

After the Rf etching is completed in the Rf etching chamber 313, the flow of argon is stopped and the argon in the Rf etching chamber 313 is exhausted.

After the Rf etching chamber 313 is evacuated to 5X10-' Torr and the sputtering chamber 314 is evacuated to 5X10-6 Torr or less, the gate valve 310d is opened. Thereafter, the substrate is moved from the Rf etching chamber 313 to the sputtering chamber 314 using a transport means, and the gate valve 310d is closed.

After transporting the substrate to the sputtering chamber 314, the sputtering chamber 3
14 to 10-' to 10 similarly to the Rf etching chamber 313.
An argon atmosphere of -3 Torr is created, and the temperature of the substrate holder 323 on which the substrate is placed is set to about 200 to 250°C. Then, argon discharge is performed with a DC power of 5 to 10 kW, and An or A℃-5j (Si:0.
5%), etc., with argon ions.
A metal such as AJt-5i or AJt-5i is deposited on a substrate at a deposition rate of about 10,000 people/minute. This process is a non-selective deposition process. The second layer is used to form wiring that connects this to the electrode.
This is called a film forming process.

After forming about 5000 metal films on the substrate, the flow of argon and the application of DC power are stopped. After evacuating the load lock chamber 311 to below 5xlO-3 Torr,
The gate valve 310e is opened and the substrate is moved. After closing the gate valve 310e, apply N to the load lock chamber 311.
2. Flow the gas until it reaches atmospheric pressure and gate valve 310f
Open it and take the substrate out of the device.

According to the second film forming step described above, the AIL film 406 can be formed on the Si 02 film 402 as shown in FIG. 10(C).

Then, by patterning this All@406 as shown in FIG. 10(D), wiring in a desired shape can be obtained.

(Experimental Example) The superiority of the above layer-CVD method and the high quality of the An deposited in the openings will be explained below based on experimental results.

First, the surface of an N-type single-crystal silicon wafer was thermally oxidized as a base to form a 5in2 of 8,000 people and 0.25μm x
A plurality of openings with various diameters ranging from 0.25 μm square to 100 μrl×100 μm square were patterned to expose the underlying Si single crystal. (Sample 1-1) The dough was treated with Al by the Al-CVt1 method under the following conditions.
One film was formed. DMAH as raw material gas, hydrogen as reaction gas, total pressure 1.5 Torr, DMA8 partial pressure 5
．． Under the common condition of Oxl O"" Torr, film formation was performed by adjusting the amount of power supplied to the halogen lamp and setting the substrate surface temperature in the range of 200° C. to 490° C. by direct heating.

As can be seen from Table 1, the substrate surface temperature due to direct heating is 2.
Above 60° C., A1 was selectively deposited within the open pores at a high deposition rate of 3000-5000 per minute. .

When examining the characteristics of the Al2 film inside the openings when the substrate surface temperature was in the range of 260°C to 440°C, it was found that there was no carbon content, resistivity 2.8 to 3.4 μΩCm, reflectance 90 to 95%, 1
It was found that the hillock density of .mu.m or more was 0 to 10 cm.sup.-2, and it had good characteristics with almost no spike occurrence (probability of failure of a 0.15 .mu.m junction).

On the other hand, when the substrate surface temperature is 200°C to 250°C,
Although the film quality is slightly worse than in the case of 260°C to 440°C, it is a fairly good film from the perspective of conventional technology, but the deposition rate is not high enough at 1000 to 1500 people/min, and the throughput is also low. It was relatively low at 7-10 sheets/h.

In addition, when the substrate surface temperature is 450°C or higher, the reflectance is 60% or less, and the hillock density of 1 μm or more is 10 to 10'.
cm-2, the occurrence of alloy spikes was 0 to 30%, and the properties of the All film inside the openings were degraded.

Next, it will be explained how the method described above can be suitably used for openings such as contact holes and through holes.

That is, it is preferably applied to contact hole/through hole structures made of the materials described below.

Al was deposited on a substrate (sample) having the structure described below under the same conditions as when Al was deposited on Sample 1-1 described above.
A film was formed.

A silicon oxide film as a second substrate surface material is formed by the C'VD method on the single crystal silicon as the first substrate surface material, and patterned by a photolithography process to partially cover the single crystal silicon surface. was discharged.

The thickness of this thermally oxidized 5i02 film is 8000 mm, and the exposed area of single crystal silicon, that is, the size of the opening, is 0.25 μm x
It was 0.25 μm to 100 μm×1 oo μm.

Sample 1-2 was prepared in this way. (Hereinafter, such a sample will be referred to as "CVDSiO2 (hereinafter abbreviated as 5in2)/single crystal silicon").

Sample】-3 is a boron-doped oxide film (hereinafter abbreviated as BSG)/single crystal silicon formed by atmospheric pressure CVD, Sample 1-4 is a phosphorous-doped oxide film (hereinafter abbreviated as PSG)/ Sample 1-5 is a phosphorus and porontope oxide film (hereinafter abbreviated as BSPG)/single crystal silicon formed by atmospheric pressure CVD, and Sample 1-6 is a nitride film (hereinafter referred to as P-) formed by plasma CVD. 5iN)/RL crystal silicon, Sample 1-7 is thermal nitride film (hereinafter abbreviated as T-3iN)/
Single-crystal silicon, Sample 1-8 is a nitride film (
Hereinafter abbreviated as LP-5iN)/single-crystal silicon sample 1-9 is a nitride film (hereinafter abbreviated as LP-5iN) formed by an ECR device.
(hereinafter abbreviated as ECR-3iN)/single crystal silicon.

Furthermore, samples 1-11 to 1-179 (/subject, sample number 1-
10.20, 30.40.50.60.70.80.9
0,100,110°120.130,140,150
, 160, 170 are missing numbers). Single crystal silicon (single crystal Si), polycrystalline silicon (polycrystalline Si), amorphous silicon (amorphous Si) as the first substrate surface material
, tungsten (W), molybdenum (MO), tantalum (Ta), tungsten silicide (WSi), titanium silicide (TiSi).

Aluminum (An), aluminum silicon (Al-
Si), titanium aluminum (AJZTi), titanium nitride (Ti-N), copper (Cu), aluminum silicon copper (An-SiCu), aluminum palladium (AjZ-Pd), titanium (T i ), molybdenum silicide (Mo -3i), tantalum silicide (Ta
-3i) was used. The second substrate surface material is T-
Si02, S i02, BSG, PSG, BPS
G, PSiN, T-3iN, LP-3iN, ECR51
It is N. For all of the samples described above, it was possible to form good Al2 films comparable to those of sample 1-1 described above.

Next, on the substrate on which Al1 was selectively deposited as described above, An was non-selectively deposited and patterned by the sputtering method described above.

As a result, the Al1 film produced by the sputtering method and the ρ film selectively deposited inside the openings have good electrical and mechanical durability due to the good surface properties of the Al2 film inside the openings. It was in contact status.

(Example 1) <Circuit Description> As this example, a method for forming wiring in an An two-layer wiring process, particularly an upper A-fi layer, in a semiconductor integrated circuit will be described. FIG. 3 shows the connection of the Aj2 pattern shown in this embodiment. FIG. 3 shows a small portion of the grid-like An wiring pattern. In FIG. 3, 108 is the connection of the upper layer AJ2, and 109a and 109b are the connections of the lower layer AI.

110 is the intersection of 109b and 108, and the black dot indicates that both are connected via a through hole. On the other hand, there is no through hole pattern at the intersection 111 between 109a and 108, and the two are not connected. In this way, a custom LSI such as a gate array can be constructed by adopting a method of determining the presence or absence of a connection based on the presence or absence of a through hole. In other words, the process up to the opening of the through-holes is performed in advance, and the presence or absence of through-holes is determined according to the circuit ordered by the customer, and the circuit is formed.

<Description of Apparatus for Forming Wiring> FIG. 1 is a style diagram showing the concept of a system for focused ion beam irradiation that can be suitably applied to this embodiment. The pattern data of the upper layer Aj2 is converted by an arithmetic circuit to provide data for controlling the ion beam.

101a is a focused ion beam source having an ion beam source, an ion optical system, and an electrostatic lens system. 1.01
The ion beam generated within the aperture and whose direction is controlled by an ion optical system and an electrostatic lens system is irradiated onto the semiconductor substrate 104 through the opening 101b.

FIG. 2 shows how a pattern is drawn by irradiation with an electron beam. In FIG. 2, 105 represents an ion source, an ion optical system, and an electrostatic lens system, 106 represents an ion beam east, 104 represents a semiconductor substrate, and 107 represents an irradiated ion beam pattern.

<Method for Forming Wiring> Next, a method for forming the AA wiring in this example will be described with reference to FIGS. 1 to 5. As described above, data of the wiring pattern of the upper layer A° C. is prepared as the pattern data. The lower Afl wiring, the insulating film covering it, and the semiconductor substrate 104 to be irradiated with an ion beam, which has a through hole for connecting the upper layer AJ2 and the lower layer AJZ, are placed in a chamber 102 serving as a drawing chamber. After drawing a wiring pattern using an ion beam as shown in FIG. 2, the semiconductor substrate is taken out from the chamber 102. The situation at this time is shown in FIG. In FIG. 4, 120 is the active region of the silicon substrate, 121 is the lower layer Afl wiring, and 12
2 is an insulating film, 123 is an ion beam or irradiated area,
124 is a through hole opening.

Next, the wafer is placed in a chamber for Afl vapor phase growth,
DMAH as alkyl aluminum hydride (
Dimethyl Aluminum)Iydr
ide) Using AlH(CI-13)2 gas and hydrogen as reaction residue, at a substrate surface temperature of around 290°C, Al1 is deposited on the ion beam irradiated area 123 and at the same time inside the through hole 124. Also, An is deposited. The Afl film thickness at this time is approximately 8,000 people. Figure 5 shows the situation immediately after this. Thereafter, heat treatment is performed at 400° C. for about 30 minutes in a nitrogen atmosphere to improve the ohmic contact between the upper layer A° C. and the lower Al layer, and to obtain a sufficiently low contact resistance.

Experimental Example> A plurality of samples having shapes as shown in FIG. 5 were created by irradiating An ions as an ion beam according to the procedure described above.

These samples have a width (line width) of the upper layer AJ2 of 0.
25-2 μm, distance I between upper layer AjZ! (space width) was set to 0.25 to 2 μm, and the layer thickness of the lower layer Aj2 was changed so that the maximum step difference was set to 0.6 to 2.4 μm.

Comparative Example> Similar to the experimental example described above using the conventional method (λ = 186 nm, NA = 40), the width (line width) of the upper layer An was 0.2
5 to 2 μm, distance 11 (space width) between upper layer AJZ to 0
．． The thickness of the lower layer Aj2 was changed to 25 to 2 μm, and the maximum step difference was 0.5 to 2.0 μm.

<Comparison result> Table 2 Note: The evaluation column is for this example/conventional example.

In this way, the quality of the shape of the upper layer AJ2 wiring of samples created by the experimental example according to the present invention and the conventional method was evaluated by comparing the level difference and the AJ2 wiring shape.
Table 2 shows the L/S of 2 as a parameter. ◎ marks are those with extremely good buttering, ○ marks are those with almost good buttering,
The Δ mark indicates that the pattern has sagged to some extent, and the X mark indicates that a defect such as a short between wirings has occurred. According to the experimental examples according to the present invention, wiring could be formed without causing defects between wirings such as short circuits under any of the conditions in Table 2, as shown in the upper left of the evaluation column.

On the other hand, with the conventional method, it was not possible to form a pattern with a step difference of 1.0 μm or more or an L/S of 0.25 μm without causing defects between wirings, as shown in the lower right of the evaluation column. According to this example, since the surface is modified using ions as charged particles, there is little change over time in the electron-donating surface, so that film formation with good reproducibility can be performed stably over a long period of time.

Furthermore, since an ion beam is used, there is very little charge-up on the substrate when drawing a wiring pattern, resulting in excellent controllability of the wiring width.

Furthermore, when hydrogen ions or Aj2 ions are selected as charged particles using the AJ2-CVD method, a film having even better characteristics as a wiring can be formed with high precision due to the reaction system.

Effects of the present invention> ■An anti-reflection layer and resist forming process are no longer required;
Since the process becomes easier, the yield, which was conventionally limited by poor buttering, can be greatly improved.

■A desired wiring pattern can be formed even on large steps.

■It is effective for miniaturizing chips because it can draw patterns as fine as the beam diameter of the beam source.

(2) By using selective vapor phase epitaxy, highly reliable wiring with good step coverage is possible even when miniaturized.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram of a charged particle irradiation system for carrying out the present invention, Fig. 2 is a schematic explanatory diagram for explaining selective irradiation of charged particles according to the present invention, and Fig. 3 is a schematic diagram according to the present invention. FIGS. 4 and 5 are schematic diagrams for explaining the wiring pattern, FIGS. 4 and 5 are schematic perspective views for explaining the process of the wiring forming method of the present invention, and FIGS. 6 to 9 are for carrying out the present invention. 10 is a schematic perspective view for explaining the film forming procedure of the wiring forming method according to the present invention, and FIG. 11(A) to 11 Figure (C) is a schematic perspective view for explaining the conventional wiring forming method, Figure 12 (A) and Figure 1.
FIG. 2(B) is a schematic diagram for explaining the prior art. 121... Lower layer A, Q wiring 122... Insulating film 123... Area irradiated with charged particles 311... Load lock chamber 312... CVD reaction chamber 3... Etching chamber 4... Sputtering chamber 6... Transfer chamber 2... Insulating film 3.404... Opening 5... Selectively formed conductive metal film 6... Non-selectively formed conductive metal 5 sides of membrane (2 holes 12 times (c) μl V

Claims (5)

[Claims] (1) In a method for forming wiring in a semiconductor device having an insulating film on an insulating film, a portion of the insulating film where a wiring is to be formed is selectively irradiated with charged particles to deposit a conductive metal substance. A method for forming wiring in a semiconductor device, the method comprising the step of selectively depositing a conductive metal substance on the irradiated portion. (2) A method for forming wiring in a semiconductor device, in which the conductive metal substance is deposited by a CVD method using an alkyl aluminum halide gas and hydrogen. (3) The method for forming interconnects in a semiconductor device according to claim 1, wherein the charged particles are a focused ion beam. (4) The method for forming interconnects in a semiconductor device according to claim 1, wherein the conductive metal material is Al. (5) The method for forming interconnects in a semiconductor device according to claim 1, wherein the conductive metal substance is a metal substance containing Al as a main component.