JPH04369272A - Composite diode - Google Patents

Abstract

PURPOSE:To improve reverse recovery characteristic of a composite diode and to easily enhance a breakdown voltage by connecting a pair of opposite conductivity type field effect transistors diode-connected to each other in anti- parallel with each other. CONSTITUTION:A pair of opposite conductivity type field effect transistors 10, 20 are diode-connected to each other, and both are connected in anti-parallel with each other to form a composite diodes having a pair of terminals P, N. For example, the transistor 10 is an electron conductive n-channel type, the transistor 20 is a hole conductive p-channel type, and both are short-circuited between a gate terminal G and a source terminal to be diode-connected. Accordingly, the electrons and the holes are rapidly absorbed, for example, into p-type and n-type drain layers without reinjections of opposite polarity holes and electrons.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite diode suitable for high-speed operation and composed of diode-connected field effect transistors.

0002

[Prior Art] Circuit devices such as inverters, chopper devices, and switching regulators are becoming increasingly high-frequency, and the performance of diodes used for rectification in these circuits is first of all high-speed operation. In addition, performance such as high voltage resistance that can sufficiently withstand the circuit voltage used, and low forward voltage drop that can suppress unnecessary power loss is usually required. As is well known, the high-speed operation performance of diodes among these diodes is more problematic during off-operation than on-operation, until the carriers in the bulk semiconductor are completely annihilated and the withstand voltage is fully recovered. Reducing the so-called reverse recovery time is most important in improving high-speed operation.

[0003] So-called high-speed diodes, which mainly have a three-layer pin structure, have been used to meet this requirement for high-speed operation. As is well known, diodes with this pin structure have the necessary breakdown voltage in their i-layer, and in order to speed up reverse recovery, so-called lifetime killer atoms such as platinum or gold are introduced to prevent off-operation. This promotes the disappearance of positive and negative carriers within the bulk of time.

[0004] Schottky barrier diodes are also suitable for high-speed operation. As is well known, this method utilizes the rectifying effect of the Schottky barrier that occurs between a metal and a semiconductor when they are brought into direct contact with each other, and since almost no carriers accumulate near the barrier, the reverse recovery time is essentially short. It has the advantage of a shorter forward voltage drop and a smaller forward voltage drop than a junction diode.

[0005]

[Problem to be solved by the invention] However, the above pi
Both n-diodes and Schottky barrier diodes have their own advantages and disadvantages as described below.

[0006] A high-speed diode with a pin structure has the advantage that the breakdown voltage can be set to a desired value depending on the thickness of its i-layer, but if the amount of lifetime killer introduced to shorten the reverse recovery time is increased too much, the forward voltage drop becomes large. Therefore, in practice, the reverse recovery time cannot be reduced below a certain limit due to this restriction. For example, if the forward voltage drop is suppressed to 10% higher than that of a normal diode, the reverse recovery time is typically 30ns.
This is the limit, and it is extremely difficult to reduce it below that level.

Although Schottky barrier diodes are very advantageous in terms of reverse recovery time and forward voltage drop, they have the problem of considerably large reverse leakage current when turned off, so they are unsuitable for applications where this is a problem. In addition, there is the problem that it is difficult to increase the withstand voltage, and although it is possible to improve it somewhat by sacrificing the forward voltage drop, there is a limit to that, so it is not possible to achieve as high a withstand voltage as with a PIN diode. .

For this reason, recently, a diode called a spin structure, which combines a pin structure and a Schottky barrier, has been attempted in order to obtain the advantages of both types of diodes (IEEE Electro
n Device Let. , EDL-8, p.
407, 1987), it is not necessarily easy to combine only the advantages of both, and the reality is that the disadvantages are more likely to emerge, especially in high voltage diodes. Furthermore,
High-speed diodes using semiconductor materials other than silicon, such as GaAs and SiC, are also being considered, but apart from very small diodes, they are not yet sufficiently practical for power applications due to economic efficiency and other considerations.

In view of the current situation, it is an object of the present invention to provide a diode that can solve the conventional restrictions on reverse recovery time while increasing the speed of operation while maintaining practicality in terms of materials and manufacturing. .

0010

[Means for Solving the Problem] According to the invention, this object is achieved by providing two diode-connected circuits of opposite conductivity type.
This is accomplished by connecting pairs of field effect transistors in antiparallel to form a composite diode.

Note that the diode connection in the above structure may be achieved by short-circuiting the gate of each field effect transistor, for example, with its source as usual. In addition, in the composite diode according to the present invention, the pair of field effect transistors constituting the diode are of opposite conductivity type or opposite channel type, so that when they are connected in antiparallel, one of the n-channel type The p-channel type operates exclusively as an electron conductor, and the p-channel type operates as an exclusively hole conductor.

[0012] As a practical configuration of this composite diode, a pair of field effect transistors are each connected as separate chips with a vertical structure, and the two chips are connected in antiparallel, or they are each connected as separate chips with a horizontal structure. It is advantageous to connect two chips stacked one above the other in antiparallel.

[0013]

[Operation] The present invention focuses on the fact that the true cause of the problem is that positive and negative carriers, that is, electrons and holes, coexist in the internal current path of a diode with a pin structure. This problem is solved by combining effect transistors to form a composite diode and separating the current paths through which electrons and holes flow for each field effect transistor.

That is, in a pin diode, during its on state, electrons and holes coexist in the bulk of the i-layer, for example, and move in opposite directions to each other, forming a current, and during its off-state, electrons move in the bulk of the p-type layer. On the other hand, when the holes finish moving toward the n-type layer and there are no more carriers in the bulk, a reverse recovery state occurs, but when electrons are absorbed by the p-type layer and holes are absorbed by the n-type layer, At the same time, holes and electrons are re-injected into the bulk respectively, so in reality, carriers in the i-layer are not easily annihilated and it takes time for complete reverse recovery. Lifetime killer speeds up reverse recovery by trapping carriers in the bulk and annihilating them, but of course carriers are always annihilated even in the on state, so if too large a quantity is introduced, the forward voltage drop will increase. This is the reason why reverse recovery time cannot be shortened as expected.

Therefore, in the present invention, a pair of diode-connected field effect transistors is used, one of which is an electron-conducting n-channel type, and the other a hole-conducting p-channel type, and both are connected in antiparallel. By forming a composite diode, electrons and holes as carriers flow exclusively into the n-channel type and p-channel type field effect transistors, respectively. Therefore, in the present invention, electrons and holes are quickly absorbed into p-type and n-type drain layers, for example, without reinjecting holes or electrons of opposite polarity, so there is no need to introduce a lifetime killer. Reverse recovery time can be shortened. In addition, since the field effect transistor in the on state is a unipolar element and does not include the weir layer voltage associated with the pn junction as in the case of bipolar,
The forward voltage drop of the composite diode according to the present invention is essentially small.

[0016]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing an example of the basic configuration of a composite diode according to the present invention.

As shown in FIG. 1, in the present invention, a pair of field effect transistors 10 and 20 of opposite conductivity types are diode-connected, and then connected in antiparallel to provide a pair of terminals P and N. Use a composite diode. In the example of FIG. 1, the field effect transistor 10 is an electron conductive n-channel type, and the field effect transistor 20 is a hole conductive p channel type, and both have a gate terminal G and a source terminal S. A diode connection is established by short-circuiting between the two terminals. When the composite diode formed by connecting these field effect transistors 10 and 20 in antiparallel is on, a current with electrons e as carriers flows only within the n-channel field effect transistor 10 from terminal N to terminal P. flowing towards
A current using holes h as carriers flows from the terminal P to the terminal N only in the p-channel field effect transistor 20.

FIG. 2 shows an embodiment in which a pair of field effect transistors 10 and 20 are each configured on separate chips with a vertical structure. All the semiconductor regions in the chips of these field effect transistors 10 and 20 are of opposite conductivity type to each other as shown in the figure, and since both are vertical, the drain region 1
Epitaxial layers are grown as drain layers 12 and 22 on the substrates 1 and 21, and channel forming layers 13 and 23 are diffused, and polycrystalline silicon gates 14 and 24 are formed on the surfaces thereof with gate oxide films 14a, respectively. and 21a, and the source layers 15 and 25 are shallowly diffused.

On the surface side of the chip, interlayer insulating films 16 and 26
The regate 14 is formed by the metal electrode films 17 and 27 disposed above.
and 24 are short-circuited with source layers 15 and 25 to form a diode connection state, and on the back side, electrode films 17 and 27 connected to drain regions 11 and 21 are provided for drain terminals. In addition,
The chip structure shown in FIG. 2 is a unit structure of a field effect transistor, and in reality, the unit structure shown in the figure is repeatedly provided in the horizontal direction a plurality of times depending on the current capacity.

The chips of the pair of field effect transistors 10 and 20 are connected in antiparallel as shown, and a pair of diode terminals P and N are led out. In the ON state of this composite diode, electrons e as single carriers are transferred from the n-type source layer 15 to the surface of the p-type channel forming layer 13 below the gate 16 on the n-channel field effect transistor 10 side. Through the formed n-type channel, it flows toward the n-type drain layer 12 and the drain region 11, and on the p-channel field effect transistor 20 side, holes h as a single carrier flow into the p-type source layer 25. From gate 2
It flows toward the p-type drain layer 22 and the drain region 21 through a p-type channel formed on the surface of the n-type channel forming layer 23 under the p-type drain layer 22 and the drain region 21 .

[0021] When a reverse voltage, that is, a positive voltage is applied to the negative terminal N during the off-operation of this composite diode, the depletion layer mainly extends into the drain layers 12 and 22 and the electrons in the bulk are e and hole h are drain regions 11 and 21
However, since these are all single carriers and are absorbed from the drain layers 12 and 22 into the drain regions 11 and 21 of the same conductivity type, re-injection of carriers of opposite polarity does not occur. The carriers in the bulk are rapidly depleted and the reverse recovery state is reached in a much shorter time than in the case of a pin fast diode. As a result of trial manufacturing of a composite diode with a withstand voltage of several hundred volts with the structure shown in FIG. 2, an extremely short reverse recovery time of about several ns was obtained without introducing a lifetime killer.

The breakdown voltage of the composite diode of the embodiment shown in FIG. 2 is determined mainly by the thickness of the drain layers 12 and 22 in which the depletion layer extends, as described above, and is 500 to 600.
When a breakdown voltage of V is required, the thickness is set to about 50 to 60 μm. Further, the impurity concentration of each part is, for example, approximately 1019 atoms/cm3 for the drain regions 11 and 21, approximately 1016 atoms/cm3 for the drain layers 12 and 22, and 1016 to 1017 atoms/cm3 for the channel forming layers 13 and 23.
3 range, source layers 15 and 25 at 1020 atoms/c
It is best to set each to about m3, and the source layer 15
The diffusion depth of the channel forming layers 13 and 23 may be as shallow as about 1 μm, but the depth of the channel forming layers 13 and 23 is preferably deeper, for example, about 15 μm.

In the present invention, as described above, electrons e flow exclusively into one of a pair of field effect transistors, and holes exclusively flow into the other, but since the mobility of the latter is lower than that of the former, FIG.
If the left and right chips are the same size, the current of the p-channel field effect transistor 20 will be smaller than the current of the n-channel field effect transistor 10. There is no problem in principle even if there is such an unevenness of current, but since an unevenness of the current density causes a decrease in the utilization efficiency of the chip area, the size of the diffusion pattern or the unit structure in the chip of the field effect transistor may be affected. It is reasonable to set the number of times of repetition as appropriate to equalize the current density distribution. Of course, it is also possible to make the currents of both field effect transistors 10 and 12 equal by such a setting.

In the embodiment shown in FIG. 3, a pair of field effect transistors 30 and 40 are arranged in a lateral configuration and are fabricated within the same chip. The wafer for this example is a normal CMOS
An n-type epitaxial layer 2 is formed on a p-type substrate 1 as in the case of
A p-type well 31 is diffused within the range surrounded by the isolation insulating film 3 for the n-channel field effect transistor 30, and the gates 32 and 42 are grown through the gate oxide films 32a and 42a. The source layers 33 and 43 and the drain layers 34 and 44 are diffused with predetermined conductivity types, respectively, to form an n-channel field effect transistor 30 with a lateral structure.
and a p-channel field effect transistor 40. The diode connection of each field effect transistor 30 and 40 and the antiparallel connection between them are all made on the front surface side of the chip by the electrode film 5 disposed on the interlayer insulating film 4 as shown in the figure, and then a pair of diodes are connected. Derive terminals P and N.

This embodiment is exactly the same as the previous embodiment shown in FIG. 2 in that the n-channel field effect transistor 30 side is used as an electron conductive component, and the p-channel field effect transistor 40 side is used as a hole conductive component. Similarly, it functions as a composite diode with a short reverse recovery time characteristic of about several ns. Although the embodiment shown in FIG. 3 is not necessarily advantageous in terms of having a high withstand voltage or large current capacity, it can be easily incorporated into an integrated circuit device by a normal wafer process, and it can be used for connections between chips as shown in FIG. This has the advantage that it is not necessary.

In the embodiment shown in FIG. 4, separate chips for field effect transistors 50 and 60 having a horizontal structure are stacked and connected in antiparallel to form a composite diode. The chip of the n-channel field effect transistor 50 has a highly impurity-concentrated n-type source region 52 and a drain region 53 diffused into the ends of a p-type substrate region 51, and has a gate 54 in contact with the source region 52 and a gate It is provided so as to face the substrate region 51 via an oxide film 54a, and is further covered with an insulating film 55 such as a silicon oxide film. Similarly, the chip of the p-channel field effect transistor 60 is
A p-type source region 62 and a p-type drain region 63 are diffused into the ends of a shaped substrate region 61, and a gate 64 is made to be in contact with the source region 62 and to face the substrate region 61 through a gate oxide film 64a. and further covered with an insulating film 65. These field effect transistors 50 and 60 both have a horizontal structure in which a channel is formed on the surface of the substrate region 51 or 61 below the gate 54 or 64.

In this embodiment, the chips of both field effect transistors 50 and 60 are stacked on top of each other by means such as bonding under high temperature to form an integrated chip 70, and electrodes for terminals P and N are provided on the left and right end surfaces. By attaching the film 71, each is diode-connected, and both are connected in antiparallel to form a composite diode. The actual manufacturing method is to bond the chips of both field effect transistors 50 and 60 while they are still in the wafer state, cut the bonded wafer and isolate it into the integrated chip 70 shown in the figure. It is advantageous in terms of manufacturing cost to attach the electrode film 71 in this manner.

In the embodiment shown in FIG. 4 as well, it is possible to construct a composite diode with good reverse recovery characteristics while using field effect transistors 50 and 60 as constituent elements for electron conductivity and hole conductivity, respectively. Exactly the same as the example. Although the composite diode according to this embodiment is not as suitable for high breakdown voltage as the embodiment shown in FIG. 2, it is very easy to combine chips and interconnect them, and the above-mentioned manufacturing method of bonding and then cutting the wafers is adopted. Therefore, it is suitable for mass-produced individual elements, and has the advantage that a structure in which chips are stacked in multiplexes as shown in the figure can be easily adopted.

FIG. 5 shows an embodiment in which a high breakdown voltage composite diode is constructed using such a multiplexed structure. As shown in the figure, the integrated chips 70 of FIG. 4 are stacked with insulating plates 72 interposed in such a manner that the conduction directions are alternately reversed as indicated by the arrows in the figure. In this case as well, the wafers bonded two by two are stacked up by means such as adhesion with insulating plates 72 formed in an appropriate planar pattern interposed therebetween, cut and isolated into the state shown in the figure, and then the electrode film is formed. By attaching 71, the integrated chip 70
The series connection of the diode terminals P and N and the derivation of the diode terminals P and N can be achieved at the same time. Of course, the number of integrated chips 70 is stacked according to the required breakdown voltage value.

Although the embodiments described above are different, the composite diode according to the present invention can be constructed to be suitable for a wide range of voltages and currents, with the embodiment of FIG. 2 being suitable for a large capacity, and the embodiment of FIG. The embodiments of FIGS. 4 and 5 are suitable for intermediate capacities between the two, respectively. For example, in the embodiment shown in FIG. 2, a composite diode having a withstand voltage of several hundred volts and a current capacity of several tens of amperes can be easily constructed. However, there is not much difference in the reverse recovery characteristics between the examples, and the reverse recovery time is theoretically 1 in the small capacity range.
It is also possible to set the capacitance to ns or less, and practically, it is possible to achieve a capacitance of about several ns over a wide capacity range. In this manner, the present invention is not limited to the above-described embodiments, and can be implemented in various forms depending on the required breakdown voltage and current capacity, while ensuring good reverse recovery characteristics.

[0031]

[Effects of the Invention] As described above, in the composite diode of the present invention, the following effects are obtained by configuring a pair of field effect transistors of opposite conductivity types, each diode-connected, connected in antiparallel. be able to.

(a) By separating electrons and holes and flowing them through two diode-connected field effect transistors during on-state, re-injection of carriers of opposite polarity is eliminated when any carrier is absorbed during off-state. Rapidly eliminates carriers in the bulk, reducing diode reverse recovery time to several ns
It can be shortened to a certain extent.

(b) There is no need to introduce a lifetime killer such as a high-speed diode with a pin structure, and the field effect transistor as a component can be easily manufactured using a normal MOS process, simplifying the process and reducing costs. It is possible to provide high-speed diodes of uniform quality, and it can be easily incorporated into integrated circuit devices.

(c) Since the breakdown voltage of the diode can be accurately set mainly by the thickness of the drain layer of the field effect transistor, it is easier to increase the breakdown voltage to a higher voltage than a Schottky barrier diode, and the problem of reverse leakage current is extremely small.

(d) Since each of the pair of field effect transistors constituting the composite diode functions as a unipolar circuit element that does not include a weir layer voltage, the voltage at which the diode turns on can be reduced.

As described above, the present invention has excellent reverse recovery characteristics,
This product provides a highly practical, high-speed operation performance composite diode that can easily be made to withstand a high voltage, is suitable for a wide voltage and current range, and is expected to contribute to improving the performance of high-frequency circuit devices. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the basic configuration of a composite diode according to the present invention.

FIG. 2 is a cross-sectional view of an embodiment in which the composite diode is constructed from a pair of vertical field effect transistors on individual chips;

FIG. 3 is a cross-sectional view of an embodiment in which the composite diode is constructed by a pair of lateral field effect transistors on a common chip.

FIG. 4 is a cross-sectional view of an embodiment in which a composite diode is constructed by stacking a pair of lateral field effect transistor chips.

FIG. 5 is a cross-sectional view of an embodiment of stacking the composite diodes of the embodiment of FIG. 4;

[Explanation of symbols]

Claims (4)

[Claims] 1. A composite diode comprising a pair of field effect transistors connected in antiparallel, each having a conductivity type opposite to the other and each diode-connected. 2. The diode according to claim 1, comprising: 1
1. A composite diode characterized in that a pair of field effect transistors are each formed on a separate chip with a vertical structure, and the two chips are connected in antiparallel. 3. The diode according to claim 1, comprising: 1
A compound diode characterized in that a pair of field effect transistors are each formed as a separate chip with a horizontal structure, and the two chips are stacked one above the other and connected in antiparallel. 4. The diode according to claim 1, wherein 1
A composite diode characterized in that one of a pair of field effect transistors is electron conductive and the other is hole conductive.