JPH04367979A - Circuit diagram editing device - Google Patents

Abstract

PURPOSE:To curtail the time required for generating connection information by generating the connection information of a changed partial circuit, incorporating it to the connection information of the existing partial circuit and generating the connection, information of the whole circuit, in the device for editing a circuit diagram of a semiconductor integrated circuit. CONSTITUTION:A generating/updating means 1 divides a circuit diagram into partial circuit blocks, and generates and updates circuit diagram information by this block unit. A hierarchizing means 2 expands this partial circuit to a logical level chart, and also, expands it to a transistor level chart and hierarchizes it. An incorporating means 5 generates layout verification connecting information by a partial circuit unit, based on the circuit diagram information of the block unit, and incorporates the layout verification connecting information generated to the changed partial circuit to the layout verification connecting information generated to the existing partial circuit. A parameter giving means 4 gives a magnification parameter to gate width of a transistor contained in the transistor level chart of its lower hierarchy, to the logical level chart and/or the partial circuit block.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of Industrial Application The present invention is applied to circuit diagram editing means for semiconductor integrated circuits. In particular, it relates to means for generating and managing circuit diagram information and layout verification connection information.

0002

[Prior Art] In a conventional example, when editing an entire circuit by dividing it into a plurality of partial circuits, the circuit diagrams of the partial circuits are input and the circuit diagrams corresponding to the individual partial circuits are created as shown in FIG. Information is generated. Furthermore, when changing the circuit diagram, the already generated circuit diagram information is changed. The individual circuit diagram information is then merged to generate circuit diagram information for the entire circuit. Layout verification connection information is not generated for each individual partial circuit, but only one piece of connection information is generated for the entire circuit based on the circuit diagram information of the entire circuit. Also,
The gate width of a transistor can be changed by directly changing the gate size parameter defined for each transistor in the transistor level circuit diagram, as shown at 801 in FIG. As shown at 901, the magnification parameter defined for the logic gate one layer higher was changed.

0003

[Problem to be solved by the invention] When designing an LSI, circuit design and layout often proceed simultaneously, and the circuit is often changed depending on the simulation results, and the layout is often changed accordingly. , the number of layout verifications is significantly large. This conventional circuit diagram editing method generates connection information based on the circuit diagram information of the entire circuit, so when some partial circuits are changed, the connection information of the partial circuits that have not been changed is The corresponding parts were also rebuilt from scratch, which had the disadvantage of requiring a lot of time each time a change was made.

[0004] In addition, when changing the gate width of transistors under the upper macroblock uniformly by several times, it is necessary to directly change all the gate width parameters at the transistor level or to define them for the logic gate. This method has the disadvantage that changing the transistor size requires a lot of man-hours because all the magnification parameters that have been set are changed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit diagram editing device that eliminates these drawbacks and can reduce the time required to create connection information.

[0006]

[Means for Solving the Problems] The present invention provides a means for dividing a circuit diagram of a semiconductor integrated circuit into partial circuit blocks, creating and updating circuit diagram information for each divided partial circuit block, and a means for dividing a circuit diagram of a semiconductor integrated circuit into partial circuit blocks. In a circuit diagram editing device equipped with a means for developing a logic level diagram into a logic level diagram, and further developing this logic level diagram into a transistor level diagram and hierarchizing the diagram,
Layout verification connection information is created for each partial circuit based on the circuit diagram information created for each partial circuit block, and the layout verification connection information created for the changed partial circuit is applied to the existing partial circuit. and means for giving the logic level diagram and/or partial circuit block a magnification parameter for the gate width of the transistor included in the transistor level diagram in the lower hierarchy. Features.

[0007]

[Operation] When editing a circuit diagram by dividing it, generate circuit diagram information and connection information for each partial circuit, and merge them to generate circuit diagram information for the entire circuit and connection information for the entire circuit. do. When a circuit diagram is changed, only the circuit diagram information and connection information corresponding to the changed partial circuit are updated, and the circuit diagram information and connection information of the unchanged partial circuit are not updated. Then, connection information corresponding to each partial circuit is merged to generate connection information for the entire circuit after the change.

Furthermore, a magnification parameter is defined for any block in any hierarchy other than the lowest transistor level hierarchy, and is multiplied by the magnification parameter of the block in the hierarchy below it. This is repeated until the lowest layer is reached, the gate width of the transistor is multiplied by the result of multiplication between the parameter layers, and connection information is generated using that value.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing the processing procedure of the first embodiment of the present invention, and shows the processing procedure from circuit diagram input and modification to connection information generation. A user inputs a circuit diagram of a partial circuit, and circuit diagram information is generated. When a partial circuit diagram is changed, the circuit diagram information that has already been created is changed. When circuit diagram information is newly created or changed, connection information corresponding to the partial circuit is created from the circuit diagram information and recorded as the latest information. The individual connection information is then merged to generate connection information for the entire circuit.

That is, in this embodiment, as shown in FIG. 10, the circuit diagram of a semiconductor integrated circuit is divided into partial circuit blocks, and circuit diagram information is created and updated for each divided partial circuit block. means 1, hierarchizing means 2 for developing this partial circuit into a logic level diagram and further developing this logic level diagram into a transistor level diagram and hierarchizing the circuit diagram information created in units of this partial circuit block; Create layout verification connection information for each subcircuit based on the information, and merge the layout verification connection information created for the changed subcircuit with the layout verification connection information created for the existing subcircuit. Means 3 and
The present invention includes a program including a parameter providing means 4 for providing the logic level diagram and/or partial circuit block with a magnification parameter for the gate width of the transistor included in the transistor level diagram in the lower hierarchy.

FIG. 2 shows an example of a state in which circuit diagram information and connection information of a partial circuit created in this embodiment are recorded. 201 shows circuit diagram information of the partial circuit, and 202 shows connection information of the partial circuit.

FIG. 3 shows an example of a state in which a magnification parameter is defined for a macroblock in this embodiment. 301 indicates a magnification parameter. Multiply the value of this parameter by the magnification parameter of the block in the lower layer. This is repeated until the lowest layer is reached, the gate width of the transistor is multiplied by the result of multiplication between the parameter layers, and connection information is generated using that value.

That is, assume that the circuit is hierarchically designed as shown in FIG. L and W in the figure represent the length and width of the transistor, respectively. Here, both the inverter and the NAND gate are L and W in the lower layer transistor circuit.
The value of is defined. In the conventional example, a multiplication factor is given in the form of K = 3 from the logic circuit diagram one level higher than the transistor circuit.
The width of the transistor was determined by W = 20 × K and W = 10 × K, but even when the width is uniformly tripled, K = 3 must be given to all gates, and the number of gates in the partial circuit is When there are many, changes become complicated. If the magnification can be specified from the upper layer partial circuit, then W = 20 x K x S = 120, W = 10 x K x S = 60 for S = 3 and K = 3.
You can specify the transistor size. In this way, by specifying the magnification parameter for a desired layer and a desired block, the transistor size can be easily changed.

FIG. 5 is a flowchart showing the processing procedure of the second embodiment of the present invention, from circuit diagram input and modification to connection information generation. When a user creates a new partial circuit, the user inputs the circuit diagram of the partial circuit, and the generated circuit diagram information is registered as the first version. next,
A first version of connection information is generated from the first version of the circuit diagram information. When a partial circuit is changed, the circuit diagram information that has already been created is changed, and the version number of the changed circuit diagram information is incremented by one and newly registered. (Old versions are also retained.) Next, partial circuit connection information is generated from the latest version of the circuit diagram information of the changed partial circuit, and is registered with the same version number as the circuit diagram information. Users can select any version of connection information for each partial circuit and merge them to create connection information for the entire circuit.

FIG. 6 shows an example of a state in which circuit diagram information and connection information of a partial circuit in this second embodiment are recorded.
501 is the circuit diagram information 1st edition, 502 is the connection information 1st edition,
Reference numeral 503 indicates the second version of the circuit diagram information, and reference numeral 504 indicates the second version of the connection information.

[0016]

[Effects of the Invention] As explained above, when a circuit diagram is edited by dividing it, the present invention regenerates only the connection information of the changed partial circuit and merges it with the existing connection information, thereby editing the entire circuit. Since the connection information can be created and the transistor size can be changed from the upper layer, the time required to create the connection information can be reduced.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the contents of processing in a first embodiment of the present invention.

FIG. 2 is a diagram showing the recording state of information created in the first embodiment of the present invention.

FIG. 3 is a diagram showing the definition state of magnification parameters according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a magnification parameter definition operation according to the first embodiment of the present invention.

FIG. 5 is a flowchart showing the contents of processing in a second embodiment of the present invention.

FIG. 6 is a diagram showing the recording state of information created in the second embodiment of the present invention.

FIG. 7 is a flowchart showing the contents of processing in a conventional example.

FIG. 8 is a diagram showing a definition state of gate size parameters according to a conventional example.

FIG. 9 is a diagram showing a definition state of a magnification parameter according to a conventional example.

FIG. 10 is a diagram showing the configuration of an apparatus that performs the processing shown in FIG. 1.

[Explanation of symbols]

1 Creation and update means 2 Hierarchization means 3. Means of annexation 4 Parameter assignment means 201 Circuit diagram information 202 Connection information 501 Circuit diagram information 1st edition 502 Connection information 1st edition 503 Circuit diagram information 2nd edition 504 Connection information 2nd edition

Claims (1)

[Claims] 1. Means for dividing a circuit diagram of a semiconductor integrated circuit into partial circuit blocks, creating and updating circuit diagram information for each divided partial circuit block, and developing the partial circuit into a logic level diagram, Furthermore, in a circuit diagram editing device equipped with a means for developing and layering this logic level diagram into a transistor level diagram, connection information for layout verification is provided for each partial circuit based on the circuit diagram information created for each partial circuit block. and merging the layout verification connection information created for the changed partial circuit with the layout verification connection information created for the existing partial circuit, and the above logic level diagram and/or the partial circuit. A circuit diagram editing device comprising: means for giving a block a magnification parameter for a gate width of a transistor included in a transistor level diagram in a lower hierarchy thereof.