JPH04367075A - Hardware design system - Google Patents

Abstract

PURPOSE:To provide a hardware design system which realizes the specifications preparation, function design and logical design by one environment such as a word processor used by a person and an editor, simplifies the design by performing the function chart and logical chart expression therein and makes the conversion into the hardware connection description language fast. CONSTITUTION:A document file including the logic information to express logics or a function by the format of a table or an expression is prepared by using a text editor, the logic information is extracted out of the document file prepared here, and converted to a hardware connection description language from the table or the expression. From the table, the effective data are extracted, this is developed at a bit unit, bit arrangement data are prepared at a bit arrangement buffer 131, the bit arrangement data are re-arranged in accordance with the arrangement information of a library 132 prepared for each cell and converted to a hardware connection description language(TDL) 133.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hardware design method in which function or logic circuit connection information can be obtained by inputting hardware specifications.

0002

2. Description of the Related Art In recent years, in hardware design, tools have been developed for inputting the operation and structure of hardware in the form of functional block diagrams, functions, or logical description languages.

As an example, for functional design, a functional design system such as a personal computer or an engineering workstation is used, a functional block diagram is drawn using a graphic editor, and the graphical information is converted into a functional description language. Similarly, for logic design, a functional design system such as a personal computer or engineering workstation was used to create logic diagrams by drawing logic cells using a graphic editor, and the graphical information was converted into a logic connection description language. .

0004

However, according to the above-mentioned conventional example, logic cells have a bit width in a logic diagram, for example, in a data path, logic cells are often configured in units of 1 bit or 4 bits. It was hard to see, and the number of drawings was large, making it difficult to manage. Further, a large amount of time is required to convert drawing information into a hardware connection description language. Furthermore, specification creation, functional design,
Since the applications have different logical designs, there are problems in that it is necessary to learn the operation of each system, and it is necessary to switch between applications in a complicated manner.

The present invention has been made in view of the above-mentioned circumstances, and allows specification creation, functional design, and logical design to be realized in a single environment such as a word processor or editor that one uses, and in which functions can be realized. The purpose of this paper is to provide a hardware design method that simplifies design by expressing diagrams and logical diagrams and speeds up conversion to a hardware connection description language.

[0006]

[Means for Solving the Problems] The present invention creates a document file containing logic information expressing logic or functions in the form of a table or an expression by using a text editor, and creates a document file that is created using a text editor. It is characterized by extracting the above logic information from the table or formula and converting it into a hardware connection description language.

[0007] Also, valid data is extracted from the table, expanded into bits to generate bit array data, and the above bit array data is rearranged according to the array information of the library prepared for each cell. It converts it into a connection description language.

[0008]

[Operation] With the above-described configuration, first, a word processor or an editing program is used to insert the above-mentioned logic information into a text such as a hardware design specification and create a document file. Logic information is extracted from this document file and tables and formulas are converted into a hardware connection description language (logic circuit connection description language or function description language).

[0009] As a result, hardware specifications, functional diagrams, logical development diagrams, etc. can be collected in one file, and
It can be implemented in one environment without having to use a wide variety of applications, contributing to high-speed processing.

0010

Embodiments Hereinafter, embodiments of the present invention will be explained using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is the CP that is the control center of the system.
It is U. A main memory 2 stores an editor program for creating document files and a language conversion program, and is also used as a working area. The CPU 1 reads this program and executes the intended purpose.

A keyboard (KB) 3 is used to input specification information. Specification information includes logic information in addition to normal document information. In this logic information, logic or function is expressed in the form of a table or an expression.

The format of the above table description is shown in FIGS. 2 and 3. Here, FIG. 2 shows a standard description, FIG. 3(a) shows a register and latch description, FIG. 3(b) shows a multiplexer description, and FIG. 3(c) shows a decoder description. Further, the format of the description of the above equation is shown in FIG.

In the figure, the first column shows the control command designation area, and the commands include M, I, O, C, S, E, F.
, Q, QN, E, etc. are prepared. The function of each command will be described later.

[0015] In addition, the symbol a in the figure indicates the module name designation (
b is the command (I command) that specifies the signal name to be input to the module, and c is the command (I command) that specifies the signal name that is output from the module.
This is the area of O command). d is the comment line specification command (C command), e is the area (S
command area).

[0016] f is a unit name writing area, in which the name of a unit having one function is written. For functions, write the functional block name; for logic, write the cell name. g
is a description area for the bit width of the output signal in the table. h is the output signal name, i is the input signal name 1, j is the input signal name 2,
Each is a descriptive area.

k is the area of the table end mark (the end mark of the area to be converted into the hardware connection description language) (the area of the E command). l is an area for a command (F command) for specifying the end of a module (specifying an end for one hierarchy), and m is an area for a table start mark in the abbreviated form of register and latch.

n is an abbreviation for registers and latches, and Q(
This is a command (Q command) area for specifying that only the Q output) side is to be converted into language (if nothing is specified, it will be converted to Q, Q bar). o is an abbreviation for register and latch, and is an area for a command (QN command) for specifying that only the Q bar (Q bar output) side is to be converted into language. p is an area for the table start mark in the multiplexer abbreviation, and q is an area for specifying the multiplexer selection signal name in the multiplexer abbreviation. r is an area for commands (D commands) that are directly written in the logic circuit connection description language, and s is an area for commands (H commands) that are directly written in the functional description language.

Returning to FIG. 1, reference numeral 4 denotes a display device (DISP), which displays document information input using the keyboard 3 and edited using an editor, as well as the results of language conversion using a language conversion program. . Reference numeral 5 denotes an external file device such as a floppy disk device or a hard disk device, which stores intermediate files and various libraries prepared for each cell. Reference numeral 6 denotes a system bus, to which the aforementioned CPU 1, main memory 2, keyboard 3, display device 4, and external file device 5 are commonly connected.

FIGS. 5 to 7 show a program for converting the descriptions expressed in the table format shown in FIGS. 2 and 3 and the description expressed in the formula format shown in FIG. 4 into a hardware connection description language. A partial diagram of a flowchart showing a processing overview,
8 to 11 are partial diagrams of a flowchart showing the procedure for converting the table in FIG. 7 into TDL (Hardware Connection Description Language).

FIGS. 12 and 13 are diagrams for explaining the operation of extracting valid data from a file containing tabular logic information and converting it into a hardware connection description language, using a 4-bit latch as an example. .

In the figure, 121 is a document file (input file) containing logic information expressed in a table format; 122
is a logic diagram expressed by the same logic information, and 123 is an intermediate file (DATAS file) in which valid data extracted from the file 121 is written. Also, 131
is a bit array buffer in which the extracted valid data is expanded in bit units; 132 is a library prepared for each cell; and 133 is a hardware connection description language (TDL) converted from the bit array buffer 131.

The operation of the embodiment of the present invention will be described below with reference to FIGS. 1 to 13. First, the CPU 1 uses the editor program stored in the main memory 2 to open the document file (input file) 121, for example, shown in FIG. . Then, the CPU 1 sequentially reads the input file 121 one record at a time, as described below, and extracts logic information expressed in a table or formula format.

That is, the CPU 1 inputs the input file 121 into one file.
The records are read one by one (step 52 in FIG. 5), and the module name is extracted by first searching for the M command (steps 53 and 54 in FIG. 5). Then, the CPU 1 opens an output file to create a conversion file and writes the module name. (Figure 5 steps 55, 56).

Next, the CPU 1 continues reading records from the input file 121 (step 61 in FIG. 6), and this time extracts the input signal by searching for the I command and writes it to the output file. (Figure 6 steps 62, 63)
.

Next, the CPU 1 continues reading records from the input file 121 (step 64 in FIG. 6), and this time extracts the output signal by searching for the O command and writes it to the output file. (Figure 6 steps 65 and 66)
.

Then, the CPU 1 continues reading records from the input file 121 (step 71 in FIG. 7), and when it detects the B command and extracts the bidirectional signal, writes it to the output file (steps 72 and 73 in FIG. 7). ). Also, if an S command is detected (step 74 in Figure 7)
, the CPU 1 converts the table (logic information written in table format) in the input file 121 into the hardware connection description language (T
DL) (step 75 in FIG. 7). The procedure for this conversion (TDL conversion) processing is shown in Figures 8 to 11.
It is organized into subroutines as shown in the figure below, and the details will be described later.

Furthermore, if the CPU 1 detects a D command while reading a record from the input file 121, it performs direct description processing using an expression (steps 76 and 77 in FIG. 7).
). Similarly, if a C command is detected, the CPU 1 performs comment processing (steps 78 and 79 in FIG. 7). Finally, the CPU 1 searches for the F command and performs writing processing to the output file.

Now, the conversion process (TDL conversion process) into a hardware connection description language using a subroutine will be explained with reference to FIGS. 8 to 11. First, the CPU
1 is the intermediate file (DATAS file) 1 that stores valid data in the table until the end mark (E command) is detected.
23, and takes it into a certain buffer (#1) (steps 81 and 82 in FIG. 8).

Then, the CPU 1 stores the output signal of the buffer (#1) in the bit array buffer 131 (step 83 in FIG. 8), and bit-expands the signal with a bit width and writes it in the bit array buffer 131 (step 83 in FIG. 8). 84)
. The CPU 1 loops this process for the number of output signals of the library 132 prepared for each cell.

Similarly, the CPU 1 stores the input signal of the buffer (#1) in the bit array buffer 131 (step 91 in FIG. 9), and bit-wide signals are expanded and written into the bit array buffer 131 (FIG. 9). Step 92)
. The CPU 1 loops this process for the number of input signals of the library 132 prepared for each cell.

Finally, the CPU 1 arranges the data in the bit array buffer 131 according to the array information in the library 132, creates a hardware connection description language (TDL) 133, and writes it into an output file (step 93 in FIG. 9). When the table end mark (E command) is detected (step S94 in FIG. 9), the series of TDL conversion processing ends.

[0033]

As described above, according to the present invention, it is possible to express functional diagrams and logic diagrams that are easy to see, and the conversion into a hardware connection description language is accelerated. In addition, you can accumulate hardware internal specifications, functional diagrams (block diagrams), logical development information, etc. in one document file, and you can create specifications, function designs, and logical designs using your own word processor. Or it can be realized in one environment such as an editor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a system to which the present invention is applied.

FIG. 2 is a diagram showing an example of logic information expressed in a “table” used in the embodiment.

FIG. 3 is a diagram showing an example of logic information expressed in a “table” used in the embodiment.

FIG. 4 is a diagram showing an example of logic information expressed as an "expression" used in the embodiment.

FIG. 5 is a partial diagram of a flowchart showing an outline of processing of a program for converting the logic information into a hardware connection description language.

FIG. 6 is another partial diagram of the same flowchart.

FIG. 7 is a diagram showing the remaining parts of the same flowchart.

8 is a partial diagram showing a specific processing procedure of a subroutine for realizing the conversion process (step 75) to the hardware connection description language shown in FIG. 7; FIG.

FIG. 9 is another partial diagram showing the specific processing procedure of the same subroutine.

FIG. 10 is yet another partial diagram showing the specific processing procedure of the same subroutine.

FIG. 11 is a remaining partial diagram showing the specific processing procedure of the subroutine.

FIG. 12 is a diagram showing part of an operation explanatory diagram for explaining the operation when valid data is extracted from a file containing tabular logic information and converted into a hardware connection description language using a 4-bit latch as an example. .

FIG. 13 is a diagram showing the rest of the same operation explanatory diagram.

[Explanation of symbols]

1...CPU, 2...Main memory, 3...Keyboard (KB), 4
...Display (DISP), 5...External file device,
6... System bus, 121... Input file (document file), 123... Intermediate file, 131... Bit array buffer, 133... TDL (hardware connection description language).

Claims (2)

[Claims] [Claim 1] A document file containing logic information expressing logic or functions in the form of a table or an expression is created using a text editor, and the above logic information is extracted from the created document file. A hardware design method characterized by extracting and converting tables or formulas into a hardware connection description language. Claim 2: Extract valid data from the table, expand it bit by bit to generate bit array data, rearrange the bit array data according to array information of a library prepared for each cell, and then use the hardware. 2. The hardware design method according to claim 1, wherein the hardware design method is converted into a connection description language.