JPH04366889A - Plasma display device - Google Patents

Plasma display device

Info

Publication number
JPH04366889A
JPH04366889A JP3140556A JP14055691A JPH04366889A JP H04366889 A JPH04366889 A JP H04366889A JP 3140556 A JP3140556 A JP 3140556A JP 14055691 A JP14055691 A JP 14055691A JP H04366889 A JPH04366889 A JP H04366889A
Authority
JP
Japan
Prior art keywords
circuit
full
illumination
plasma display
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3140556A
Other languages
Japanese (ja)
Inventor
Masatoshi Shimizu
正敏 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3140556A priority Critical patent/JPH04366889A/en
Publication of JPH04366889A publication Critical patent/JPH04366889A/en
Pending legal-status Critical Current

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

PURPOSE:To instantaneously end full-illumination operation which prevents initial discharge delay by generating a signal which makes all electrodes of a plasma display panel illumination state simultaneously power-ON operation and detecting all the electrodes being in an illumination state. CONSTITUTION:A row electrode driving circuit 2 and a column electrode driving circuit 3 are connected to the electrodes of the plasma display panel 1 and a control circuit 4 controls display information and scan information required for them. When the display information is held in the illumination state for a time more than one screen scan, the plasma display panel 1 enters the full- illumination state. A full-illumination circuit 5 detects the power-ON operation and switches all the display information to the illumination state. A full- illumination detecting circuit 6 detects the full-illumination state and resets the signal of the full-illumination circuit 5. Thus, the full-illumination operation which prevents the initial discharge delay ends instantaneously regardless of whether the turn-on time of the plasma display panel 1 is short or long.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、ACリフレッシュ形プ
ラズマディスプレイ装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC refresh type plasma display device.

【0002】0002

【従来の技術】従来、この種のACリフレッシュ形プラ
ズマディスプレイパネルの表示装置は、図3に示すよう
に、プラズマディスプレイパネル1とその電極を駆動す
る行駆動回路2,列駆動回路3に必要な信号を作り出す
制御回路4及び全点灯回路5を有している。制御回路4
は行駆動回路2と列駆動回路3に必要な走査情報や表示
情報を司どっている。制御回路4からの信号を行駆動回
路2と列駆動回路3でプラズマディスプレイパネル1に
必要な駆動電圧に変え所望の表示を得ている。プラズマ
ディスプレイパネルは電源投入時に点灯遅れが発生する
。それを防止するため電源投入時に一定時間、全電極を
点灯状態にするための全点灯回路5が設けられている。
2. Description of the Related Art Conventionally, as shown in FIG. 3, this type of AC refresh type plasma display panel display device has a plasma display panel 1 and a row drive circuit 2 and a column drive circuit 3 that drive the electrodes thereof. It has a control circuit 4 that generates a signal and a full lighting circuit 5. Control circuit 4
controls scanning information and display information necessary for the row drive circuit 2 and column drive circuit 3. The row drive circuit 2 and column drive circuit 3 convert signals from the control circuit 4 into drive voltages necessary for the plasma display panel 1 to obtain a desired display. Plasma display panels experience a lighting delay when the power is turned on. To prevent this, an all-lighting circuit 5 is provided to keep all electrodes lit for a certain period of time when the power is turned on.

【0003】0003

【発明が解決しようとする課題】この従来のプラズマデ
ィスプレイパネルの表示装置は、初期放電遅れを防止す
るために一定時間全電極を点灯させる全点灯回路5を有
しているが、プラズマディスプレイパネルの放電遅れ時
間のバラツキは大きい。この放電遅れ時間をターンオン
タイムと呼んでいるが、このバラツキを吸収するだけの
時間、一般に5秒から10秒程度全点灯するように全点
灯回路5は設定されている。ターンオンタイムの早いも
のは、電源投入と同時に点灯し、設定された時間だけ点
灯しつづけ、ターンオンタイムの遅いものは設定された
時間の終りごろに点灯するというような問題点があった
。又設定された時間内に点灯開始しなかった場合、全店
点灯路が全く効かないという問題点もあった。
[Problems to be Solved by the Invention] This conventional plasma display panel display device has an all-lighting circuit 5 that lights up all electrodes for a certain period of time in order to prevent an initial discharge delay. There is a large variation in discharge delay time. This discharge delay time is called turn-on time, and the full lighting circuit 5 is set so that the lights are fully lit for a time that is sufficient to absorb this variation, generally about 5 to 10 seconds. Lights with a fast turn-on time turn on at the same time as the power is turned on and remain lit for a set period of time, while lights with a slow turn-on time turn on at the end of the set time. There was also the problem that if the lights did not start within the set time, the all-store lighting path would not work at all.

【0004】0004

【課題を解決するための手段】本発明のプラズマディス
プレイパネルの表示装置は、電源投入と同時に全電極を
全点灯させる回路に加え、全点灯したかどうかの検出回
路を備え、プラズマディスプレイパネルが全点灯したら
全点灯検出回路が働き全点灯回路をオフすることにより
、ターンオンタイムの早いものも遅いものも一定の短い
時間だけ全点灯することになる。
[Means for Solving the Problems] The plasma display panel display device of the present invention includes a circuit that lights up all the electrodes at the same time as the power is turned on, and a detection circuit that detects whether all the electrodes are lit. When the lights turn on, the full lighting detection circuit operates and turns off the full lighting circuit, so that both early and slow turn-on times are fully lit for a fixed short period of time.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明する
。図1は本発明の一実施例のブロックダイアグラムであ
る。プラズマディスプレイパネル1の電極には、それぞ
れ行電極駆動回路2及び列電極駆動回路3が接続されて
いる。制御回路4は行電極駆動回路2と列電極駆動回路
3に必要な表示情報や走査情報を司どっている。表示情
報を一画面走査する時間以上点灯状態に保つとプラズマ
ディスプレイパネル1は全点灯状態となる。全点灯回路
5は電源投入を検出し、前記表示情報を全て点灯状態に
切替える回路である。全点灯検出回路6は全点灯状態を
検出し、全点灯回路5の信号を解除する働きをする。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. A row electrode drive circuit 2 and a column electrode drive circuit 3 are connected to the electrodes of the plasma display panel 1, respectively. The control circuit 4 controls display information and scanning information necessary for the row electrode drive circuit 2 and column electrode drive circuit 3. If the plasma display panel 1 is kept lit for longer than the time required to scan one screen of display information, the plasma display panel 1 becomes fully lit. The all-lighting circuit 5 is a circuit that detects power-on and switches all the display information to a lit state. The full lighting detection circuit 6 detects the full lighting state and functions to release the signal from the full lighting circuit 5.

【0006】図2は本実施例の全点灯回路5及び点灯検
出回路6の詳細図である。図において、Dタイプフリッ
プフロップ51は入力Dがロジック用電源Vccに接続
されていて、クロック入力端子CKが抵抗R1とコンデ
ンサC1に接続されている。この状態でロジック用電源
を投入するとクロック端子CKは抵抗R1とコンデンサ
C1の容量で決まる時定数分だけ遅れて立上がる。Dフ
リップフロップ51はクロック端子CKが立上る時の入
力端子Dの情報を出力Qに出力する。この場合出力Qは
ロジック“H”となりオアゲート52の入力54に出力
される。オアゲート52の一方の入力53は制御回路4
からデーターの入力を受けてオアゲート52を通して、
列電極駆動回路3に出力されている。入力54が“H”
となるとオアゲート52の出力55も“H”となり、全
点灯状態になる。
FIG. 2 is a detailed diagram of the entire lighting circuit 5 and lighting detection circuit 6 of this embodiment. In the figure, a D type flip-flop 51 has an input D connected to a logic power supply Vcc, and a clock input terminal CK connected to a resistor R1 and a capacitor C1. When the logic power supply is turned on in this state, the clock terminal CK rises with a delay of a time constant determined by the capacitance of the resistor R1 and the capacitor C1. The D flip-flop 51 outputs information at the input terminal D to the output Q when the clock terminal CK rises. In this case, the output Q becomes logic "H" and is output to the input 54 of the OR gate 52. One input 53 of the OR gate 52 is connected to the control circuit 4
Receives data input from the or gate 52,
It is output to the column electrode drive circuit 3. Input 54 is “H”
When this happens, the output 55 of the OR gate 52 also becomes "H", resulting in a fully lit state.

【0007】表示用電源のリターン側には抵抗R2が入
れられている。この抵抗R2の所から抵抗R5を通して
オペアンプ61の入力+に加えられる。一方オペアンプ
61の入力−は抵抗R3と可変抵抗R4の中点に入れら
れている。オペアンプ61は入力+側が入力−側より電
圧が高くなった時、抵抗R6を通してインバーター62
に電圧を出力する。ダイオードD1,D2は抵抗R6を
通してインバーター62に入力される電圧がロジック電
源以上にならないように入れられている。インバーター
62は入力信号を反転するもので、抵抗R6を通して正
の電圧が入力されると出力にロジック“L”となる電圧
を出力し、Dフリップフロップ51のリセット端子Rを
“L”とし、出力Qを“L”にして、全点灯状態を解除
できる。つまり全点灯時に抵抗R2を流れる電流により
抵抗R2に発生する電圧が抵抗R3と抵抗R4で分割さ
れる電圧より上になるように抵抗R3,R4を調整する
。コンデンサC2は抵抗R2に発生する電圧が平均化す
るように入れられている。又抵抗R5と時定数を形成し
ており、全点灯になってから全点灯を解除するまでのタ
イムラグを作る役目もおっている。
A resistor R2 is connected to the return side of the display power supply. The signal is applied from this resistor R2 to the input + of the operational amplifier 61 through the resistor R5. On the other hand, the input - of the operational amplifier 61 is placed at the midpoint between the resistor R3 and the variable resistor R4. When the voltage on the input + side becomes higher than the input - side, the operational amplifier 61 connects the inverter 62 through the resistor R6.
Outputs voltage to. The diodes D1 and D2 are inserted so that the voltage input to the inverter 62 through the resistor R6 does not exceed the logic power supply. The inverter 62 inverts the input signal, and when a positive voltage is input through the resistor R6, it outputs a logic "L" voltage, sets the reset terminal R of the D flip-flop 51 to "L", and outputs The full lighting state can be canceled by setting Q to "L". In other words, the resistors R3 and R4 are adjusted so that the voltage generated across the resistor R2 by the current flowing through the resistor R2 during full lighting is higher than the voltage divided by the resistors R3 and R4. Capacitor C2 is inserted so that the voltage generated across resistor R2 is averaged. It also forms a time constant with the resistor R5, and has the role of creating a time lag from when all the lights are turned on until when all the lights are turned off.

【0008】[0008]

【発明の効果】以上説明したように本発明は、電源投入
と同時に全点灯回路を働かせ、全点灯になったことを検
出する検出回路を設け、全点灯状態になったら全点灯回
路を停止させることにより、初期放電遅れを防止する全
点灯動作が、プラズマディスプレイパネルのターンオン
タイムの早い遅いにかかわらず瞬時に終了するという効
果がある。又必ず全点灯が入るという効果もある。
[Effects of the Invention] As explained above, the present invention activates the full lighting circuit at the same time as the power is turned on, provides a detection circuit to detect when the full lighting is reached, and stops the full lighting circuit when the full lighting is reached. This has the effect that the entire lighting operation for preventing initial discharge delay is completed instantly regardless of whether the turn-on time of the plasma display panel is early or late. It also has the effect of ensuring that all lights are turned on.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例のブロックダイアグラムであ
る。
FIG. 1 is a block diagram of one embodiment of the invention.

【図2】図1に示した全点灯回路及び全点灯検出回路の
詳細図である。
FIG. 2 is a detailed diagram of the all-on circuit and all-on detection circuit shown in FIG. 1;

【図3】従来のプラズマディスプレイ装置のブロックダ
イアグラムである。
FIG. 3 is a block diagram of a conventional plasma display device.

【符号の説明】[Explanation of symbols]

1    プラズマディスプレイパネル2    行電
極駆動回路 3    列電極駆動回路 4    制御回路 5    全点灯回路 6    全点灯検出回路 51    Dフリップフロップ 52    オアゲート 53〜55    入出力線 61    オペアンプ 62    インバータ R1〜R6    抵抗 C1,C2    コンデンサ D1,D2    ダイオード Vcc    ロジック用電源
1 Plasma display panel 2 Row electrode drive circuit 3 Column electrode drive circuit 4 Control circuit 5 Full lighting circuit 6 Full lighting detection circuit 51 D flip-flop 52 OR gates 53-55 Input/output line 61 Operational amplifier 62 Inverter R1-R6 Resistor C1, C2 Capacitor D1, D2 Diode Vcc Logic power supply

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  電極が誘電体で被覆されているプラズ
マディスプレイパネルとその駆動回路より構成される表
示装置において、電源オンと同時にプラズマディスプレ
イパネルの全電極が点灯状態になる信号を発生する回路
と、全電極が点灯状態になったことを検出し、前記信号
をオフする回路とを有することを特徴とするプラズマデ
ィスプレイ装置。
1. A display device comprising a plasma display panel whose electrodes are covered with a dielectric material and its drive circuit, in which a circuit generates a signal that turns on all electrodes of the plasma display panel at the same time as power is turned on. . A plasma display device comprising: a circuit that detects that all electrodes are turned on and turns off the signal.
JP3140556A 1991-06-13 1991-06-13 Plasma display device Pending JPH04366889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3140556A JPH04366889A (en) 1991-06-13 1991-06-13 Plasma display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3140556A JPH04366889A (en) 1991-06-13 1991-06-13 Plasma display device

Publications (1)

Publication Number Publication Date
JPH04366889A true JPH04366889A (en) 1992-12-18

Family

ID=15271431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3140556A Pending JPH04366889A (en) 1991-06-13 1991-06-13 Plasma display device

Country Status (1)

Country Link
JP (1) JPH04366889A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100512918B1 (en) * 2001-12-03 2005-09-07 파이오니아 가부시키가이샤 Driving device for plasma display panel
KR100679440B1 (en) * 2001-10-26 2007-02-07 파이오니아 가부시키가이샤 Driving method of AC-type plasma display panel

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100679440B1 (en) * 2001-10-26 2007-02-07 파이오니아 가부시키가이샤 Driving method of AC-type plasma display panel
KR100512918B1 (en) * 2001-12-03 2005-09-07 파이오니아 가부시키가이샤 Driving device for plasma display panel
KR100713789B1 (en) * 2001-12-03 2007-05-04 파이오니아 가부시키가이샤 Driving device for plasma display panel

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