JPH04364528A - Extraction value calculating circuit - Google Patents

Abstract

PURPOSE:To calculate an accurate extraction value at a high speed without increasing the hardware quantity. CONSTITUTION:The extracted value generating circuit 10 is added to a conventional digital signal processor which has a multiplier 20, an arithmetic logical unit, etc. Then a value Y to be extracted is stored in a 1st register 1. The output of a 2nd register 3 stored with an extraction value X is squared by a multiplier 20 and a subtracter 21 calculates the difference between the multiplication result and the output of the register 1. The circuit 10 performs addition and subtraction between the outputs of a right shift register 2 for the storage of an intermediate value R and the 2nd register 3 by exclusive logic according to the plus/minus information of the subtracter 21 and updates the contents of the register 3 according to the addition and subtraction result. The operation is repeated n times so as to find an n-bit solution and then the value in the register 3 is the extraction value X for the extracted value Y stored in the register 1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applied to a digital signal processor (hereinafter referred to as DSP) that performs high-speed calculations under program control using an arithmetic logic unit (hereinafter referred to as ALU) and a multiplier. It is something that
The present invention relates to a square root value calculation circuit that calculates a square root value (root value).

0002

2. Description of the Related Art Conventionally, there have been techniques related to this type of DSP described in, for example, Japanese Patent Application Laid-Open Nos. 2-125331 and 2-137023.

[0003] In recent years, digital signal processing technology using DSP has been widely used in the field of signal processing. DSP
It is possible to freely change its operation using software through program control, and because of this degree of freedom, it is being applied to a variety of applications.

[0004] Digital signal processing technology treats signals as discrete numerical values, and generally obtains results through four arithmetic operations. However, as digital signal processing technology itself becomes more complex, processes other than the four arithmetic operations are increasingly being used. In terms of performance, conventional DSPs only had three types of arithmetic circuits for addition, subtraction, and multiplication, but recently they have added a divider and have built-in four types of arithmetic circuits, including addition, subtraction, and multiplication. DSPs that do this are also emerging.

In digital signal processing technology, a square root operation (root operation) is the next operation after the four arithmetic operations.
There is. The technology in the above document uses Newton-Raphs, which approximates the function value using the equation of the tangent to the function.
The square root calculation is realized by software using a convergence method based on the on method.

[0006]

[Problems to be Solved by the Invention] However, using a fixed-point arithmetic DSP, Newton-Raphs
When the square root value is calculated using the convergence method based on the ON method, the following problem occurs. (a) Newton-Raphso using division
Using the n method requires one division for one convergence equation. Since division requires more time for calculation than addition, subtraction, and multiplication, the calculation time for one convergence expression becomes longer, and as a result, more calculation time is required to obtain the square root value.

(b) Newton without division
- When the Raphson method is used, a reciprocal number is used for the intermediate value, so a loss of precision occurs, and the answer may not converge to the correct answer. This is especially noticeable in fixed-point arithmetic.

The present invention solves the problem of the prior art, which is that it is difficult to calculate the square root value quickly and accurately without increasing the circuit scale (hardware amount) in a fixed-point DSP. The present invention provides a square root value calculation circuit.

[0009]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the first invention provides a square root value calculation circuit using a DSP that performs fixed-point arithmetic, and a first invention that stores a square root value.
a right shift register that operates to right shift based on a clock signal and outputs a value of a power of 2; and a right shift register that operates based on the clock signal so that the output of the right shift register is 2i (where i is an integer). , the 2i digit is logic “1” and all digits below the 2i-1 digit are logic “0”
and a second register for storing a square root value that outputs a value that becomes ``.Furthermore, a multiplier that squares the output of the second register, and an output of the first register and the multiplier. and a subtracter that subtracts and outputs the positive/negative information of the subtraction result, performs addition/subtraction by performing exclusive logic of the outputs of the right shift register and the second register based on the positive/negative information, and uses the result of the addition/subtraction to A square root value generation circuit for updating the contents of the second register is provided.

[0010] The second invention is a square root value calculation circuit using a DSP that performs fixed-point arithmetic operations in the same manner as the first invention. a right shift register that outputs a value of a power of 2; a clock control circuit that controls input of the clock signal based on positive/negative information; When the output of is 2i (where i is an integer), the second square root value storage unit outputs a value in which the 2i digit is logic “1” and all digits below the 2i-1 digit are logic “0”. It is equipped with a register.

[0011]Furthermore, there is provided a logic circuit that performs logical addition of the outputs of the right shift register and the second register, and updates the contents of the second register with the result of the addition, and a logic circuit that squares the output of the logic circuit. and a subtracter that subtracts the outputs of the first register and the multiplier and outputs the positive/negative information of the subtraction result to the clock control circuit.

0012

[Operation] According to the first invention, since the square root value calculation circuit is configured as described above, the contents of the second register are squared by the multiplier, and the multiplication result and the contents of the first register are Subtracted by the subtractor. Based on the positive/negative information from the subtracter, the square root value generation circuit performs addition/subtraction by performing exclusive logic on the contents of the right shift register and the second register, and updates the contents of the second register with the result of the addition/subtraction. Then, if the above operation is executed n times to obtain an n-bit solution, the value existing in the second register becomes the square root value to be sought.

According to the second invention, the contents of the right shift register are squared by a multiplier via a logic circuit, and the multiplication result is subtracted from the contents of the first register by a subtracter. Based on the positive/negative information of this subtracter, the clock control circuit controls the input of the clock signal to the second register, and the logic circuit adds the contents of the second register and the contents of the right shift register. Update the contents of the second register with the result. Then, in order to obtain an n-bit solution, if the above operation is executed n times, the value existing in the second register becomes the square root value to be sought. Therefore, the above problem can be solved.

[0014]

[Embodiment] First, the principle of an embodiment of the present invention will be explained.

Consider the problem of finding the square root value X of the square root value (positive number) Y. At this time, the relationship between X and Y is X2 ≦Y<(X+1)2
...It is expressed as (1).

It is now assumed that Y is a finite-precision positive value and is expressed as a binary number of 2×n bits. Y≦2 2×n −1
...(2) The range of X that satisfies formula (1) is X<2n -1
...It is expressed as (3).

From equations (1), (2), and (3), X can be obtained in n hours by searching for 2n-1 candidates for X using the bisection method.

First Embodiment FIG. 1 is a block diagram of a square root value calculation circuit showing a first embodiment of the present invention using the above-described principle.

This square root value calculation circuit includes a multiplier and an ALU.
A first register 1 that stores an unsquared root value Y, a right shift register 2 and a second register whose output value changes in synchronization with, for example, the rising edge of a clock signal CK. It is equipped with a register 3. The right shift register 2 is a register that performs a right shift operation in synchronization with the rise of the clock signal CK and stores an intermediate value R of a power of 2. The second register 3 performs a storage operation in synchronization with the rise of the clock signal CK, and when the intermediate value R of the right shift register 2 is 2i (where i is an integer), the 2i digit is always "1". This is a register for storing the square root value X in which all digits below 2i-1 digits are "0".

Right shift register 2 and second register 3
On the output side of the square root value generating circuit 10, input terminals 10a,
10b is connected, the output terminal 10d of the square root value generation circuit 10 is connected to the input side of the second register 3, and the output side of the second register 3 is connected to the two input sides of the multiplier 20. has been done. The square root value generation circuit 10 includes, in addition to input terminals 10a and 10b and an output terminal 10d, a flag input terminal 10 that inputs, for example, a negative flag F as positive/negative information.
c, and has a function of calculating the following equations (A1) and (A2) and updating the contents of the second register 3 based on the calculation results.

[0021]

[Math 1]

The multiplier 20 has the function of squaring the output of the second register 3, and its output side and the output side of the first register 1 are connected to the input side of the subtracter 21. . The subtracter 21 has a function of subtracting two input values and outputting positive/negative information of the subtraction result, for example, a negative flag F, to the flag input terminal 10c of the square root value generation circuit 10, and is constituted by an ALU.

FIG. 2 is a circuit diagram showing an example of the configuration of the square root value generating circuit of FIG. 1. In FIG.

This square root value generation circuit 10 has an input terminal 10
A group of AND gates 111 to 11n which take the AND of the two inputs from the flag input terminal 10c and the OR which takes the output of the AND gate 111 and a fixed value "0".
AND gate 121 and input from input terminal 10a
OR gate groups 122 to 12n which take the logical sum of the outputs of the gates 112 to 11n, and exclusive OR which takes the logical sum of the input from the input terminal 10b and the outputs of the OR gate group 121 to 12n and outputs to the output terminal 10d. Logical sum (E
XOR) gate groups 131 to 13n. EXOR gate 131 is the most significant bit (MSB)
), EXOR gate 13n is the least significant bit (LSB)
It is.

FIG. 3 is a flowchart showing a basic algorithm for determining the square root value X of the unexpanded root value Y in FIG. As shown in this figure, in order to obtain an n-bit solution, it is necessary to perform the processing of steps 110 to 140 n times. The implementation method of this basic algorithm utilizes the characteristics of the values of the right shift register 2 and the second register 3. That is, the intermediate value R of the right shift register 2 is always a power of 2, and the value X of the second register 3 is such that the intermediate value R is 2.
i, the 2i digit is always “1” and 2i−
Utilizing the feature that all digits below the first digit are "0", the EXOR gate group 13 of the square root value generation circuit 10 performs the addition and subtraction of the equations (A1) and (A2), that is, the following equation (4).
1 to 13n. X-R+R'=
X EXOR R EXOR R'...
(4) Next, the calculation operation of the square root value will be explained with reference to FIG.

However, it is assumed that the output values of the right shift register 2 and the second register 3 change at the rising edge of the clock signal CK.

At step 100 in FIG. 3, the first and second registers 1 and 3 and the right shift register 2 are initialized. The first register 1 stores the opened mean value Y. Both the second register 3 and the right shift register 2 store a value of "1" only in the MSB. here,
The right shift register 2 is set to “1” according to the square root value calculation operation.
The position of is shifted to the right, and when all bits become "0", the square root value calculation operation ends. The second register 3 has a function of determining the square root value from the MSB side according to the square root value calculation operation.

At time t1, the next operation is executed during the time from the rising edge of clock signal CK to the next rising edge at time t2.

When the intermediate value R of the right shift register 2 is not 0 in step 110, in step 120, the second
The multiplier 20 calculates the square value X2 of the value X of the register 3. Furthermore, in step 120, the difference (Y
-X2) is calculated by the subtracter 21, and the negative flag F is determined and outputted to the flag input terminal 10c of the square root value generation circuit 10.

In step 130, the square root value generating circuit 10 uses the determined negative flag F to calculate Y−X2.
>0, calculate formula (A1) (step 131
), when Y-X2 < 0, calculate formula (A2) (
Step 132). This decision logic is (A1), (A2
) Based on the formula, MBS bit of output = Xmsb EXOR (R
msb AND F)) Other i-th bit output = Xi EXOR (Ri+1
OR (Ri AND F)). However, Xi is the i-th bit of the second register 3, Ri is the i-th bit of the right shift register 2, and F is a negative flag ("1" when positive logic = negative).

At the next rising edge of the clock signal CK at time t2, in step 140, the intermediate value R of the right shift register 2 is shifted to the right by one bit, and the output of the square root value generating circuit 10 is shifted to the second is stored in register 3.

When the operations of steps 110 to 140 are executed n times and n clock signals CK are input, the intermediate value R becomes 0 in step 110, and the value existing in the second register 3 X becomes the square root value of the opened root value Y (
Step 121).

This first embodiment has the following advantages.

(a) It becomes possible to obtain the square root value X without performing a jump operation under program control. Furthermore, the required calculation time is the number of bits n of the square root value
This is the same calculation time required to find the reciprocal using a general divider. Moreover, since the output of the second register 3 is multiplied by the multiplier 20 and subtracted by the subtracter 21, the throughput between them is fast and the processing speed is fast. Therefore, the square root value X can be calculated quickly and accurately using a fixed-point DSP.

(b) Comparing the conventional DSP and the DSP to which the square root value generating circuit 10 of this embodiment is added, the amount of hardware increased by the addition of the square root value generating circuit 10 is as shown in FIG. per bit, AND gate, OR
There is only one gate and one EXOR gate, and the amount of elements is extremely small. Furthermore, since these gates have a regular arrangement structure, it is easy to implement an LSI circuit, and an increase in the amount of hardware can be prevented.

Second Embodiment FIG. 4 is a block diagram of a square root value calculation circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 are given the same reference numerals. There is.

In this square root value calculation circuit, a clock control circuit 30 and a logic circuit 40 are provided in place of the square root value generation circuit 10 of FIG.

The clock control circuit 30 uses the second clock signal based on the positive/negative information output from the subtracter 21, for example, the positive flag G.
This circuit controls the input of the clock signal CK to the register 3, and is composed of, for example, an AND gate 31.

The right shift register 2 connected to the input side of the AND gate 31 is a register for storing an intermediate value R whose output value changes in synchronization with, for example, the rising edge of the clock signal CK, and the initial value is MSB. According to the square root value calculation operation, the position of the "1" is shifted to the right, and when all bits become "0", the square root value calculation operation ends. The output side of this right shift register 3 is connected to an input terminal 40a of a logic circuit 40. Further, the second register 3 connected to the output side of the AND gate 31 is a register for storing the square root value X whose output value changes in synchronization with, for example, the rising edge of the clock signal CK, and performs the square root value calculation operation. According to this, the square root value is determined from the MSB side. The output side of this second register 3 is connected to an input terminal 40b of a logic circuit 40.

The logic circuit 40 has an output terminal 40c connected to the input side of the multiplier 20 and the second register 3, and
It has a function of adding the inputs of the two input terminals 40a and 40b and updating the contents of the second register 3 based on the addition result, and is composed of a group of OR gates. Multiplier 20
is a circuit that squares the output of the logic circuit 40 and outputs the multiplication result to the subtracter 21. The subtracter 21 is a circuit that subtracts the outputs of the first register 1 and the multiplier 20 and outputs positive/negative information of the subtraction result, for example, a positive flag G, to the AND gate 31.

FIG. 5 is a circuit diagram showing an example of the configuration of logic circuit 40 in FIG. 4. Referring to FIG.

This logic circuit 40 has two input terminals 40
OR gate group 411 connected to a and 40b, respectively
~41n, and their output side is the output terminal 40
connected to c.

FIG. 6 is a flowchart showing a basic algorithm for determining the square root value X of the unexpanded root value Y in FIG. As shown in this figure, in the basic algorithm of this second embodiment, in order to obtain an n-bit solution, the loop is
need to be executed once. In the implementation method of this basic algorithm, as in the first embodiment, the characteristics of the values of the right shift register 2 and the second register 3, that is, the intermediate value R of the register 2 is always a power of 2; When the intermediate value R is 2i, the value X of is calculated by the following formula ( The addition of A3) is realized by the logic circuit 40. B←X+R
(A3) Next, the operation of each step in FIG. 6 will be explained.

Initialization is performed in step 200, and the second register 3 stores all "0" values, and the right shift register 2 stores only the MSB "1" values. It is assumed that the first register 1 stores an opened mean value Y.

On the condition that the intermediate value R of the right shift register 2 is not 0 in step 210, in step 220,
The logic circuit 40 adds the intermediate value R of the right shift register 2 and the value X of the second register 3 according to equation (A3). Let this added value be B. In step 230, the added value B in step 220 is squared, and the subtracter 21 calculates the difference (Y-B2) between the squared value B2 and the squared root value Y of the first register 1, and the positive flag is Confirm G.

In the clock control circuit 30, step 23
Using the positive flag G determined as 0, the input of the clock signal CK to the second register 3 is controlled in step 240. That is, when the positive flag G is positive (“1”)
In step 240, the AND gate 31 is opened, the clock signal CK is supplied to the second register 3, and the output of the logic circuit 40 is taken into the second register 3. On the other hand, when the positive flag G is negative (“0”), the AN
The D-gate 31 is closed and the clock signal CK is not supplied to the second register 3, which retains the value of the previous state and the process proceeds to step 250.

In step 250, right shift register 2
Shift the intermediate value R of 1 bit to the right, step 21
Return to 0. Then, n clock signals CK are input,
When the intermediate value R of the right shift register 2 becomes 0 in step 210, the square root value calculation process ends in step 221, and the value existing in the second register 3 becomes the square root value X to be sought.

This second embodiment has the following advantages.

(A) As in the first embodiment, it is possible to obtain the square root value without performing a jump operation by program control, and the required calculation time is reduced by the bits of the square root value This is the same calculation time required to find the reciprocal with a general divider. Therefore, even in a fixed-point DSP, an accurate square root value X can be obtained quickly.

(B) The amount of hardware increases compared to the conventional D
Compared to the SP, there is only a clock control circuit 30 and a logic circuit 40, the amount of elements is extremely small, and it is easy to implement LSI circuits. Further, the circuit configuration of the clock control circuit 30 and the logic circuit 40 is the same as that of the square root value generation circuit 1 of the first embodiment.
Since this embodiment is simpler than 0, the additional circuit configuration is simpler than that of the first embodiment.

[0051] Note that the present invention is not limited to the above embodiments,
Various modifications are possible. Examples of such modifications include the following.

(i) In FIG. 1, the negative flag F of the subtracter 21 is used to obtain the exclusive OR in the square root value generating circuit 10, but the circuit configuration of the square root value generating circuit 10 shown in FIG. It is also possible to process in the square root value generation circuit 10 using a positive flag of the positive/negative information outputted from the subtracter 21 by configuring it with a logical NOR gate or the like.

(ii) In FIG. 4, of the positive and negative information output from the subtracter 21, the positive flag G is set to the clock control circuit 3.
0 to control the input of the clock signal CK, but by configuring the clock control circuit 30 with another gate circuit, the input of the clock signal CK to the second register 3 can be controlled using the negative flag. It may also be controlled. Further, although the logic circuit 40 is configured with an OR gate, if the outputs of the right shift register 2 and the second register 3 are reverse phase signals, the logic circuit 40 can also be configured with gate circuits corresponding to the outputs. It is.

(iii) In FIGS. 1 and 4, the subtracter 21 is constructed from an ALU, but it may also be constructed from a dedicated subtraction circuit.

[0055]

As explained in detail above, according to the first invention, the content of the second register is updated in the square root value generation circuit based on the positive/negative information of the subtracter, that is, the square root value candidate is Since the calculation is performed, an accurate square root value can be obtained quickly even in a fixed-point DSP. Moreover, by using conventional ALUs, multipliers, etc., a square root value calculation circuit can be configured by simply adding a square root value generation circuit, and an accurate square root value calculation circuit can be configured while suppressing an increase in the amount of hardware. realizable.

According to the second invention, the clock control circuit controls the input of the clock signal to the second register based on the positive/negative information of the subtracter, and based on the output of the logic circuit,
Since the contents of the second register are updated, that is, candidates for the square root value are calculated, the square root value can be calculated quickly and accurately even in a fixed-point DSP, similar to the first invention. . Furthermore, by using a DSP having a conventional ALU, multiplier, etc., an accurate square root value calculation circuit can be realized by simply adding a clock control circuit and a logic circuit, while suppressing an increase in the amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of a square root value calculation circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the square root value generation circuit of FIG. 1;

FIG. 3 is a flowchart of the basic algorithm in FIG. 1;

FIG. 4 is a configuration block diagram of a square root value calculation circuit showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram of the logic circuit of FIG. 4;

FIG. 6 is a flowchart of the basic algorithm in FIG. 4;

[Explanation of symbols]

1 First register 2 Right shift register 3 Second register 10 Square root value generation circuit 20 Multiplier 21 Subtractor 30 Clock control circuit 31 AND gate 40 Logic circuit F Negative flag G Positive flag

Claims (2)

[Claims] 1. A first register that stores an unexpanded root value, a right shift register that operates to right shift based on a clock signal and outputs a value of a power of 2, and a right shift register that operates based on the clock signal to output a value of a power of 2. The output of the shift register is 2i
(where i is an integer), the 2i digit is logic “1”
and a second register for storing a square root value that outputs a value in which all digits below the 2i-1 digit are logic "0"; a multiplier that squares the output of the second register; and a multiplier that squares the output of the second register; a subtracter that subtracts the outputs of the register and the multiplier and outputs positive/negative information of the subtraction result; and performs addition/subtraction by taking exclusive logic of the outputs of the right shift register and the second register based on the positive/negative information; A square root value calculation circuit comprising: a square root value generation circuit that updates the contents of the second register according to the addition/subtraction results. 2. A first register that stores an unexpanded root value; a right shift register that performs a right shift operation based on a clock signal and outputs a value of a power of 2; and a right shift register that outputs a value of a power of 2; The output of the right shift register operates based on the clock control circuit to control and the output clock signal of the clock control circuit, and the output of the right shift register is 2i
; integer), then 2i digits are logical “1” and 2i-
A second register for storing a square root value that outputs a value in which all digits below the first digit are logical "0", and a logical sum of the outputs of the right shift register and the second register;
a logic circuit that updates the contents of the second register according to the addition result; a multiplier that squares the output of the logic circuit; A square root value calculation circuit comprising: a subtracter that outputs positive/negative information to the clock control circuit.